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Enable yosys sim support for clock signals in hierarchical designs

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This commit is contained in:
Jannis Harder 2023-01-11 18:02:45 +01:00
parent 06c36d5bb0
commit 6398938e6a
2 changed files with 8 additions and 2 deletions
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5
sbysrc/sby_sim.py
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@ -63,7 +63,10 @@ def sim_witness_trace(prefix, task, engine_idx, witness_file, *, append, deps=()
for assertion in summary["assertions"]:
if task.design:
prop = task.design.properties_by_path[tuple(assertion["path"])]
try:
prop = task.design.properties_by_path[tuple(assertion["path"])]
except KeyError:
prop = None
else:
prop = None