3
0
Fork 0
mirror of https://github.com/YosysHQ/sby.git synced 2025-04-05 22:14:08 +00:00

Fix syntax errors

This commit is contained in:
Miodrag Milanovic 2021-01-26 09:09:43 +01:00
parent 091222b87f
commit 605db98382

View file

@ -14,9 +14,9 @@ module top (
input clk, input clk,
input [7:0] addr, input [7:0] addr,
input [7:0] wdata, input [7:0] wdata,
output [7:0] rdata, output [7:0] rdata
); );
const rand reg [7:0] test_addr; rand const reg [7:0] test_addr;
reg [7:0] test_data; reg [7:0] test_data;
reg test_valid = 0; reg test_valid = 0;
@ -42,7 +42,7 @@ module memory (
input clk, input clk,
input [7:0] addr, input [7:0] addr,
input [7:0] wdata, input [7:0] wdata,
output [7:0] rdata, output [7:0] rdata
); );
reg [7:0] mem [0:255]; reg [7:0] mem [0:255];