Add formal_bind example

Demonstrate binding SVA properties to a VHDL design.
Mention example code (with snippets) in section on Verific.

docs/examples/vhd/formal_bind.sby

@@ -0,0 +1,20 @@
+[tasks]
+bmc
+cover
+
+[options]
+bmc: mode bmc
+cover: mode cover
+depth 16
+
+[engines]
+smtbmc bitwuzla
+
+[script]
+verific -vhdl updowncount.vhd
+verific -sv formal_bind.sv
+prep -top updowncount
+
+[files]
+updowncount.vhd
+formal_bind.sv