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sby_design: Extract total memory size and forall usage
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parent
157bb156c0
commit
5014d74023
3 changed files with 30 additions and 14 deletions
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@ -194,7 +194,7 @@ def run(mode, task, engine_idx, engine):
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match = re.match(r"^## [0-9: ]+ Assert failed in (\S+): (\S+) \((\S+)\)", line)
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if match:
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cell_name = match[3]
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prop = task.design_hierarchy.find_property_by_cellname(cell_name, trans_dict=smt2_trans)
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prop = task.design.hierarchy.find_property_by_cellname(cell_name, trans_dict=smt2_trans)
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prop.status = "FAIL"
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last_prop.append(prop)
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return line
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@ -202,7 +202,7 @@ def run(mode, task, engine_idx, engine):
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match = re.match(r"^## [0-9: ]+ Reached cover statement at (\S+) \((\S+)\) in step \d+.", line)
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if match:
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cell_name = match[2]
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prop = task.design_hierarchy.find_property_by_cellname(cell_name, trans_dict=smt2_trans)
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prop = task.design.hierarchy.find_property_by_cellname(cell_name, trans_dict=smt2_trans)
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prop.status = "PASS"
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last_prop.append(prop)
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return line
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@ -218,7 +218,7 @@ def run(mode, task, engine_idx, engine):
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match = re.match(r"^## [0-9: ]+ Unreached cover statement at (\S+) \((\S+)\).", line)
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if match:
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cell_name = match[2]
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prop = task.design_hierarchy.find_property_by_cellname(cell_name, trans_dict=smt2_trans)
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prop = task.design.hierarchy.find_property_by_cellname(cell_name, trans_dict=smt2_trans)
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prop.status = "FAIL"
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return line
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@ -250,7 +250,7 @@ def run(mode, task, engine_idx, engine):
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if excess_traces > 0:
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task.summary.append(f"""and {excess_traces} further trace{"s" if excess_traces > 1 else ""}""")
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elif proc_status == "PASS" and mode == "bmc":
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for prop in task.design_hierarchy:
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for prop in task.design.hierarchy:
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if prop.type == prop.Type.ASSERT and prop.status == "UNKNOWN":
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prop.status = "PASS"
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@ -285,7 +285,7 @@ def run(mode, task, engine_idx, engine):
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assert False
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if task.basecase_pass and task.induction_pass:
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for prop in task.design_hierarchy:
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for prop in task.design.hierarchy:
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if prop.type == prop.Type.ASSERT and prop.status == "UNKNOWN":
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prop.status = "PASS"
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task.update_status("PASS")
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