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sby_design: Extract total memory size and forall usage
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parent
157bb156c0
commit
5014d74023
3 changed files with 30 additions and 14 deletions
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@ -99,7 +99,16 @@ class SbyModule:
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return prop
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raise KeyError(f"No such property: {cell_name}")
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@dataclass
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class SbyDesign:
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hierarchy: SbyModule = None
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memory_bits: int = 0
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forall: bool = False
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def design_hierarchy(filename):
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design = SbyDesign(hierarchy=None)
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design_json = json.load(filename)
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def make_mod_hier(instance_name, module_name, hierarchy=""):
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# print(instance_name,":", module_name)
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@ -125,13 +134,19 @@ def design_hierarchy(filename):
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if sort["type"][0] != '$' or sort["type"].startswith("$paramod"):
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for cell in sort["cells"]:
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mod.submodules[cell["name"]] = make_mod_hier(cell["name"], sort["type"], hierarchy=sub_hierarchy)
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if sort["type"] in ["$mem", "$mem_v2"]:
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for cell in sort["cells"]:
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design.memory_bits += int(cell["parameters"]["WIDTH"], 2) * int(cell["parameters"]["SIZE"], 2)
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if sort["type"] in ["$allconst", "$allseq"]:
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design.forall = True
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return mod
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for m in design_json["modules"]:
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attrs = m["attributes"]
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if "top" in attrs and int(attrs["top"]) == 1:
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hierarchy = make_mod_hier(m["name"], m["name"])
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return hierarchy
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design.hierarchy = make_mod_hier(m["name"], m["name"])
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return design
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else:
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raise ValueError("Cannot find top module")
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@ -140,10 +155,11 @@ def main():
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if len(sys.argv) != 2:
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print(f"""Usage: {sys.argv[0]} design.json""")
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with open(sys.argv[1]) as f:
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d = design_hierarchy(f)
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print("Design Hierarchy:", d)
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for p in d.get_property_list():
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design = design_hierarchy(f)
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print("Design Hierarchy:", design.hierarchy)
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for p in design.hierarchy.get_property_list():
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print("Property:", p)
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print("Memory Bits:", design.memory_bits)
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if __name__ == '__main__':
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main()
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