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Merge pull request #278 from YosysHQ/krys/docs_verific

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Add note on docs to clarify verific support
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N. Engelhardt 2025-03-03 15:09:36 +00:00 committed by GitHub
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9
docs/source/quickstart.rst
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@ -297,7 +297,14 @@ As verification properties become more complex and check longer sequences, the
additional effort of hand-coding without SVA properties becomes much more additional effort of hand-coding without SVA properties becomes much more
difficult. Using a parser such as Verific supports these checks *without* difficult. Using a parser such as Verific supports these checks *without*
having to write out potentially complicated state machines. Verific is included having to write out potentially complicated state machines. Verific is included
for use in the *Tabby CAD Suite*. for use in the *Tabby CAD Suite*.
.. note::
The Verific frontend for Yosys requires the commercial `Tabby CAD Suite`_.
This is not the same as simply having a Verific license when using Yosys.
.. _Tabby CAD Suite: https://www.yosyshq.com/tabby-cad-datasheet
Further information Further information
******************* *******************

8
docs/source/verific.rst
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@ -2,6 +2,14 @@
SystemVerilog, VHDL, SVA SystemVerilog, VHDL, SVA
======================== ========================
.. note::
This document describes features only available with the commercial `Tabby
CAD Suite`_ and the included Verific frontend. This is not the same as simply
having a Verific license when using Yosys.
.. _Tabby CAD Suite: https://www.yosyshq.com/tabby-cad-datasheet
Run ``verific -sv <files>`` in the ``[script]`` section of you ``.sby`` file Run ``verific -sv <files>`` in the ``[script]`` section of you ``.sby`` file
to read a SystemVerilog source file, and ``verific -vhdl <files>`` to read a to read a SystemVerilog source file, and ``verific -vhdl <files>`` to read a
VHDL source file. VHDL source file.

8
docs/source/verilog.rst
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@ -20,10 +20,10 @@ within the core.
`endif `endif
endmodule endmodule
The ``bind()`` operator can also be used when using the Verific front end. The ``bind()`` operator can also be used when using the Verific front end. This
This will provide an option to attach formal properties to a given piece will provide an option to attach formal properties to a given piece of logic,
of logic, without actually modifying the module in question to do so as without actually modifying the module in question to do so as we did in the
we did in the example above. example above. Refer to :doc:`verific` for more on the Verific front end.
SystemVerilog Immediate Assertions SystemVerilog Immediate Assertions
---------------------------------- ----------------------------------