mirrors/sby
3
0
Fork 0
mirror of https://github.com/YosysHQ/sby.git synced 2025-04-04 13:54:07 +00:00
Code Activity

Merge pull request #278 from YosysHQ/krys/docs_verific

Browse source 
Add note on docs to clarify verific support
This commit is contained in:
N. Engelhardt 2025-03-03 15:09:36 +00:00 committed by GitHub
parent 26b387466d 7f1853bd78
commit 4d92762d5a
No known key found for this signature in database
GPG key ID: B5690EEEBB952194
3 changed files with 20 additions and 5 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

9
docs/source/quickstart.rst
View file

@ -297,7 +297,14 @@ As verification properties become more complex and check longer sequences, the
additional effort of hand-coding without SVA properties becomes much more
difficult. Using a parser such as Verific supports these checks *without*
having to write out potentially complicated state machines. Verific is included
for use in the *Tabby CAD Suite*.
for use in the *Tabby CAD Suite*.
.. note::
The Verific frontend for Yosys requires the commercial `Tabby CAD Suite`_.
This is not the same as simply having a Verific license when using Yosys.
.. _Tabby CAD Suite: https://www.yosyshq.com/tabby-cad-datasheet
Further information
*******************

8
docs/source/verific.rst
View file

@ -2,6 +2,14 @@
SystemVerilog, VHDL, SVA
========================
.. note::
This document describes features only available with the commercial `Tabby
CAD Suite`_ and the included Verific frontend. This is not the same as simply
having a Verific license when using Yosys.
.. _Tabby CAD Suite: https://www.yosyshq.com/tabby-cad-datasheet
Run ``verific -sv <files>`` in the ``[script]`` section of you ``.sby`` file
to read a SystemVerilog source file, and ``verific -vhdl <files>`` to read a
VHDL source file.

8
docs/source/verilog.rst
View file

@ -20,10 +20,10 @@ within the core.
`endif
endmodule
The ``bind()`` operator can also be used when using the Verific front end.
This will provide an option to attach formal properties to a given piece
of logic, without actually modifying the module in question to do so as
we did in the example above.
The ``bind()`` operator can also be used when using the Verific front end. This
will provide an option to attach formal properties to a given piece of logic,
without actually modifying the module in question to do so as we did in the
example above. Refer to :doc:`verific` for more on the Verific front end.
SystemVerilog Immediate Assertions
----------------------------------