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Use the test Makefile for all examples

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* Rename and move sbysrc/demo[123].sby to docs/examples/demos
    * Make them use multiple tasks for multiple engines
* Scan docs/examples for sby files for make test
* `make ci` is now `NOSKIP` by default
* Skip scripts using `verific` w/o yosys verific support
    * This does not fail even with NOSKIP set
This commit is contained in:
Jannis Harder 2022-06-13 13:20:33 +02:00
parent 1d21513a47
commit 499371fd39
18 changed files with 77 additions and 92 deletions
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21
sbysrc/demo1.sby
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@ -1,21 +0,0 @@
[options]
mode bmc
depth 10
wait on
[engines]
smtbmc yices
smtbmc boolector -ack
smtbmc --nomem z3
abc bmc3
[script]
read_verilog -formal -norestrict -assume-asserts picorv32.v
read_verilog -formal axicheck.v
prep -top testbench
[files]
picorv32.v ../extern/picorv32.v
axicheck.v ../extern/axicheck.v

21
sbysrc/demo2.sby
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@ -1,21 +0,0 @@
[options]
mode prove
wait on
[engines]
aiger suprove
aiger avy
[script]
read_verilog -formal demo.v
prep -top top
[file demo.v]
module top(input clk, input up, down);
reg [4:0] counter = 0;
always @(posedge clk) begin
if (up && counter != 10) counter <= counter + 1;
if (down && counter != 0) counter <= counter - 1;
end
assert property (counter != 15);
endmodule

53
sbysrc/demo3.sby
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@ -1,53 +0,0 @@
[options]
depth 10
mode bmc
[engines]
smtbmc yices
[script]
read_verilog -formal demo.v
prep -top top
[file demo.v]
module top (
input clk,
input [7:0] addr,
input [7:0] wdata,
output [7:0] rdata
);
rand const reg [7:0] test_addr;
reg [7:0] test_data;
reg test_valid = 0;
always @(posedge clk) begin
if (addr == test_addr) begin
if (test_valid)
assert(test_data == rdata);
test_data <= wdata;
test_valid <= 1;
end
end
memory uut (
.clk (clk ),
.addr (addr ),
.wdata(wdata),
.rdata(rdata)
);
endmodule
module memory (
input clk,
input [7:0] addr,
input [7:0] wdata,
output [7:0] rdata
);
reg [7:0] mem [0:255];
always @(posedge clk)
mem[addr] <= wdata;
assign rdata = mem[addr];
endmodule

1
sbysrc/sby.py
View file

@ -381,6 +381,7 @@ if dump_taskinfo:
taskinfo[taskname or ""] = {
"mode": cfg.options.get("mode"),
"engines": cfg.engines,
"script": cfg.script,
}
print(json.dumps(taskinfo, indent=2))
sys.exit(0)