Use the test Makefile for all examples

* Rename and move sbysrc/demo[123].sby to docs/examples/demos
    * Make them use multiple tasks for multiple engines
* Scan docs/examples for sby files for make test
* `make ci` is now `NOSKIP` by default
* Skip scripts using `verific` w/o yosys verific support
    * This does not fail even with NOSKIP set

docs/examples/demos/up_down_counter.sby

@@ -0,0 +1,24 @@
+[tasks]
+suprove
+avy
+
+[options]
+mode prove
+
+[engines]
+suprove: aiger suprove
+avy: aiger avy
+
+[script]
+read_verilog -formal demo.v
+prep -top top
+
+[file demo.v]
+module top(input clk, input up, down);
+  reg [4:0] counter = 0;
+  always @(posedge clk) begin
+    if (up && counter != 10) counter <= counter + 1;
+    if (down && counter != 0) counter <= counter - 1;
+  end
+  assert property (counter != 15);
+endmodule