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Include verilog source files for demo1.sby

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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
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Claire Wolf 2020-07-21 13:01:36 +02:00
parent 59a8fbdf36
commit 494f84b0ab
4 changed files with 3259 additions and 5 deletions
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sbysrc/demo1.sby
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@ -16,6 +16,6 @@ read_verilog -formal axicheck.v
prep -top testbench
[files]
picorv32.v ~/Work/picorv32/picorv32.v
axicheck.v ~/Work/picorv32/scripts/smtbmc/axicheck.v
picorv32.v ../extern/picorv32.v
axicheck.v ../extern/axicheck.v