mirrors/sby
3
0
Fork 0
mirror of https://github.com/YosysHQ/sby.git synced 2025-04-23 13:25:31 +00:00
Code Activity

Include verilog source files for demo1.sby

Browse source 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
This commit is contained in:
Claire Wolf 2020-07-21 13:01:36 +02:00
parent 59a8fbdf36
commit 494f84b0ab
4 changed files with 3259 additions and 5 deletions
Download patch file Download diff file Expand all files Collapse all files

6
Makefile
View file

@ -47,13 +47,13 @@ test: \
test_quickstart_demo test_quickstart_cover test_quickstart_prove test_quickstart_memory
test_demo1:
python3 sbysrc/sby.py -f sbysrc/demo1.sby
cd sbysrc && python3 sby.py -f demo1.sby
test_demo2:
python3 sbysrc/sby.py -f sbysrc/demo2.sby
cd sbysrc && python3 sby.py -f demo2.sby
test_demo3:
python3 sbysrc/sby.py -f sbysrc/demo3.sby
cd sbysrc && python3 sby.py -f demo3.sby
test_abstract_abstr:
cd docs/examples/abstract && python3 ../../../sbysrc/sby.py -f abstr.sby