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Update remaining quickstart examples

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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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Clifford Wolf 2018-06-29 18:21:38 +02:00
parent 45a11da8ea
commit 2fa29974dd
7 changed files with 22 additions and 14 deletions
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49
docs/examples/quickstart/prove.v
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@ -1,49 +0,0 @@
module testbench (
input clk,
input reset,
input [7:0] din,
output reg [7:0] dout
);
demo uut (
.clk (clk ),
.reset(reset),
.din (din ),
.dout (dout ),
);
initial assume (reset);
assert property (reset || !dout[1:0]);
endmodule
module demo (
input clk,
input reset,
input [7:0] din,
output reg [7:0] dout
);
reg [7:0] buffer;
reg [1:0] state;
always @(posedge clk) begin
if (reset) begin
dout <= 0;
state <= 0;
end else
case (state)
0: begin
buffer <= din;
state <= 1;
end
1: begin
if (buffer[1:0])
buffer <= buffer + 1;
else
state <= 2;
end
2: begin
dout <= dout + buffer;
state <= 0;
end
endcase
end
endmodule