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Add make_model option to generate models not required by the task

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Useful to do custom things (like counter example minimization) but still
use sby's flow to prepare models.
This commit is contained in:
Jannis Harder 2022-08-02 17:08:53 +02:00
parent 22585b33dc
commit 231f0b80aa
2 changed files with 18 additions and 2 deletions
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6
docs/source/reference.rst
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@ -153,6 +153,12 @@ options are:
| ``tbtop`` | All | The top module for generated Verilog test benches, as |
| | | hierarchical path relative to the design top module. |
+------------------+------------+---------------------------------------------------------+
| ``make_model`` | All | Force generation of the named formal models. Takes a |
| | | comma-separated list of model names. For a model |
| | | ``<name>`` this will generate the |
| | | ``model/design_<name>.*`` files within the working |
| | | directory, even when not required to run the task. |
+------------------+------------+---------------------------------------------------------+
| ``smtc`` | ``bmc``, | Pass this ``.smtc`` file to the smtbmc engine. All |
| | ``prove``, | other engines are disabled when this option is used. |
| | ``cover`` | Default: None |