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Gus Smith 2025-12-15 12:41:38 -08:00
parent 358ccf3ab6
commit 1ee552a502
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tests/staged_sim_and_verif/Req_Ack.sv
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@ -11,7 +11,7 @@ module DUT (
// Deterministic initial state
initial begin
reqs_seen = 2'b00;
reqs_seen = 2'b0;
cycle_count = 32'b0;
end