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Replace (read_)ilang with (read_)rtlil

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This commit is contained in:
Krystine Sherwin 2024-11-05 12:55:09 +13:00
parent daed0e1544
commit 176e59c3d8
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2 changed files with 5 additions and 5 deletions
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8
sbysrc/sby_core.py
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@ -1004,7 +1004,7 @@ class SbyTask(SbyConfig):
if model_name == "prep":
with open(f"""{self.workdir}/model/design_prep.ys""", "w") as f:
print(f"# running in {self.workdir}/model/", file=f)
print(f"""read_ilang design.il""", file=f)
print(f"""read_rtlil design.il""", file=f)
if not self.opt_skip_prep:
print("scc -select; simplemap; select -clear", file=f)
print("memory_nordff", file=f)
@ -1084,7 +1084,7 @@ class SbyTask(SbyConfig):
if re.match(r"^smt2(_syn)?(_nomem)?(_stbv|_stdt)?$", model_name):
with open(f"{self.workdir}/model/design_{model_name}.ys", "w") as f:
print(f"# running in {self.workdir}/model/", file=f)
print(f"""read_ilang design_prep.il""", file=f)
print(f"""read_rtlil design_prep.il""", file=f)
print("hierarchy -smtcheck", file=f)
print("delete */t:$print", file=f)
print("formalff -assume", file=f)
@ -1118,7 +1118,7 @@ class SbyTask(SbyConfig):
if re.match(r"^btor(_syn)?(_nomem)?$", model_name):
with open(f"{self.workdir}/model/design_{model_name}.ys", "w") as f:
print(f"# running in {self.workdir}/model/", file=f)
print(f"""read_ilang design_prep.il""", file=f)
print(f"""read_rtlil design_prep.il""", file=f)
print("hierarchy -simcheck", file=f)
print("delete */t:$print", file=f)
print("formalff -assume", file=f)
@ -1154,7 +1154,7 @@ class SbyTask(SbyConfig):
if model_name == "aig":
with open(f"{self.workdir}/model/design_aiger.ys", "w") as f:
print(f"# running in {self.workdir}/model/", file=f)
print("read_ilang design_prep.il", file=f)
print("read_rtlil design_prep.il", file=f)
print("delete */t:$print", file=f)
print("hierarchy -simcheck", file=f)
print("formalff -assume", file=f)

2
tools/cexenum/cexenum.py
View file

@ -196,7 +196,7 @@ class AigModel(tl.process.Process):
self[tl.LogContext].scope = "aiger"
(App.cache_dir / "design_aiger.ys").write_text(
lines(
"read_ilang ../model/design_prep.il",
"read_rtlil ../model/design_prep.il",
"hierarchy -simcheck",
"flatten",
"setundef -undriven -anyseq",