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https://github.com/YosysHQ/sby.git
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Replace (read_)ilang with (read_)rtlil
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parent
daed0e1544
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@ -1004,7 +1004,7 @@ class SbyTask(SbyConfig):
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if model_name == "prep":
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with open(f"""{self.workdir}/model/design_prep.ys""", "w") as f:
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print(f"# running in {self.workdir}/model/", file=f)
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print(f"""read_ilang design.il""", file=f)
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print(f"""read_rtlil design.il""", file=f)
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if not self.opt_skip_prep:
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print("scc -select; simplemap; select -clear", file=f)
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print("memory_nordff", file=f)
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@ -1084,7 +1084,7 @@ class SbyTask(SbyConfig):
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if re.match(r"^smt2(_syn)?(_nomem)?(_stbv|_stdt)?$", model_name):
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with open(f"{self.workdir}/model/design_{model_name}.ys", "w") as f:
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print(f"# running in {self.workdir}/model/", file=f)
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print(f"""read_ilang design_prep.il""", file=f)
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print(f"""read_rtlil design_prep.il""", file=f)
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print("hierarchy -smtcheck", file=f)
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print("delete */t:$print", file=f)
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print("formalff -assume", file=f)
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@ -1118,7 +1118,7 @@ class SbyTask(SbyConfig):
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if re.match(r"^btor(_syn)?(_nomem)?$", model_name):
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with open(f"{self.workdir}/model/design_{model_name}.ys", "w") as f:
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print(f"# running in {self.workdir}/model/", file=f)
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print(f"""read_ilang design_prep.il""", file=f)
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print(f"""read_rtlil design_prep.il""", file=f)
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print("hierarchy -simcheck", file=f)
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print("delete */t:$print", file=f)
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print("formalff -assume", file=f)
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@ -1154,7 +1154,7 @@ class SbyTask(SbyConfig):
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if model_name == "aig":
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with open(f"{self.workdir}/model/design_aiger.ys", "w") as f:
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print(f"# running in {self.workdir}/model/", file=f)
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print("read_ilang design_prep.il", file=f)
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print("read_rtlil design_prep.il", file=f)
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print("delete */t:$print", file=f)
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print("hierarchy -simcheck", file=f)
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print("formalff -assume", file=f)
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@ -196,7 +196,7 @@ class AigModel(tl.process.Process):
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self[tl.LogContext].scope = "aiger"
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(App.cache_dir / "design_aiger.ys").write_text(
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lines(
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"read_ilang ../model/design_prep.il",
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"read_rtlil ../model/design_prep.il",
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"hierarchy -simcheck",
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"flatten",
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"setundef -undriven -anyseq",
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