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Merge pull request #341 from jix/cycle_width_option

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Add `cycle_width` option for sim's new `-width` option
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Jannis Harder 2025-10-20 18:52:09 +02:00 • committed by GitHub
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3 changed files with 8 additions and 0 deletions
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3
docs/source/reference.rst
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@ -160,6 +160,9 @@ options are:
| ``fst`` | All | Generate FST traces using Yosys's sim command. | | ``fst`` | All | Generate FST traces using Yosys's sim command. |
| | | Values: ``on``, ``off``. Default: ``off`` | | | | Values: ``on``, ``off``. Default: ``off`` |
+-------------------+------------+---------------------------------------------------------+ +-------------------+------------+---------------------------------------------------------+
| ``cycle_width`` | All | Cycle width used by Yosys's sim command. |
| | | Values: even numbers >= 2. Default: ``10`` |
+-------------------+------------+---------------------------------------------------------+
| ``aigsmt`` | All | Which SMT2 solver to use for converting AIGER witnesses | | ``aigsmt`` | All | Which SMT2 solver to use for converting AIGER witnesses |
| | | to counter example traces. Use ``none`` to disable | | | | to counter example traces. Use ``none`` to disable |
| | | conversion of AIGER witnesses. Default: ``yices`` | | | | conversion of AIGER witnesses. Default: ``yices`` |

3
sbysrc/sby_core.py
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@ -1395,6 +1395,9 @@ class SbyTask(SbyConfig):
self.handle_bool_option("vcd", True) self.handle_bool_option("vcd", True)
self.handle_bool_option("vcd_sim", False) self.handle_bool_option("vcd_sim", False)
self.handle_bool_option("fst", False) self.handle_bool_option("fst", False)
self.handle_int_option("cycle_width", 10)
if self.opt_cycle_width < 2 or self.opt_cycle_width % 2 != 0:
self.error(f"cycle_width option must be an even number >= 2, but is {self.opt_cycle_width}")
self.handle_bool_option("witrename", True) self.handle_bool_option("witrename", True)
self.handle_bool_option("aigfolds", False) self.handle_bool_option("aigfolds", False)

2
sbysrc/sby_sim.py
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@ -44,6 +44,8 @@ def sim_witness_trace(prefix, task, engine_idx, witness_file, *, append, inducti
sim_args = "" sim_args = ""
if inductive: if inductive:
sim_args += " -noinitstate" sim_args += " -noinitstate"
if task.opt_cycle_width != 10:
formats.append(f"-width {task.opt_cycle_width}")
print(f"sim -hdlname -summary {trace_name}.json -append {append}{sim_args} -r {trace_name}.yw {' '.join(formats)}", file=f) print(f"sim -hdlname -summary {trace_name}.json -append {append}{sim_args} -r {trace_name}.yw {' '.join(formats)}", file=f)
def exit_callback(retval): def exit_callback(retval):