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Add primegen example

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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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Clifford Wolf 2018-03-03 19:58:35 +01:00
parent 35a5fb94f1
commit 0f21d01460
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docs/examples/puzzles/primegen.sby Normal file
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[options]
mode cover
depth 1
[engines]
smtbmc --dumpsmt2 --stbv z3
[script]
read_verilog -formal primegen.v
prep -top primegen
[files]
primegen.v