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Fix bug in /examples/quickstart/prove.v
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@ -22,7 +22,7 @@ module demo (
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output reg [7:0] dout
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);
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reg [7:0] buffer;
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reg [2:0] state;
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reg [1:0] state;
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always @(posedge clk) begin
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if (reset) begin
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@ -30,17 +30,17 @@ module demo (
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state <= 0;
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end else
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case (state)
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3'b 001: begin
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0: begin
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buffer <= din;
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state <= 1;
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end
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3'b 010: begin
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1: begin
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if (buffer[1:0])
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buffer <= buffer + 1;
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else
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state <= 2;
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end
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3'b 100: begin
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2: begin
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dout <= dout + buffer;
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state <= 0;
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end
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