Revert "Rework file based on new understanding of make"

This reverts commit 2b38c31936.

tests/staged_sim_and_verif/skip_staged_flow.sby

@@ -0,0 +1,59 @@
+[tasks]
+stage_1_init init
+stage_1_fv fv
+stage_2_init init
+stage_2_fv fv
+
+[options]
+init:
+mode prep
+
+fv:
+mode cover
+depth 40
+
+--
+
+[engines]
+init: none
+fv: smtbmc
+
+[script]
+stage_1_init:
+verific -formal Req_Ack.sv
+hierarchy -top DUT
+
+stage_1_fv:
+read_rtlil design_prep.il
+# This selection computes (all things with phase)-(all things with phase=1)
+# to remove all phased SVA constructs not intended for phase 1.
+select */a:phase */a:phase=1 %d
+delete
+
+stage_2_init:
+read_rtlil design_prep.il
+sim -a -w -scope DUT -r trace0.yw
+
+stage_2_fv:
+read_rtlil design_prep.il
+# This selection computes (all things with phase)-(all things with phase=2)
+# to remove all phased SVA constructs not intended for phase 2.
+select */a:phase */a:phase=2 %d
+delete
+
+--
+
+[files]
+
+stage_1_init:
+Req_Ack.sv
+
+stage_1_fv:
+skip_staged_flow_stage_1_init/model/design_prep.il
+
+stage_2_init:
+skip_staged_flow_stage_1_init/model/design_prep.il
+skip_staged_flow_stage_1_fv/engine_0/trace0.yw
+
+stage_2_fv:
+skip_staged_flow_stage_2_init/model/design_prep.il

tests/staged_sim_and_verif/staged_sim_and_verif.sby

@@ -1,59 +1,14 @@
-[tasks]
-stage_1_init init
-stage_1_fv fv
-stage_2_init init
-stage_2_fv fv
-
 [options]
-init:
-mode prep
-
-fv:
 mode cover
-depth 40
-
---
+depth 1
 
 [engines]
-init: none
-fv: smtbmc
+smtbmc
 
 [script]
-stage_1_init:
+# Minimal job so dumptaskinfo picks up the tools this flow requires.
 verific -formal Req_Ack.sv
-hierarchy -top DUT
-
-stage_1_fv:
-read_rtlil design_prep.il
-# This selection computes (all things with phase)-(all things with phase=1)
-# to remove all phased SVA constructs not intended for phase 1.
-select */a:phase */a:phase=1 %d
-delete
-
-stage_2_init:
-read_rtlil design_prep.il
-sim -a -w -scope DUT -r trace0.yw
-
-stage_2_fv:
-read_rtlil design_prep.il
-# This selection computes (all things with phase)-(all things with phase=2)
-# to remove all phased SVA constructs not intended for phase 2.
-select */a:phase */a:phase=2 %d
-delete
-
---
+prep -top DUT
 
 [files]
-
-stage_1_init:
 Req_Ack.sv
-
-stage_1_fv:
-staged_sim_and_verif_stage_1_init/model/design_prep.il
-
-stage_2_init:
-staged_sim_and_verif_stage_1_init/model/design_prep.il
-staged_sim_and_verif_stage_1_fv/engine_0/trace0.yw
-
-stage_2_fv:
-staged_sim_and_verif_stage_2_init/model/design_prep.il

tests/staged_sim_and_verif/staged_sim_and_verif.sh

@@ -4,10 +4,10 @@ set -euo pipefail
 SCRIPT_DIR="$(cd "$(dirname "$0")" && pwd)"
 cd "$SCRIPT_DIR"
 
-FLOW_FILE="staged_sim_and_verif.sby"
+FLOW_FILE="skip_staged_flow.sby"
 
 # Clean previous runs so we always exercise the full staged flow.
-rm -rf staged_sim_and_verif_stage_1_init staged_sim_and_verif_stage_1_fv staged_sim_and_verif_stage_2_init staged_sim_and_verif_stage_2_fv
+rm -rf skip_staged_flow_stage_1_init skip_staged_flow_stage_1_fv skip_staged_flow_stage_2_init skip_staged_flow_stage_2_fv
 
 run_task() {
     python3 "$SBY_MAIN" -f "$FLOW_FILE" "$1"