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Revive an independent prep stage
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parent
9389f3a7d6
commit
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2 changed files with 31 additions and 5 deletions
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@ -1,4 +1,5 @@
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[tasks]
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[tasks]
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prep
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stage_1
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stage_1
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stage_2
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stage_2
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stage_3_init
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stage_3_init
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@ -6,8 +7,12 @@ stage_3a_cover
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stage_3b_assert
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stage_3b_assert
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[options]
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[options]
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prep:
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mode prep
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stage_1:
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stage_1:
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mode cover
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mode cover
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skip_prep on
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stage_2:
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stage_2:
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mode cover
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mode cover
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@ -30,17 +35,31 @@ skip_prep on
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[engines]
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[engines]
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smtbmc
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smtbmc
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prep:
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none
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stage_3_init:
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stage_3_init:
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none
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none
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--
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--
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[script]
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[script]
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stage_1:
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# This separate prep step generates model_prep.il, which is our ground-truth
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# design file from which all other checkpoints are derived. It is essential
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# to have at least one prep step in `mode prep`, as we must produce a .il file
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# which has had the SBY-internal prep routine run on it. Any file written
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# in the user-provided script below will represent the state of the design
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# *before* the SBY prep routine. (Note that the `prep` pass below is *not*
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# the SBY prep routine, but just the Yosys synthesis pass.)
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prep:
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verific -formal Req_Ack.sv
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verific -formal Req_Ack.sv
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hierarchy -top DUT
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hierarchy -top DUT
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prep
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prep
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stage_1:
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read_rtlil design_prep.il
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# Write checkpoint file.
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# Write checkpoint file.
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write_rtlil stage_1_init.il
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write_rtlil stage_1_init.il
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@ -50,12 +69,15 @@ select */c:phase* */c:phase1* %d
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delete
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delete
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stage_2:
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stage_2:
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# Read the stage 1 checkpoint, and then use the stage 1 trace to simulate up
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# to the end of stage 1.
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# Note that, in stage 2, we do not use -noinitstate on sim, as this first
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# simulation begins at t=0 and thus $initstate cells should be active. All
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# future calls to sim should include -noinitstate.
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read_rtlil stage_1_init.il
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read_rtlil stage_1_init.il
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# Note that, in stage 2, we do not use -noinitstate, as this first simulation
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# begins at t=0. All future calls to sim should include -noinitstate.
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sim -a -w -scope DUT -r trace0.yw
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sim -a -w -scope DUT -r trace0.yw
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write_rtlil stage_2_init.il
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write_rtlil stage_2_init.il
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select */c:phase* */c:phase2* %d
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select */c:phase* */c:phase2* %d
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delete
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delete
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@ -82,9 +104,12 @@ delete
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[files]
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[files]
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stage_1:
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prep:
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Req_Ack.sv
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Req_Ack.sv
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stage_1:
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skip_staged_flow_prep/model/design_prep.il
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stage_2:
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stage_2:
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skip_staged_flow_stage_1/src/stage_1_init.il
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skip_staged_flow_stage_1/src/stage_1_init.il
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skip_staged_flow_stage_1/engine_0/trace0.yw
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skip_staged_flow_stage_1/engine_0/trace0.yw
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@ -7,6 +7,7 @@ run_task() {
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python3 "$SBY_MAIN" -f "$FLOW_FILE" "$1"
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python3 "$SBY_MAIN" -f "$FLOW_FILE" "$1"
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}
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}
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run_task prep
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run_task stage_1
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run_task stage_1
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run_task stage_2
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run_task stage_2
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run_task stage_3_init
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run_task stage_3_init
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