913 lines
31 KiB
Rust
913 lines
31 KiB
Rust
// SPDX-License-Identifier: LGPL-3.0-or-later
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// See Notices.txt for copyright information
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use cpu::{
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config::{CpuConfig, UnitConfig},
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next_pc::{
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CallStackOp, DecodeToPostDecodeInterface, DecodeToPostDecodeInterfaceInner,
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FETCH_BLOCK_ID_WIDTH, NextPcToFetchInterface, NextPcToFetchInterfaceInner,
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PostDecodeOutputInterface, RetireToNextPcInterface, RetireToNextPcInterfaceInner,
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RetireToNextPcInterfacePerInsn, WipDecodedInsn, WipDecodedInsnKind, next_pc,
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},
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unit::UnitKind,
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util::array_vec::ArrayVec,
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};
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use fayalite::{
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prelude::*,
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sim::vcd::VcdWriterDecls,
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util::{DebugAsDisplay, RcWriter},
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};
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use std::{
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cell::Cell,
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collections::{BTreeMap, BTreeSet, VecDeque},
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num::NonZeroUsize,
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u64,
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};
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#[derive(Copy, Clone, Debug)]
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enum MockInsn {
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Nop4,
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Jump { target: u64 },
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CondBranch { target: u64 },
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Call { target: u64 },
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Ret,
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}
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impl MockInsn {
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fn byte_len(self) -> u64 {
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match self {
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MockInsn::Nop4 => 4,
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MockInsn::Jump { .. } => 4,
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MockInsn::CondBranch { .. } => 4,
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MockInsn::Call { .. } => 4,
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MockInsn::Ret => 4,
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}
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}
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const INSNS: &'static [(u64, Self)] = &[
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(0x0, MockInsn::Nop4),
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(0x4, MockInsn::Nop4),
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(0x8, MockInsn::CondBranch { target: 0x4 }),
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(0xC, MockInsn::Call { target: 0x18 }),
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(0x10, MockInsn::Jump { target: 0x14 }),
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(0x14, MockInsn::Jump { target: 0x10 }),
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(0x18, MockInsn::Jump { target: 0x1C }),
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(0x1C, MockInsn::Ret),
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];
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const RETIRE_SEQ_INIT: &'static [RetireSeqEntry] = &[
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RetireSeqEntry {
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pc: 0x0,
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cond_br_taken: None,
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kind: MockInsn::Nop4,
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},
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RetireSeqEntry {
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pc: 0x4,
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cond_br_taken: None,
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kind: MockInsn::Nop4,
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},
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RetireSeqEntry {
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pc: 0x8,
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cond_br_taken: Some(true),
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kind: MockInsn::CondBranch { target: 0x4 },
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},
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RetireSeqEntry {
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pc: 0x4,
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cond_br_taken: None,
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kind: MockInsn::Nop4,
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},
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RetireSeqEntry {
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pc: 0x8,
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cond_br_taken: Some(true),
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kind: MockInsn::CondBranch { target: 0x4 },
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},
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RetireSeqEntry {
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pc: 0x4,
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cond_br_taken: None,
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kind: MockInsn::Nop4,
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},
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RetireSeqEntry {
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pc: 0x8,
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cond_br_taken: Some(true),
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kind: MockInsn::CondBranch { target: 0x4 },
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},
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RetireSeqEntry {
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pc: 0x4,
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cond_br_taken: None,
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kind: MockInsn::Nop4,
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},
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RetireSeqEntry {
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pc: 0x8,
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cond_br_taken: Some(false),
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kind: MockInsn::CondBranch { target: 0x4 },
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},
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RetireSeqEntry {
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pc: 0xC,
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cond_br_taken: None,
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kind: MockInsn::Call { target: 0x18 },
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},
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RetireSeqEntry {
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pc: 0x18,
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cond_br_taken: None,
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kind: MockInsn::Jump { target: 0x1C },
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},
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RetireSeqEntry {
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pc: 0x1C,
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cond_br_taken: None,
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kind: MockInsn::Ret,
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},
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];
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const RETIRE_SEQ_CYCLE: &'static [RetireSeqEntry] = &[
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RetireSeqEntry {
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pc: 0x10,
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cond_br_taken: None,
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kind: MockInsn::Jump { target: 0x14 },
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},
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RetireSeqEntry {
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pc: 0x14,
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cond_br_taken: None,
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kind: MockInsn::Jump { target: 0x10 },
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},
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];
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}
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#[derive(Copy, Clone, Debug)]
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struct RetireSeqEntry {
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pc: u64,
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cond_br_taken: Option<bool>,
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kind: MockInsn,
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}
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#[derive(Clone)]
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struct RetireSeq {
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iter: std::iter::Chain<
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std::slice::Iter<'static, RetireSeqEntry>,
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std::iter::Cycle<std::slice::Iter<'static, RetireSeqEntry>>,
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>,
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}
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impl RetireSeq {
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fn new() -> Self {
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Self {
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iter: MockInsn::RETIRE_SEQ_INIT
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.iter()
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.chain(MockInsn::RETIRE_SEQ_CYCLE.iter().cycle()),
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}
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}
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}
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impl Iterator for RetireSeq {
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type Item = RetireSeqEntry;
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fn next(&mut self) -> Option<Self::Item> {
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self.iter.next().copied()
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}
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}
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#[derive(Debug)]
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struct MockInsns {
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insns: BTreeMap<u64, MockInsn>,
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}
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impl MockInsns {
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fn new() -> Self {
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Self {
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insns: BTreeMap::from_iter(MockInsn::INSNS.iter().copied()),
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}
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}
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fn fetch_block(&self, pc_range: std::ops::Range<u64>) -> impl Iterator<Item = (u64, MockInsn)> {
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self.insns
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.range(pc_range.clone())
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.filter_map(move |(&pc, &insn)| {
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if pc_range.end >= pc + insn.byte_len() {
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Some((pc, insn))
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} else {
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None
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}
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})
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}
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}
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const FETCH_PIPE_QUEUE_SIZE: usize = 5;
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const DEMO_ILLEGAL_INSN_TRAP: u64 = 0xFF000000u64;
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#[hdl]
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struct FetchPipeQueueEntry {
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start_pc: UInt<64>,
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cycles_left: UInt<8>,
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fetch_block_id: UInt<{ FETCH_BLOCK_ID_WIDTH }>,
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}
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impl FetchPipeQueueEntry {
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#[hdl]
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fn default_sim(self) -> SimValue<Self> {
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#[hdl(sim)]
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FetchPipeQueueEntry {
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start_pc: 0u64,
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cycles_left: 0u8,
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fetch_block_id: 0u8,
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}
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}
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fn get_next_delay(delay_sequence_index: &Cell<u64>) -> u8 {
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let index = delay_sequence_index.get();
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delay_sequence_index.set(delay_sequence_index.get().wrapping_add(1));
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// make a pseudo-random number deterministically based on index
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let random = index
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.wrapping_add(1)
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.wrapping_mul(0x18C49126EABE7A0D) // random prime
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.rotate_left(32)
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.wrapping_mul(0x92B38C197608A6B) // random prime
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.rotate_right(60);
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(random % 8) as u8
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}
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}
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#[hdl_module(extern)]
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fn mock_fetch_pipe(config: PhantomConst<CpuConfig>) {
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#[hdl]
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let cd: ClockDomain = m.input();
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#[hdl]
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let from_fetch: NextPcToFetchInterface<PhantomConst<CpuConfig>> =
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m.input(NextPcToFetchInterface[config]);
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#[hdl]
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let to_post_decode: DecodeToPostDecodeInterface<PhantomConst<CpuConfig>> =
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m.output(DecodeToPostDecodeInterface[config]);
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#[hdl]
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let queue_debug: ArrayVec<FetchPipeQueueEntry, ConstUsize<{ FETCH_PIPE_QUEUE_SIZE }>> =
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m.output();
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m.register_clock_for_past(cd.clk);
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m.extern_module_simulation_fn(
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(cd, from_fetch, to_post_decode, queue_debug),
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|(cd, from_fetch, to_post_decode, queue_debug), mut sim| async move {
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// intentionally have a different sequence each time we're reset
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let delay_sequence_index = Cell::new(0);
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sim.resettable(
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cd,
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async |mut sim| {
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sim.write(from_fetch.fetch.ready, false).await;
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sim.write(from_fetch.cancel.ready, false).await;
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sim.write(
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to_post_decode.inner.data,
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to_post_decode.ty().inner.data.HdlNone(),
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)
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.await;
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sim.write(
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queue_debug,
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queue_debug.ty().new_sim(FetchPipeQueueEntry.default_sim()),
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)
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.await;
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},
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|sim, ()| {
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run_fn(
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cd,
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from_fetch,
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to_post_decode,
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queue_debug,
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&delay_sequence_index,
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sim,
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)
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},
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)
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.await;
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},
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);
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#[hdl]
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async fn run_fn(
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cd: Expr<ClockDomain>,
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from_fetch: Expr<NextPcToFetchInterface<PhantomConst<CpuConfig>>>,
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to_post_decode: Expr<DecodeToPostDecodeInterface<PhantomConst<CpuConfig>>>,
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queue_debug: Expr<ArrayVec<FetchPipeQueueEntry, ConstUsize<{ FETCH_PIPE_QUEUE_SIZE }>>>,
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delay_sequence_index: &Cell<u64>,
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mut sim: ExternModuleSimulationState,
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) {
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let config = from_fetch.config.ty();
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let mock_insns = MockInsns::new();
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let mut queue: VecDeque<SimValue<FetchPipeQueueEntry>> = VecDeque::new();
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let mut next_id = 0u32;
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loop {
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let mut sim_queue = queue_debug.ty().new_sim(FetchPipeQueueEntry.default_sim());
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for entry in &queue {
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ArrayVec::try_push_sim(&mut sim_queue, entry)
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.ok()
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.expect("queue is known to be small enough");
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}
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sim.write(queue_debug, sim_queue).await;
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if let Some(front) = queue.front().filter(|v| v.cycles_left.as_int() == 0) {
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#[hdl(sim)]
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let FetchPipeQueueEntry {
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start_pc,
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cycles_left: _,
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fetch_block_id,
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} = front;
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let start_pc = start_pc.as_int();
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let end_pc =
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(start_pc + 1).next_multiple_of(config.get().fetch_width_in_bytes() as u64);
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let insns = to_post_decode.ty().inner.data.HdlSome.insns;
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let zeroed_insn = UInt[insns.element().canonical().bit_width()]
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.zero()
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.cast_bits_to(insns.element());
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let mut insns = insns.new_sim(zeroed_insn);
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let mut expected_pc = start_pc;
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// TODO: handle instructions that go past the end of a fetch block
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for (pc, insn) in mock_insns.fetch_block(start_pc..end_pc) {
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let next_pc = pc + insn.byte_len();
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if pc != expected_pc {
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break;
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}
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expected_pc = next_pc;
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let kind = match insn {
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MockInsn::Nop4 => WipDecodedInsnKind.NonBranch(),
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MockInsn::Jump { target } => WipDecodedInsnKind.Branch(target),
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MockInsn::CondBranch { target } => WipDecodedInsnKind.BranchCond(target),
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MockInsn::Call { target } => WipDecodedInsnKind.Call(target),
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MockInsn::Ret => WipDecodedInsnKind.Ret(),
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};
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let insn = #[hdl(sim)]
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WipDecodedInsn {
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fetch_block_id,
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id: next_id.cast_to_static::<UInt<_>>(),
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pc,
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size_in_bytes: insn.byte_len().cast_to_static::<UInt<_>>(),
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kind,
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};
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match ArrayVec::try_push_sim(&mut insns, insn) {
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Ok(()) => next_id = next_id.wrapping_add(1),
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Err(_) => break,
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}
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}
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if **ArrayVec::len_sim(&insns) == 0 {
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let Ok(()) = ArrayVec::try_push_sim(
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&mut insns,
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#[hdl(sim)]
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WipDecodedInsn {
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fetch_block_id,
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id: next_id.cast_to_static::<UInt<_>>(),
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pc: start_pc,
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size_in_bytes: 0u8.cast_to_static::<UInt<_>>(),
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kind: WipDecodedInsnKind.Interrupt(DEMO_ILLEGAL_INSN_TRAP),
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},
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) else {
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unreachable!();
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};
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next_id = next_id.wrapping_add(1);
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}
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sim.write(
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to_post_decode.inner.data,
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HdlSome(
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#[hdl(sim)]
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DecodeToPostDecodeInterfaceInner::<_> { insns, config },
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),
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)
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.await;
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} else {
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sim.write(
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to_post_decode.inner.data,
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to_post_decode.ty().inner.data.HdlNone(),
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)
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.await;
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}
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sim.write(from_fetch.fetch.ready, queue.len() < FETCH_PIPE_QUEUE_SIZE)
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.await;
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sim.write(from_fetch.cancel.ready, true).await;
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sim.wait_for_clock_edge(cd.clk).await;
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if sim.read_past_bool(to_post_decode.inner.ready, cd.clk).await {
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#[hdl(sim)]
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if let HdlSome(_) = sim.read_past(to_post_decode.inner.data, cd.clk).await {
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queue.pop_front();
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}
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}
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for entry in &mut queue {
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if entry.cycles_left.as_int() > 0 {
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entry.cycles_left = (entry.cycles_left.as_int() - 1u8).to_sim_value();
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}
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}
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// handle cancels before pushing new fetch op
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#[hdl(sim)]
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if let HdlSome(in_progress_fetches_to_cancel) =
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sim.read_past(from_fetch.cancel.data, cd.clk).await
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{
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// cancel in-progress fetches from newest to oldest
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for _ in 0..*in_progress_fetches_to_cancel {
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let _ = queue.pop_back();
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}
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}
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if !sim.read_past_bool(from_fetch.fetch.ready, cd.clk).await {
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continue;
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}
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// handle pushing new fetch op after handling cancels
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#[hdl(sim)]
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if let HdlSome(inner) = sim.read_past(from_fetch.fetch.data, cd.clk).await {
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#[hdl(sim)]
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let NextPcToFetchInterfaceInner {
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start_pc,
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fetch_block_id,
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} = &inner;
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queue.push_back(
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#[hdl(sim)]
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FetchPipeQueueEntry {
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start_pc,
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cycles_left: FetchPipeQueueEntry::get_next_delay(delay_sequence_index),
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fetch_block_id,
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},
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);
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}
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}
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}
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}
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const EXECUTE_RETIRE_PIPE_QUEUE_SIZE: usize = 15;
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#[hdl]
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struct ExecuteRetirePipeQueueEntry {
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insn: WipDecodedInsn,
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cycles_left: UInt<8>,
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}
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impl ExecuteRetirePipeQueueEntry {
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#[hdl]
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fn default_sim(self) -> SimValue<Self> {
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#[hdl(sim)]
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Self {
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insn: #[hdl(sim)]
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WipDecodedInsn {
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fetch_block_id: 0u8,
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id: 0_hdl_u12,
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pc: 0xEEEE_EEEE_EEEE_EEEEu64,
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size_in_bytes: 0_hdl_u4,
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kind: WipDecodedInsnKind.NonBranch(),
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},
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cycles_left: 0u8,
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}
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}
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fn get_next_delay(delay_sequence_index: &Cell<u64>) -> u8 {
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let index = delay_sequence_index.get();
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delay_sequence_index.set(delay_sequence_index.get().wrapping_add(1));
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// make a pseudo-random number deterministically based on index
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let random = index
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.wrapping_add(1)
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.wrapping_mul(0x39FF446D8BFB75BB) // random prime
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.rotate_left(32)
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.wrapping_mul(0x73161B54984B1C21) // random prime
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.rotate_right(60);
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(random % 16) as u8
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}
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}
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/// an arbitrary value
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const END_PC: u64 = u64::from_be_bytes(*b"EndInsns");
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#[derive(Clone)]
|
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struct MockExecuteState {
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queue: VecDeque<SimValue<ExecuteRetirePipeQueueEntry>>,
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used_ids: BTreeSet<SimValue<UInt<12>>>,
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retire_seq: RetireSeq,
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canceling: bool,
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config: PhantomConst<CpuConfig>,
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}
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impl MockExecuteState {
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fn new(config: PhantomConst<CpuConfig>) -> Self {
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Self {
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queue: VecDeque::new(),
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used_ids: BTreeSet::new(),
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retire_seq: RetireSeq::new(),
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canceling: false,
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config,
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}
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}
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fn on_clock_cycle(&mut self) {
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for entry in &mut self.queue {
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if entry.cycles_left.as_int() > 0 {
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entry.cycles_left = (entry.cycles_left.as_int() - 1u8).to_sim_value();
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}
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}
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}
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#[hdl]
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fn do_retire(
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&mut self,
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entry: SimValue<ExecuteRetirePipeQueueEntry>,
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passive: bool,
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) -> Result<SimValue<RetireToNextPcInterfacePerInsn<PhantomConst<CpuConfig>>>, String> {
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#[hdl(sim)]
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let ExecuteRetirePipeQueueEntry {
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insn,
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cycles_left: _,
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} = entry;
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self.used_ids.remove(&insn.id);
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let RetireSeqEntry {
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pc,
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cond_br_taken,
|
|
kind,
|
|
} = self
|
|
.retire_seq
|
|
.next()
|
|
.ok_or_else(|| "expected no more instructions to retire")?;
|
|
let next_pc = self
|
|
.retire_seq
|
|
.clone()
|
|
.next()
|
|
.map(|v| v.pc)
|
|
.unwrap_or(END_PC);
|
|
let (expected_kind, call_stack_op) = match kind {
|
|
MockInsn::Nop4 => (
|
|
#[hdl(sim)]
|
|
WipDecodedInsnKind::NonBranch(),
|
|
#[hdl(sim)]
|
|
CallStackOp::None(),
|
|
),
|
|
MockInsn::Jump { target } => (
|
|
#[hdl(sim)]
|
|
WipDecodedInsnKind::Branch(target),
|
|
#[hdl(sim)]
|
|
CallStackOp::None(),
|
|
),
|
|
MockInsn::CondBranch { target } => (
|
|
#[hdl(sim)]
|
|
WipDecodedInsnKind::BranchCond(target),
|
|
#[hdl(sim)]
|
|
CallStackOp::None(),
|
|
),
|
|
MockInsn::Call { target } => (
|
|
#[hdl(sim)]
|
|
WipDecodedInsnKind::Call(target),
|
|
#[hdl(sim)]
|
|
CallStackOp::Push(pc.wrapping_add(kind.byte_len())),
|
|
),
|
|
MockInsn::Ret => (
|
|
#[hdl(sim)]
|
|
WipDecodedInsnKind::Ret(),
|
|
#[hdl(sim)]
|
|
CallStackOp::Pop(),
|
|
),
|
|
};
|
|
let expected_insn = #[hdl(sim)]
|
|
WipDecodedInsn {
|
|
fetch_block_id: &insn.fetch_block_id,
|
|
id: &insn.id,
|
|
pc,
|
|
size_in_bytes: kind.byte_len().cast_to_static::<UInt<4>>(),
|
|
kind: expected_kind,
|
|
};
|
|
if *expected_insn.cmp_ne(&insn) {
|
|
return Err(format!(
|
|
"insn doesn't match expected:\ninsn: {insn:?}\nexpected insn: {expected_insn:?}"
|
|
));
|
|
}
|
|
if let Some(next_insn) = self.queue.front() {
|
|
if next_pc != next_insn.insn.pc.as_int() {
|
|
self.canceling = true;
|
|
if !passive {
|
|
println!(
|
|
"MockExecuteState: starting canceling {} instruction(s): next_pc={next_pc:#x}, mis-predicted next_pc={next_insn_pc}",
|
|
self.queue.len(),
|
|
next_insn_pc = next_insn.insn.pc
|
|
);
|
|
}
|
|
}
|
|
}
|
|
Ok(
|
|
#[hdl(sim)]
|
|
RetireToNextPcInterfacePerInsn::<_> {
|
|
id: &insn.id,
|
|
next_pc,
|
|
call_stack_op,
|
|
cond_br_taken: if let Some(cond_br_taken) = cond_br_taken {
|
|
#[hdl(sim)]
|
|
HdlSome(cond_br_taken)
|
|
} else {
|
|
#[hdl(sim)]
|
|
HdlNone()
|
|
},
|
|
config: self.config,
|
|
},
|
|
)
|
|
}
|
|
#[hdl]
|
|
fn try_retire(
|
|
&mut self,
|
|
passive: bool,
|
|
) -> Option<(
|
|
SimValue<RetireToNextPcInterfacePerInsn<PhantomConst<CpuConfig>>>,
|
|
Result<(), String>,
|
|
)> {
|
|
if self.canceling {
|
|
return None;
|
|
}
|
|
if self.queue.front()?.cycles_left.as_int() != 0 {
|
|
return None;
|
|
}
|
|
let entry = self.queue.pop_front()?;
|
|
let id = entry.insn.id.clone();
|
|
Some(match self.do_retire(entry, passive) {
|
|
Ok(v) => (v, Ok(())),
|
|
Err(e) => (
|
|
#[hdl(sim)]
|
|
RetireToNextPcInterfacePerInsn::<_> {
|
|
id,
|
|
next_pc: u64::from_be_bytes(*b"ErrError"),
|
|
call_stack_op: #[hdl(sim)]
|
|
CallStackOp::None(),
|
|
cond_br_taken: #[hdl(sim)]
|
|
HdlNone(),
|
|
config: self.config,
|
|
},
|
|
Err(e),
|
|
),
|
|
})
|
|
}
|
|
fn space_available(&self) -> usize {
|
|
EXECUTE_RETIRE_PIPE_QUEUE_SIZE.saturating_sub(self.queue.len())
|
|
}
|
|
#[hdl]
|
|
fn start(&mut self, insn: &SimValue<WipDecodedInsn>, delay_sequence_index: &Cell<u64>) {
|
|
if !self.used_ids.insert(insn.id.clone()) {
|
|
panic!("next_pc gave a duplicate insn id: {insn:?}");
|
|
}
|
|
self.queue.push_back(
|
|
#[hdl(sim)]
|
|
ExecuteRetirePipeQueueEntry {
|
|
insn,
|
|
cycles_left: ExecuteRetirePipeQueueEntry::get_next_delay(delay_sequence_index),
|
|
},
|
|
);
|
|
}
|
|
#[hdl]
|
|
fn finish_cancel(&mut self) {
|
|
println!(
|
|
"MockExecuteState: finishing canceling {} instruction(s)",
|
|
self.queue.len(),
|
|
);
|
|
self.queue.clear();
|
|
self.used_ids.clear();
|
|
self.canceling = false;
|
|
}
|
|
}
|
|
|
|
#[hdl_module(extern)]
|
|
fn mock_execute_retire_pipe(config: PhantomConst<CpuConfig>) {
|
|
#[hdl]
|
|
let cd: ClockDomain = m.input();
|
|
#[hdl]
|
|
let from_post_decode: PostDecodeOutputInterface<PhantomConst<CpuConfig>> =
|
|
m.input(PostDecodeOutputInterface[config]);
|
|
#[hdl]
|
|
let retire_output: RetireToNextPcInterface<PhantomConst<CpuConfig>> =
|
|
m.output(RetireToNextPcInterface[config]);
|
|
#[hdl]
|
|
let queue_debug: ArrayVec<
|
|
ExecuteRetirePipeQueueEntry,
|
|
ConstUsize<{ EXECUTE_RETIRE_PIPE_QUEUE_SIZE }>,
|
|
> = m.output();
|
|
m.register_clock_for_past(cd.clk);
|
|
m.extern_module_simulation_fn(
|
|
(cd, from_post_decode, retire_output, queue_debug),
|
|
|(cd, from_post_decode, retire_output, queue_debug), mut sim| async move {
|
|
// intentionally have a different sequence each time we're reset
|
|
let delay_sequence_index = Cell::new(0);
|
|
sim.resettable(
|
|
cd,
|
|
async |mut sim| {
|
|
sim.write(from_post_decode.ready, 0usize).await;
|
|
sim.write(
|
|
retire_output.inner.data,
|
|
retire_output.ty().inner.data.HdlNone(),
|
|
)
|
|
.await;
|
|
sim.write(
|
|
retire_output.next_insn_ids,
|
|
retire_output.next_insn_ids.ty().HdlNone(),
|
|
)
|
|
.await;
|
|
sim.write(
|
|
queue_debug,
|
|
queue_debug
|
|
.ty()
|
|
.new_sim(ExecuteRetirePipeQueueEntry.default_sim()),
|
|
)
|
|
.await;
|
|
},
|
|
|sim, ()| {
|
|
run_fn(
|
|
cd,
|
|
from_post_decode,
|
|
retire_output,
|
|
queue_debug,
|
|
&delay_sequence_index,
|
|
sim,
|
|
)
|
|
},
|
|
)
|
|
.await;
|
|
},
|
|
);
|
|
#[hdl]
|
|
async fn run_fn(
|
|
cd: Expr<ClockDomain>,
|
|
from_post_decode: Expr<PostDecodeOutputInterface<PhantomConst<CpuConfig>>>,
|
|
retire_output: Expr<RetireToNextPcInterface<PhantomConst<CpuConfig>>>,
|
|
queue_debug: Expr<
|
|
ArrayVec<ExecuteRetirePipeQueueEntry, ConstUsize<{ EXECUTE_RETIRE_PIPE_QUEUE_SIZE }>>,
|
|
>,
|
|
delay_sequence_index: &Cell<u64>,
|
|
mut sim: ExternModuleSimulationState,
|
|
) {
|
|
let config = from_post_decode.config.ty();
|
|
let mut state = MockExecuteState::new(config);
|
|
let empty_retire_insn = #[hdl(sim)]
|
|
RetireToNextPcInterfacePerInsn::<_> {
|
|
id: 0_hdl_u12,
|
|
next_pc: 0u64,
|
|
call_stack_op: #[hdl(sim)]
|
|
CallStackOp::None(),
|
|
cond_br_taken: #[hdl(sim)]
|
|
HdlNone(),
|
|
config,
|
|
};
|
|
let retire_vec_ty = retire_output.inner.data.ty().HdlSome.insns;
|
|
loop {
|
|
state.on_clock_cycle();
|
|
let mut sim_queue = queue_debug
|
|
.ty()
|
|
.new_sim(ExecuteRetirePipeQueueEntry.default_sim());
|
|
let mut next_insn_ids = retire_output.next_insn_ids.ty().HdlSome.new_sim(0_hdl_u12);
|
|
for entry in &state.queue {
|
|
ArrayVec::try_push_sim(&mut sim_queue, entry)
|
|
.ok()
|
|
.expect("queue is known to be small enough");
|
|
let _ = ArrayVec::try_push_sim(&mut next_insn_ids, &entry.insn.id);
|
|
}
|
|
sim.write(queue_debug, sim_queue).await;
|
|
sim.write(
|
|
retire_output.next_insn_ids,
|
|
if state.canceling {
|
|
#[hdl(sim)]
|
|
(retire_output.next_insn_ids.ty()).HdlNone()
|
|
} else {
|
|
#[hdl(sim)]
|
|
(retire_output.next_insn_ids.ty()).HdlSome(next_insn_ids)
|
|
},
|
|
)
|
|
.await;
|
|
let mut retiring = retire_vec_ty.new_sim(&empty_retire_insn);
|
|
let mut peek_state = state.clone();
|
|
while let Some((peek_retire, result)) = peek_state.try_retire(true) {
|
|
if result.is_err() && **ArrayVec::len_sim(&retiring) > 0 {
|
|
break;
|
|
}
|
|
let Ok(_) = ArrayVec::try_push_sim(&mut retiring, peek_retire) else {
|
|
break;
|
|
};
|
|
}
|
|
sim.write(
|
|
retire_output.inner.data,
|
|
if **ArrayVec::len_sim(&retiring) > 0 {
|
|
#[hdl(sim)]
|
|
(retire_output.inner.data.ty()).HdlSome(
|
|
#[hdl(sim)]
|
|
RetireToNextPcInterfaceInner::<_> {
|
|
insns: retiring,
|
|
config,
|
|
},
|
|
)
|
|
} else {
|
|
#[hdl(sim)]
|
|
(retire_output.inner.data.ty()).HdlNone()
|
|
},
|
|
)
|
|
.await;
|
|
sim.write(
|
|
from_post_decode.ready,
|
|
if state.canceling {
|
|
0
|
|
} else {
|
|
state.space_available().min(config.get().fetch_width.get())
|
|
},
|
|
)
|
|
.await;
|
|
sim.wait_for_clock_edge(cd.clk).await;
|
|
println!(
|
|
"Dump mock execute retire pipe queue: {:#?}",
|
|
Vec::from_iter(state.queue.iter().map(|v| {
|
|
DebugAsDisplay(format!(
|
|
"fid={:#x} id={} pc={:#x}",
|
|
v.insn.fetch_block_id.as_int(),
|
|
v.insn.id,
|
|
v.insn.pc.as_int(),
|
|
))
|
|
}))
|
|
);
|
|
if state.canceling {
|
|
state.finish_cancel();
|
|
}
|
|
if sim.read_past_bool(retire_output.inner.ready, cd.clk).await {
|
|
for _ in 0..**ArrayVec::len_sim(&retiring) {
|
|
match state.try_retire(false) {
|
|
Some((_, Ok(_))) => {}
|
|
Some((_, Err(e))) => panic!("retire error: {e}"),
|
|
None => unreachable!(),
|
|
}
|
|
}
|
|
}
|
|
let mut new_insns = sim.read_past(from_post_decode.insns, cd.clk).await;
|
|
ArrayVec::truncate_sim(
|
|
&mut new_insns,
|
|
*sim.read_past(from_post_decode.ready, cd.clk).await,
|
|
);
|
|
for insn in dbg!(ArrayVec::elements_sim_ref(&new_insns)) {
|
|
state.start(insn, delay_sequence_index);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
#[hdl_module]
|
|
fn dut(config: PhantomConst<CpuConfig>) {
|
|
#[hdl]
|
|
let cd: ClockDomain = m.input();
|
|
#[hdl]
|
|
let next_pc = instance(next_pc(config));
|
|
#[hdl]
|
|
let next_pc {
|
|
cd: next_pc_cd,
|
|
to_fetch: next_pc_to_fetch,
|
|
from_decode: next_pc_from_decode,
|
|
post_decode_output: next_pc_post_decode_output,
|
|
from_retire: next_pc_from_retire,
|
|
state_for_debug: _,
|
|
} = next_pc;
|
|
connect(next_pc_cd, cd);
|
|
#[hdl]
|
|
let mock_fetch_pipe = instance(mock_fetch_pipe(config));
|
|
#[hdl]
|
|
let mock_fetch_pipe {
|
|
cd: mock_fetch_pipe_cd,
|
|
from_fetch: mock_fetch_pipe_from_fetch,
|
|
to_post_decode: mock_fetch_pipe_to_post_decode,
|
|
queue_debug: _,
|
|
} = mock_fetch_pipe;
|
|
connect(mock_fetch_pipe_cd, cd);
|
|
connect(mock_fetch_pipe_from_fetch, next_pc_to_fetch);
|
|
connect(next_pc_from_decode, mock_fetch_pipe_to_post_decode);
|
|
#[hdl]
|
|
let mock_execute_retire_pipe = instance(mock_execute_retire_pipe(config));
|
|
#[hdl]
|
|
let mock_execute_retire_pipe {
|
|
cd: mock_execute_retire_pipe_cd,
|
|
from_post_decode: mock_execute_retire_pipe_from_post_decode,
|
|
retire_output: mock_execute_retire_pipe_retire_output,
|
|
queue_debug: _,
|
|
} = mock_execute_retire_pipe;
|
|
connect(mock_execute_retire_pipe_cd, cd);
|
|
connect(next_pc_from_retire, mock_execute_retire_pipe_retire_output);
|
|
connect(
|
|
mock_execute_retire_pipe_from_post_decode,
|
|
next_pc_post_decode_output,
|
|
);
|
|
}
|
|
|
|
#[hdl]
|
|
#[test]
|
|
fn test_next_pc() {
|
|
let _n = SourceLocation::normalize_files_for_tests();
|
|
let mut config = CpuConfig::new(
|
|
vec![
|
|
UnitConfig::new(UnitKind::AluBranch),
|
|
UnitConfig::new(UnitKind::AluBranch),
|
|
],
|
|
NonZeroUsize::new(20).unwrap(),
|
|
);
|
|
config.fetch_width = NonZeroUsize::new(2).unwrap();
|
|
let m = dut(PhantomConst::new_sized(config));
|
|
let mut sim = Simulation::new(m);
|
|
let writer = RcWriter::default();
|
|
sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
|
|
struct DumpVcdOnDrop {
|
|
writer: Option<RcWriter>,
|
|
}
|
|
impl Drop for DumpVcdOnDrop {
|
|
fn drop(&mut self) {
|
|
if let Some(mut writer) = self.writer.take() {
|
|
let vcd = String::from_utf8(writer.take()).unwrap();
|
|
println!("####### VCD:\n{vcd}\n#######");
|
|
}
|
|
}
|
|
}
|
|
let mut writer = DumpVcdOnDrop {
|
|
writer: Some(writer),
|
|
};
|
|
sim.write_clock(sim.io().cd.clk, false);
|
|
sim.write_reset(sim.io().cd.rst, true);
|
|
for _cycle in 0..500 {
|
|
sim.advance_time(SimDuration::from_nanos(500));
|
|
println!("clock tick");
|
|
sim.write_clock(sim.io().cd.clk, true);
|
|
sim.advance_time(SimDuration::from_nanos(500));
|
|
sim.write_clock(sim.io().cd.clk, false);
|
|
sim.write_reset(sim.io().cd.rst, false);
|
|
}
|
|
// FIXME: vcd is just whatever next_pc does now, which isn't known to be correct
|
|
let vcd = String::from_utf8(writer.writer.take().unwrap().take()).unwrap();
|
|
println!("####### VCD:\n{vcd}\n#######");
|
|
if vcd != include_str!("expected/next_pc.vcd") {
|
|
panic!();
|
|
}
|
|
}
|