libre-chip/cpu
3
0
Fork 2
Code Issues 1 Pull requests Projects Releases Packages Wiki Activity Actions
No description https://libre-chip.org/grants/nlnet-first.html
92 commits 2 branches 0 tags 11 MiB
Find a file
Jacob Lifshay 5e9d0957f6
reorder the decoder test cases to match the PowerISA v3.1C PDF
2026-01-23 09:46:29 -08:00
.forgejo/workflows update CI to use new fayalite-deps container 2025-10-24 02:54:03 -07:00
crates/cpu reorder the decoder test cases to match the PowerISA v3.1C PDF 2026-01-23 09:46:29 -08:00
scripts mark .vcd files as generated 2026-01-20 16:20:40 -08:00
.gitattributes mark .vcd files as generated 2026-01-20 16:20:40 -08:00
.gitignore implement decoding mcrxrx 2026-01-22 07:34:53 -08:00
Cargo.lock WIP adding simple power isa decoder 2026-01-12 07:10:58 -08:00
Cargo.toml WIP adding simple power isa decoder 2026-01-12 07:10:58 -08:00
LICENSE.md start adding cpu data types 2024-10-08 20:22:15 -07:00
Notices.txt start adding cpu data types 2024-10-08 20:22:15 -07:00
README.md add readme 2025-10-24 16:36:31 -07:00

README.md

Libre-Chip's CPU

https://libre-chip.org/first_arch/index.html

Funding

NLnet Grants

This project was funded through the NGI0 Commons Fund, a fund established by NLnet with financial support from the European Commission's Next Generation Internet programme, under the aegis of DG Communications Networks, Content and Technology under grant agreement № 101135429. Additional funding is made available by the Swiss State Secretariat for Education, Research and Innovation (SERI).