1866 lines
66 KiB
Rust
1866 lines
66 KiB
Rust
// SPDX-License-Identifier: LGPL-3.0-or-later
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// See Notices.txt for copyright information
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use crate::{
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config::{
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CpuConfig, CpuConfig2PowOutRegNumWidth, CpuConfigFetchWidth, CpuConfigPRegNumWidth,
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CpuConfigRobSize, CpuConfigUnitCount, PhantomConstCpuConfig, TwiceCpuConfigFetchWidth,
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},
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instruction::{
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COMMON_MOP_SRC_LEN, L2RegNum, L2RegisterFileMOp, MOp, MOpDebug, MOpDestReg, MOpRegNum,
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MOpTrait, PRegNum, ReadL2RegMOp, UnitNum, UnitOutRegNum,
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},
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next_pc::{CallStackOp, SimValueDefault},
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register::PRegValue,
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rename_execute_retire::to_unit_interfaces::ExecuteToUnitInterfaces,
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unit::{UnitKind, UnitMOp},
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util::array_vec::ArrayVec,
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};
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use fayalite::{
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int::UIntInRangeInclusiveType,
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prelude::*,
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ty::{OpaqueSimValue, StaticType},
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util::ready_valid::ReadyValid,
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};
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use std::{collections::VecDeque, fmt, mem, num::NonZero};
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pub mod to_unit_interfaces;
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pub const MOP_ID_WIDTH: usize = 16;
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#[hdl]
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pub type MOpId = UInt<{ MOP_ID_WIDTH }>;
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#[hdl]
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/// A µOp along with the state needed for this instance of the µOp.
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pub struct MOpInstance<MOp> {
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pub fetch_block_id: UInt<8>,
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pub id: MOpId,
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pub pc: UInt<64>,
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/// initialized to 0 by decoder, overwritten by `next_pc()`
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pub predicted_next_pc: UInt<64>,
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pub size_in_bytes: UInt<4>,
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/// `true` if this µOp is the first µOp in the ISA-level instruction.
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/// In general, a single µOp can't be canceled by itself,
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/// it needs to be canceled along with all other µOps that
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/// come from the same ISA-level instruction.
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pub is_first_mop_in_insn: Bool,
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pub mop: MOp,
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}
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#[hdl(no_static)]
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/// TODO: merge with [`crate::next_pc::PostDecodeOutputInterface`]
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pub struct PostDecodeOutputInterface<C: PhantomConstGet<CpuConfig>> {
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pub insns: ArrayVec<MOpInstance<MOp>, CpuConfigFetchWidth<C>>,
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#[hdl(flip)]
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pub ready: UIntInRangeInclusiveType<ConstUsize<0>, CpuConfigFetchWidth<C>>,
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/// tells the rename/execute/retire circuit to cancel all non-retired instructions
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pub cancel: ReadyValid<()>,
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pub config: C,
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}
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#[hdl(no_static)]
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pub struct NextPcPredictorOp<C: PhantomConstGet<CpuConfig>> {
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pub call_stack_op: CallStackOp,
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/// should be `HdlSome(taken)` for any conditional control-flow instruction
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/// with an immediate target that can be predicted as taken/not-taken (branch/call/return).
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pub cond_br_taken: HdlOption<Bool>,
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pub config: C,
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}
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#[hdl(no_static)]
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/// TODO: merge with [`crate::next_pc::RetireToNextPcInterfaceInner`]
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pub enum RetireToNextPcInterfaceInner<C: PhantomConstGet<CpuConfig>> {
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CancelAndStartAt(UInt<64>),
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RetiredInstructions(ArrayVec<NextPcPredictorOp<C>, CpuConfigFetchWidth<C>>),
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}
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#[hdl(no_static)]
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/// handles updating speculative branch predictor state (e.g. branch histories)
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/// when instructions retire, as well as updating state when a
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/// branch instruction is mis-speculated.
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pub struct RetireToNextPcInterface<C: PhantomConstGet<CpuConfig>> {
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pub inner: ReadyValid<RetireToNextPcInterfaceInner<C>>,
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/// only for debugging
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pub next_insns: HdlOption<ArrayVec<MOpInstance<MOp>, CpuConfigRobSize<C>>>,
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}
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#[hdl]
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pub type RenamedMOp<C: PhantomConstGet<CpuConfig>> =
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crate::instruction::RenamedMOp<PRegNum<C>, CpuConfigPRegNumWidth<C>>;
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#[hdl]
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pub type RenamedSrcRegUInt<C: PhantomConstGet<CpuConfig>> = UIntType<CpuConfigPRegNumWidth<C>>;
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#[hdl(no_static)]
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pub struct UnitStart<C: PhantomConstGet<CpuConfig>> {
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pub mop: MOpInstance<RenamedMOp<C>>,
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pub src_values: Array<PRegValue, { COMMON_MOP_SRC_LEN }>,
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pub config: C,
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}
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#[hdl(no_static)]
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pub struct UnitFinishedSuccessfully<C: PhantomConstGet<CpuConfig>> {
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pub dest: UnitOutRegNum<C>,
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pub dest_value: PRegValue,
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pub predictor_op: NextPcPredictorOp<C>,
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}
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#[hdl(no_static)]
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pub struct UnitCausedCancel<C: PhantomConstGet<CpuConfig>> {
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pub id: MOpId,
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pub start_at_pc: UInt<64>,
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pub config: C,
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}
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#[hdl(no_static)]
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pub struct UnitFinished<C: PhantomConstGet<CpuConfig>> {
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pub id: MOpId,
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pub finished_successfully: HdlOption<UnitFinishedSuccessfully<C>>,
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pub caused_cancel: HdlOption<UnitCausedCancel<C>>,
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pub config: C,
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}
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#[hdl(no_static)]
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pub struct UnitMOpIsNoLongerSpeculative<C: PhantomConstGet<CpuConfig>> {
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pub id: MOpId,
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pub config: C,
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}
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#[hdl(no_static)]
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pub struct UnitMOpCantCauseCancel<C: PhantomConstGet<CpuConfig>> {
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pub id: MOpId,
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pub config: C,
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}
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#[hdl(no_static)]
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pub struct ExecuteToUnitInterface<C: PhantomConstGet<CpuConfig>> {
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pub start: ReadyValid<UnitStart<C>>,
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pub cancel_all: ReadyValid<()>,
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pub is_no_longer_speculative: ReadyValid<UnitMOpIsNoLongerSpeculative<C>>,
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#[hdl(flip)]
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pub cant_cause_cancel: ReadyValid<UnitMOpCantCauseCancel<C>>,
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#[hdl(flip)]
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pub finished: ReadyValid<UnitFinished<C>>,
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pub config: C,
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}
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fn zeroed<T: Type>(ty: T) -> SimValue<T> {
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SimValue::from_opaque(
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ty,
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OpaqueSimValue::from_bits(UInt::new(ty.canonical().bit_width()).zero()),
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)
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}
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impl<C: PhantomConstCpuConfig> SimValueDefault for RenameExecuteRetireDebugState<C> {
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#[hdl]
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fn sim_value_default(self) -> SimValue<Self> {
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let Self {
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rename_delayed,
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rename_table,
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retire_rename_table,
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rob,
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next_pc_canceling,
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unit_canceling,
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l1_reg_file,
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per_insn_timeline,
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} = self;
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let empty_string = SimOnlyValue::new(String::new());
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#[hdl(sim)]
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Self {
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rename_delayed: zeroed(rename_delayed),
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rename_table: zeroed(rename_table),
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retire_rename_table: zeroed(retire_rename_table),
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rob: zeroed(rob),
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next_pc_canceling: zeroed(next_pc_canceling),
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unit_canceling: zeroed(unit_canceling),
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l1_reg_file: zeroed(l1_reg_file),
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per_insn_timeline: SimValue::from_array_elements(
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per_insn_timeline,
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(0..per_insn_timeline.len()).map(|_| empty_string.clone()),
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),
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}
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}
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}
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#[hdl(no_static)]
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enum RenameTableEntry<C: PhantomConstGet<CpuConfig>> {
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L1(PRegNum<C>),
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L2(L2RegNum),
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}
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impl<C: PhantomConstCpuConfig> RenameTableEntry<C> {
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#[hdl]
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fn const_zero(self) -> SimValue<Self> {
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#[hdl(sim)]
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self.L1(self.L1.const_zero())
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}
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#[hdl]
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fn debug_sim(this: &SimValue<Self>) -> impl fmt::Debug {
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fmt::from_fn(move |f| {
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#[hdl(sim)]
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match this {
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Self::L1(v) => write!(f, "L1({:?})", PRegNum::debug_sim(v)),
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Self::L2(v) => write!(f, "L2({:?})", L2RegNum::debug_sim(v)),
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}
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})
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}
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}
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/// make arrays dynamically-sized to avoid putting large types on the stack
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#[hdl(get(|c| 1 << MOpRegNum::WIDTH))]
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type MOpRegCount<C: PhantomConstGet<CpuConfig>> = DynSize;
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#[hdl(no_static)]
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struct RenameTableDebugState<C: PhantomConstGet<CpuConfig>> {
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entries: ArrayType<RenameTableEntry<C>, MOpRegCount<C>>,
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config: C,
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}
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#[derive(Debug)]
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struct RenameTable<C: PhantomConstCpuConfig> {
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entries: Box<[SimValue<RenameTableEntry<C>>; 1 << MOpRegNum::WIDTH]>,
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config: C,
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}
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impl<C: PhantomConstCpuConfig> Clone for RenameTable<C> {
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fn clone(&self) -> Self {
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Self {
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entries: self.entries.clone(),
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config: self.config.clone(),
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}
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}
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fn clone_from(&mut self, source: &Self) {
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let Self { entries, config } = self;
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entries.clone_from(&source.entries);
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*config = source.config;
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}
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}
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#[derive(Debug, Clone)]
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enum RenameTableUpdate<C: PhantomConstCpuConfig> {
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Write {
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unrenamed_reg_num: u32,
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new: SimValue<RenameTableEntry<C>>,
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},
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UpdateForReadL2Reg {
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dest: SimValue<PRegNum<C>>,
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src: SimValue<L2RegNum>,
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},
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UpdateForWriteL2Reg {
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dest: SimValue<L2RegNum>,
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src: SimValue<PRegNum<C>>,
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},
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}
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impl<C: PhantomConstCpuConfig> RenameTable<C> {
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fn new(config: C) -> Self {
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let entries: Box<[SimValue<RenameTableEntry<C>>; 1 << MOpRegNum::WIDTH]> =
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vec![RenameTableEntry[config].const_zero(); 1 << MOpRegNum::WIDTH]
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.try_into()
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.expect("size is known to match");
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Self { entries, config }
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}
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#[hdl]
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fn to_debug_state(&self) -> SimValue<RenameTableDebugState<C>> {
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let Self { entries, config } = self;
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let ty = RenameTableDebugState[*config];
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#[hdl(sim)]
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RenameTableDebugState::<_> {
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entries: entries.to_sim_value_with_type(ty.entries),
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config,
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}
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}
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#[hdl]
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fn update(&mut self, update: &RenameTableUpdate<C>, rename_table_name: &str) {
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match update {
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RenameTableUpdate::Write {
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unrenamed_reg_num,
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new,
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} => {
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if *unrenamed_reg_num == MOpRegNum::CONST_ZERO_REG_NUM {
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// writing to const zero reg does nothing
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return;
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}
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println!(
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"{rename_table_name}: Write: {unrenamed_reg_num:#x} <- {:?}",
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RenameTableEntry::debug_sim(new),
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);
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self.entries[*unrenamed_reg_num as usize] = new.clone();
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}
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RenameTableUpdate::UpdateForReadL2Reg { dest, src } => {
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let new = #[hdl(sim)]
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(RenameTableEntry[self.config]).L1(dest);
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for (unrenamed_reg_num, entry) in self.entries.iter_mut().enumerate() {
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#[hdl(sim)]
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match &entry {
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RenameTableEntry::<_>::L1(_) => {}
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RenameTableEntry::<_>::L2(l2) => {
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if L2RegNum::value_sim(l2) == L2RegNum::value_sim(src) {
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println!(
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"{rename_table_name}: UpdateForReadL2Reg: {unrenamed_reg_num:#x} updating from {:?} to {:?}",
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RenameTableEntry::debug_sim(&entry),
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RenameTableEntry::debug_sim(&new),
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);
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*entry = new.clone();
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}
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}
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}
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}
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}
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RenameTableUpdate::UpdateForWriteL2Reg { dest, src } => {
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let new = #[hdl(sim)]
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(RenameTableEntry[self.config]).L2(dest);
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for (unrenamed_reg_num, entry) in self.entries.iter_mut().enumerate() {
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#[hdl(sim)]
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match &entry {
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RenameTableEntry::<_>::L1(l1) => {
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if l1 == src {
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println!(
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"{rename_table_name}: UpdateForWriteL2Reg: {unrenamed_reg_num:#x} updating from {:?} to {:?}",
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RenameTableEntry::debug_sim(&entry),
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RenameTableEntry::debug_sim(&new),
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);
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*entry = new.clone();
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}
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}
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RenameTableEntry::<_>::L2(_) => {}
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}
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}
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}
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}
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}
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}
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#[hdl(no_static)]
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enum MOpExecutionProgressDebugState<C: PhantomConstGet<CpuConfig>> {
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NotStarted,
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Started,
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Finished(NextPcPredictorOp<C>),
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Canceled,
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}
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#[hdl(no_static)]
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struct RobEntryDebugState<C: PhantomConstGet<CpuConfig>> {
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mop: MOpInstance<RenamedMOp<C>>,
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is_speculative: Bool,
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sent_is_no_longer_speculative: Bool,
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can_cause_cancel: Bool,
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progress: MOpExecutionProgressDebugState<C>,
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caused_cancel: HdlOption<UnitCausedCancel<C>>,
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}
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impl<C: PhantomConstCpuConfig> SimValueDefault for RobEntryDebugState<C> {
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fn sim_value_default(self) -> SimValue<Self> {
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zeroed(self)
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}
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}
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#[derive(Clone, Debug)]
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enum MOpExecutionProgress<C: Type + PhantomConstGet<CpuConfig>> {
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NotStarted,
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Started,
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Finished(SimValue<NextPcPredictorOp<C>>),
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Canceled,
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}
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impl<C: Type + PhantomConstGet<CpuConfig>> MOpExecutionProgress<C> {
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#[hdl]
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fn debug_state(&self, config: C) -> SimValue<MOpExecutionProgressDebugState<C>> {
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let ret_ty = MOpExecutionProgressDebugState[config];
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match self {
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Self::NotStarted =>
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{
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#[hdl(sim)]
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ret_ty.NotStarted()
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}
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Self::Started =>
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{
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#[hdl(sim)]
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ret_ty.Started()
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}
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Self::Finished(v) =>
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{
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#[hdl(sim)]
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ret_ty.Finished(v)
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}
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Self::Canceled =>
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{
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#[hdl(sim)]
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ret_ty.Canceled()
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}
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}
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}
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}
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#[derive(Debug)]
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struct RobEntry<C: PhantomConstCpuConfig> {
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mop: SimValue<MOpInstance<RenamedMOp<C>>>,
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is_speculative: bool,
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sent_is_no_longer_speculative: bool,
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can_cause_cancel: bool,
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progress: MOpExecutionProgress<C>,
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caused_cancel: Option<SimValue<UnitCausedCancel<C>>>,
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}
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impl<C: PhantomConstCpuConfig> RobEntry<C> {
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fn new(mop: SimValue<MOpInstance<RenamedMOp<C>>>) -> Self {
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Self {
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mop,
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is_speculative: true,
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sent_is_no_longer_speculative: false,
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can_cause_cancel: true,
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progress: MOpExecutionProgress::NotStarted,
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caused_cancel: None,
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}
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}
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fn dest_reg(&self) -> &SimValue<PRegNum<C>> {
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MOpTrait::dest_reg_sim_ref(&self.mop.mop)
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}
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fn unit_num(&self) -> &SimValue<UnitNum<C>> {
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&self.dest_reg().unit_num
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}
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fn unit_index(&self) -> usize {
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UnitNum::index_sim(&self.unit_num()).expect("known to have unit_index")
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}
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fn unit_out_reg(&self) -> &SimValue<UnitOutRegNum<C>> {
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&self.dest_reg().unit_out_reg
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}
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fn unit_out_reg_index(&self) -> usize {
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UnitOutRegNum::value_sim(&self.unit_out_reg())
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}
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}
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#[hdl]
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struct RobEntriesDebugState {
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unrenamed: MOpInstance<MOp>,
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/// number of renamed µOps that this unrenamed µOp corresponds to
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renamed_entries_len: UInt<8>,
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}
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|
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#[derive(Debug)]
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struct RobEntries<C: PhantomConstCpuConfig> {
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unrenamed: SimValue<MOpInstance<MOp>>,
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rename_table_updates: Vec<RenameTableUpdate<C>>,
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renamed_entries: VecDeque<RobEntry<C>>,
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}
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impl<C: PhantomConstCpuConfig> RobEntries<C> {
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#[hdl]
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fn debug_state(&self) -> SimValue<RobEntriesDebugState> {
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let Self {
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unrenamed,
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rename_table_updates: _,
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renamed_entries,
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} = self;
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#[hdl(sim)]
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RobEntriesDebugState {
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unrenamed,
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renamed_entries_len: u8::try_from(renamed_entries.len())
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.expect("renamed_entries.len() should fit in u8"),
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}
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}
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}
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#[hdl(no_static)]
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struct NeedSendCancelDebugState<C: PhantomConstGet<CpuConfig>> {
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|
send_to_next_pc: HdlOption<UInt<64>>,
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send_to_units: ArrayType<Bool, CpuConfigUnitCount<C>>,
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config: C,
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}
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|
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#[hdl]
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enum NextPcCancelingDebugState {
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NeedSendCancel(UInt<64>),
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NeedReceiveCancel,
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}
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|
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#[derive(Clone, PartialEq, Eq, Debug)]
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enum NextPcCancelingState {
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NeedSendCancel(u64),
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NeedReceiveCancel,
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}
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|
|
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impl NextPcCancelingState {
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#[hdl]
|
|
fn debug_state(this: &Option<Self>) -> SimValue<HdlOption<NextPcCancelingDebugState>> {
|
|
match this {
|
|
Some(Self::NeedSendCancel(pc)) =>
|
|
{
|
|
#[hdl(sim)]
|
|
HdlSome(
|
|
#[hdl(sim)]
|
|
NextPcCancelingDebugState.NeedSendCancel(pc),
|
|
)
|
|
}
|
|
Some(Self::NeedReceiveCancel) =>
|
|
{
|
|
#[hdl(sim)]
|
|
HdlSome(
|
|
#[hdl(sim)]
|
|
NextPcCancelingDebugState.NeedReceiveCancel(),
|
|
)
|
|
}
|
|
None =>
|
|
{
|
|
#[hdl(sim)]
|
|
HdlNone()
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
#[hdl(no_static)]
|
|
pub struct ReorderBufferDebugState<C: PhantomConstGet<CpuConfig>> {
|
|
next_renamed_mop_id: MOpId,
|
|
entries: ArrayVec<RobEntriesDebugState, CpuConfigRobSize<C>>,
|
|
incomplete_back_entry: HdlOption<RobEntriesDebugState>,
|
|
renamed: ArrayVec<RobEntryDebugState<C>, CpuConfigRobSize<C>>,
|
|
config: C,
|
|
}
|
|
|
|
#[derive(Debug)]
|
|
struct ReorderBuffer<C: PhantomConstCpuConfig> {
|
|
next_renamed_mop_id: SimValue<MOpId>,
|
|
entries: VecDeque<RobEntries<C>>,
|
|
incomplete_back_entry: Option<RobEntries<C>>,
|
|
config: C,
|
|
}
|
|
|
|
impl<C: PhantomConstCpuConfig> ReorderBuffer<C> {
|
|
fn new(config: C) -> Self {
|
|
Self {
|
|
next_renamed_mop_id: MOpId.zero().into_sim_value(),
|
|
entries: VecDeque::new(),
|
|
incomplete_back_entry: None,
|
|
config,
|
|
}
|
|
}
|
|
#[hdl]
|
|
fn debug_state(&self) -> SimValue<ReorderBufferDebugState<C>> {
|
|
let Self {
|
|
next_renamed_mop_id,
|
|
entries,
|
|
incomplete_back_entry,
|
|
config,
|
|
} = self;
|
|
let ty = ReorderBufferDebugState[*config];
|
|
#[hdl(sim)]
|
|
ReorderBufferDebugState::<_> {
|
|
next_renamed_mop_id,
|
|
entries: ty
|
|
.entries
|
|
.from_iter_sim(
|
|
zeroed(StaticType::TYPE),
|
|
entries.iter().map(RobEntries::debug_state),
|
|
)
|
|
.expect("known to fit"),
|
|
incomplete_back_entry: if let Some(incomplete_back_entry) = incomplete_back_entry {
|
|
#[hdl(sim)]
|
|
HdlSome(incomplete_back_entry.debug_state())
|
|
} else {
|
|
#[hdl(sim)]
|
|
HdlNone()
|
|
},
|
|
renamed: ty
|
|
.renamed
|
|
.from_iter_sim(
|
|
zeroed(ty.renamed.element()),
|
|
self.renamed().map(|entry| {
|
|
let RobEntry {
|
|
mop,
|
|
is_speculative,
|
|
sent_is_no_longer_speculative,
|
|
can_cause_cancel,
|
|
progress,
|
|
caused_cancel,
|
|
} = entry;
|
|
let caused_cancel_ty = HdlOption[UnitCausedCancel[self.config]];
|
|
#[hdl(sim)]
|
|
RobEntryDebugState::<_> {
|
|
mop,
|
|
is_speculative,
|
|
sent_is_no_longer_speculative,
|
|
can_cause_cancel,
|
|
progress: progress.debug_state(self.config),
|
|
caused_cancel: if let Some(caused_cancel) = caused_cancel {
|
|
#[hdl(sim)]
|
|
caused_cancel_ty.HdlSome(caused_cancel)
|
|
} else {
|
|
#[hdl(sim)]
|
|
caused_cancel_ty.HdlNone()
|
|
},
|
|
}
|
|
}),
|
|
)
|
|
.ok()
|
|
.expect("known to fit"),
|
|
config,
|
|
}
|
|
}
|
|
fn unrenamed_len(&self) -> usize {
|
|
self.entries.len()
|
|
}
|
|
fn unrenamed(&self) -> impl DoubleEndedIterator<Item = &SimValue<MOpInstance<MOp>>> + Clone {
|
|
self.entries.iter().map(|v| &v.unrenamed)
|
|
}
|
|
fn unrenamed_mut(
|
|
&mut self,
|
|
) -> impl DoubleEndedIterator<Item = &mut SimValue<MOpInstance<MOp>>> {
|
|
self.entries.iter_mut().map(|v| &mut v.unrenamed)
|
|
}
|
|
fn renamed_len(&self) -> usize {
|
|
let Self {
|
|
next_renamed_mop_id: _,
|
|
entries,
|
|
incomplete_back_entry,
|
|
config: _,
|
|
} = self;
|
|
entries
|
|
.iter()
|
|
.chain(incomplete_back_entry)
|
|
.map(|entries| entries.renamed_entries.len())
|
|
.sum()
|
|
}
|
|
fn renamed(&self) -> impl DoubleEndedIterator<Item = &RobEntry<C>> + Clone {
|
|
let Self {
|
|
next_renamed_mop_id: _,
|
|
entries,
|
|
incomplete_back_entry,
|
|
config: _,
|
|
} = self;
|
|
entries
|
|
.iter()
|
|
.chain(incomplete_back_entry)
|
|
.flat_map(|entries| &entries.renamed_entries)
|
|
}
|
|
fn renamed_mut(&mut self) -> impl DoubleEndedIterator<Item = &mut RobEntry<C>> {
|
|
let Self {
|
|
next_renamed_mop_id: _,
|
|
entries,
|
|
incomplete_back_entry,
|
|
config: _,
|
|
} = self;
|
|
entries
|
|
.iter_mut()
|
|
.chain(incomplete_back_entry)
|
|
.flat_map(|entries| &mut entries.renamed_entries)
|
|
}
|
|
fn try_renamed_by_id(&self, id: &SimValue<MOpId>) -> Option<&RobEntry<C>> {
|
|
self.renamed().find(|v| v.mop.id == *id)
|
|
}
|
|
fn try_renamed_by_id_mut(&mut self, id: &SimValue<MOpId>) -> Option<&mut RobEntry<C>> {
|
|
self.renamed_mut().find(|v| v.mop.id == *id)
|
|
}
|
|
#[track_caller]
|
|
fn renamed_by_id(&self, id: &SimValue<MOpId>) -> &RobEntry<C> {
|
|
match self.try_renamed_by_id(id) {
|
|
Some(v) => v,
|
|
None => panic!("MOpId not found: {id:?}"),
|
|
}
|
|
}
|
|
fn renamed_by_id_mut(&mut self, id: &SimValue<MOpId>) -> &mut RobEntry<C> {
|
|
match self.try_renamed_by_id_mut(id) {
|
|
Some(v) => v,
|
|
None => panic!("MOpId not found: {id:?}"),
|
|
}
|
|
}
|
|
fn renamed_push_back_with_new_id(
|
|
&mut self,
|
|
unrenamed: &SimValue<MOpInstance<MOp>>,
|
|
mut renamed: RobEntry<C>,
|
|
) {
|
|
let replacement_id = self
|
|
.next_renamed_mop_id
|
|
.as_int()
|
|
.wrapping_add(1)
|
|
.into_sim_value();
|
|
renamed.mop.id = mem::replace(&mut self.next_renamed_mop_id, replacement_id);
|
|
self.incomplete_back_entry
|
|
.get_or_insert_with(|| RobEntries {
|
|
unrenamed: unrenamed.clone(),
|
|
rename_table_updates: Vec::new(),
|
|
renamed_entries: VecDeque::new(),
|
|
})
|
|
.renamed_entries
|
|
.push_back(renamed);
|
|
}
|
|
fn finished_unrenamed_push_back(&mut self, unrenamed: &SimValue<MOpInstance<MOp>>) {
|
|
let entry = self
|
|
.incomplete_back_entry
|
|
.take()
|
|
.unwrap_or_else(|| RobEntries {
|
|
unrenamed: unrenamed.clone(),
|
|
rename_table_updates: Vec::new(),
|
|
renamed_entries: VecDeque::new(),
|
|
});
|
|
self.entries.push_back(entry);
|
|
}
|
|
fn clear(&mut self) {
|
|
let Self {
|
|
next_renamed_mop_id: _,
|
|
entries,
|
|
incomplete_back_entry,
|
|
config: _,
|
|
} = self;
|
|
entries.clear();
|
|
*incomplete_back_entry = None;
|
|
}
|
|
fn unrenamed_back_append_rename_table_update(
|
|
&mut self,
|
|
unrenamed: &SimValue<MOpInstance<MOp>>,
|
|
update: RenameTableUpdate<C>,
|
|
) {
|
|
self.incomplete_back_entry
|
|
.get_or_insert_with(|| RobEntries {
|
|
unrenamed: unrenamed.clone(),
|
|
rename_table_updates: Vec::new(),
|
|
renamed_entries: VecDeque::new(),
|
|
})
|
|
.rename_table_updates
|
|
.push(update);
|
|
}
|
|
}
|
|
|
|
type SimOnlyString = SimOnly<String>;
|
|
#[expect(non_upper_case_globals)]
|
|
const SimOnlyString: SimOnlyString = SimOnlyString::TYPE;
|
|
|
|
#[hdl(get(|c| c.rob_size.get().next_power_of_two()))]
|
|
type PerInsnTimelineLen<C: PhantomConstGet<CpuConfig>> = DynSize;
|
|
|
|
#[hdl(no_static)]
|
|
pub struct RenameExecuteRetireDebugState<C: PhantomConstGet<CpuConfig>> {
|
|
rename_delayed: ArrayVec<MOpInstance<MOp>, TwiceCpuConfigFetchWidth<C>>,
|
|
rename_table: RenameTableDebugState<C>,
|
|
retire_rename_table: RenameTableDebugState<C>,
|
|
rob: ReorderBufferDebugState<C>,
|
|
next_pc_canceling: HdlOption<NextPcCancelingDebugState>,
|
|
unit_canceling: ArrayType<Bool, CpuConfigUnitCount<C>>,
|
|
l1_reg_file: ArrayType<
|
|
ArrayType<HdlOption<PRegValue>, CpuConfig2PowOutRegNumWidth<C>>,
|
|
CpuConfigUnitCount<C>,
|
|
>,
|
|
per_insn_timeline: ArrayType<SimOnlyString, PerInsnTimelineLen<C>>,
|
|
}
|
|
|
|
#[derive(Debug)]
|
|
struct RenameExecuteRetireState<C: PhantomConstCpuConfig> {
|
|
rename_delayed: VecDeque<SimValue<MOpInstance<MOp>>>,
|
|
rename_table: RenameTable<C>,
|
|
retire_rename_table: RenameTable<C>,
|
|
rob: ReorderBuffer<C>,
|
|
next_pc_canceling: Option<NextPcCancelingState>,
|
|
unit_canceling: Box<[bool]>,
|
|
l1_reg_file: Box<[Box<[Option<SimValue<PRegValue>>]>]>,
|
|
l2_reg_file_unit_index: usize,
|
|
config: C,
|
|
}
|
|
|
|
impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
|
|
fn new(config: C) -> Self {
|
|
Self {
|
|
rename_delayed: VecDeque::with_capacity(TwiceCpuConfigFetchWidth[config]),
|
|
rename_table: RenameTable::new(config),
|
|
retire_rename_table: RenameTable::new(config),
|
|
rob: ReorderBuffer::new(config),
|
|
next_pc_canceling: None,
|
|
unit_canceling: vec![false; CpuConfigUnitCount[config]].into_boxed_slice(),
|
|
l1_reg_file: vec![
|
|
vec![None; CpuConfig2PowOutRegNumWidth[config]].into_boxed_slice();
|
|
CpuConfigUnitCount[config]
|
|
]
|
|
.into_boxed_slice(),
|
|
l2_reg_file_unit_index: config
|
|
.get()
|
|
.units
|
|
.iter()
|
|
.position(|unit| unit.kind == UnitKind::TransformedMove)
|
|
.expect("Unit for L2 register file is missing"),
|
|
config,
|
|
}
|
|
}
|
|
fn is_canceling(&self) -> bool {
|
|
self.next_pc_canceling.is_some() || self.unit_canceling.iter().any(|v| *v)
|
|
}
|
|
fn per_insn_timeline(&self) -> SimValue<ArrayType<SimOnlyString, PerInsnTimelineLen<C>>> {
|
|
let len = PerInsnTimelineLen[self.config];
|
|
let retval_ty = ArrayType[SimOnlyString][len];
|
|
assert!(len.is_power_of_two());
|
|
let mask = len - 1;
|
|
let empty_string = SimOnlyValue::new(String::new());
|
|
let mut retval =
|
|
SimValue::from_array_elements(retval_ty, (0..len).map(|_| empty_string.clone()));
|
|
for rob in self.rob.renamed() {
|
|
let masked_id = rob.mop.id.as_int() as usize & mask;
|
|
**retval[masked_id] = fmt::from_fn(|f| {
|
|
if rob.is_speculative {
|
|
f.write_str("(S)")?;
|
|
}
|
|
match rob.progress {
|
|
MOpExecutionProgress::NotStarted => f.write_str("NotStarted")?,
|
|
MOpExecutionProgress::Started => f.write_str("Started")?,
|
|
MOpExecutionProgress::Finished(_) => f.write_str("Finished")?,
|
|
MOpExecutionProgress::Canceled => f.write_str("Canceled")?,
|
|
}
|
|
if rob.caused_cancel.is_some() {
|
|
f.write_str("(caused cancel)")?;
|
|
}
|
|
write!(
|
|
f,
|
|
": {:#x}{}: ",
|
|
rob.mop.pc.as_int(),
|
|
if *rob.mop.is_first_mop_in_insn {
|
|
""
|
|
} else {
|
|
".."
|
|
},
|
|
)?;
|
|
MOpDebug::mop_debug(&rob.mop.mop, f)
|
|
})
|
|
.to_string();
|
|
// TODO
|
|
}
|
|
retval
|
|
}
|
|
#[hdl]
|
|
async fn write_for_debug(
|
|
&self,
|
|
sim: &mut ExternModuleSimulationState,
|
|
state_for_debug: Expr<RenameExecuteRetireDebugState<C>>,
|
|
) {
|
|
let Self {
|
|
ref rename_delayed,
|
|
ref rename_table,
|
|
ref retire_rename_table,
|
|
ref rob,
|
|
ref next_pc_canceling,
|
|
ref unit_canceling,
|
|
ref l1_reg_file,
|
|
l2_reg_file_unit_index: _,
|
|
config: _,
|
|
} = *self;
|
|
sim.write(
|
|
state_for_debug,
|
|
#[hdl(sim)]
|
|
RenameExecuteRetireDebugState::<_> {
|
|
rename_delayed: state_for_debug
|
|
.ty()
|
|
.rename_delayed
|
|
.from_iter_sim(zeroed(StaticType::TYPE), rename_delayed)
|
|
.expect("known to fit"),
|
|
rename_table: rename_table.to_debug_state(),
|
|
retire_rename_table: retire_rename_table.to_debug_state(),
|
|
rob: rob.debug_state(),
|
|
next_pc_canceling: NextPcCancelingState::debug_state(next_pc_canceling),
|
|
unit_canceling,
|
|
l1_reg_file: SimValue::from_array_elements(
|
|
state_for_debug.ty().l1_reg_file,
|
|
l1_reg_file.iter().map(|v| {
|
|
SimValue::from_array_elements(
|
|
state_for_debug.ty().l1_reg_file.element(),
|
|
v.iter().map(|v| {
|
|
if let Some(v) = v {
|
|
#[hdl(sim)]
|
|
HdlSome(v)
|
|
} else {
|
|
#[hdl(sim)]
|
|
HdlNone()
|
|
}
|
|
}),
|
|
)
|
|
}),
|
|
),
|
|
per_insn_timeline: self.per_insn_timeline(),
|
|
},
|
|
)
|
|
.await;
|
|
}
|
|
#[hdl]
|
|
async fn write_to_next_pc_next_insns(
|
|
&self,
|
|
sim: &mut ExternModuleSimulationState,
|
|
next_insns: Expr<HdlOption<ArrayVec<MOpInstance<MOp>, CpuConfigRobSize<C>>>>,
|
|
) {
|
|
sim.write(
|
|
next_insns,
|
|
if self.is_canceling() {
|
|
#[hdl(sim)]
|
|
(next_insns.ty()).HdlNone()
|
|
} else {
|
|
#[hdl(sim)]
|
|
(next_insns.ty()).HdlSome(
|
|
next_insns
|
|
.ty()
|
|
.HdlSome
|
|
.from_iter_sim(
|
|
zeroed(MOpInstance[MOp]),
|
|
self.rename_delayed.iter().chain(self.rob.unrenamed()),
|
|
)
|
|
.ok()
|
|
.expect("known to fit"),
|
|
)
|
|
},
|
|
)
|
|
.await;
|
|
}
|
|
fn space_available_for_unit(&self, unit_index: usize) -> usize {
|
|
let mut retval = self.config.get().unit_max_in_flight(unit_index);
|
|
for renamed in self.rob.renamed() {
|
|
if renamed.unit_index() == unit_index {
|
|
let Some(v) = NonZero::new(retval.get() - 1) else {
|
|
return 0;
|
|
};
|
|
retval = v;
|
|
}
|
|
}
|
|
retval.get()
|
|
}
|
|
#[hdl]
|
|
fn find_free_unit_out_reg(&self, unit_index: usize) -> Option<usize> {
|
|
// TODO: replace searching through instructions and rename tables with tracking when regs are free
|
|
let mut allocated_regs = vec![false; 1 << self.config.get().out_reg_num_width];
|
|
for renamed in self.rob.renamed() {
|
|
if renamed.unit_index() == unit_index {
|
|
allocated_regs[renamed.unit_out_reg_index()] = true;
|
|
}
|
|
MOpTrait::for_each_src_reg_sim_ref(&renamed.mop.mop, &mut |src_reg, _index| {
|
|
#[hdl(sim)]
|
|
let PRegNum::<_> {
|
|
unit_num,
|
|
unit_out_reg,
|
|
} = src_reg.cast_bits_to(PRegNum[self.config]);
|
|
if Some(unit_index) == UnitNum::index_sim(&unit_num) {
|
|
allocated_regs[UnitOutRegNum::value_sim(&unit_out_reg)] = true;
|
|
}
|
|
});
|
|
}
|
|
for entry in self
|
|
.rename_table
|
|
.entries
|
|
.iter()
|
|
.chain(self.retire_rename_table.entries.iter())
|
|
{
|
|
#[hdl(sim)]
|
|
match entry {
|
|
RenameTableEntry::<_>::L1(entry) => {
|
|
if Some(unit_index) == UnitNum::index_sim(&entry.unit_num) {
|
|
allocated_regs[UnitOutRegNum::value_sim(&entry.unit_out_reg)] = true;
|
|
}
|
|
}
|
|
RenameTableEntry::<_>::L2(_) => {}
|
|
}
|
|
}
|
|
allocated_regs.iter().position(|v| !v)
|
|
}
|
|
#[hdl]
|
|
fn find_free_l2_reg(&self) -> Option<usize> {
|
|
// TODO: replace searching through instructions and rename tables with tracking when regs are free
|
|
let mut allocated_regs = vec![false; L2RegNum.l2_reg_count()];
|
|
for renamed in self.rob.renamed() {
|
|
#[hdl(sim)]
|
|
if let RenamedMOp::<_>::TransformedMove(l2_register_file_op) = &renamed.mop.mop {
|
|
let l2_reg = #[hdl(sim)]
|
|
match l2_register_file_op {
|
|
L2RegisterFileMOp::<_, _>::ReadL2Reg(v) => &v.common.imm,
|
|
L2RegisterFileMOp::<_, _>::WriteL2Reg(v) => &v.common.imm,
|
|
};
|
|
allocated_regs[L2RegNum::value_sim(l2_reg)] = true;
|
|
}
|
|
}
|
|
for entry in self
|
|
.rename_table
|
|
.entries
|
|
.iter()
|
|
.chain(self.retire_rename_table.entries.iter())
|
|
{
|
|
#[hdl(sim)]
|
|
match entry {
|
|
RenameTableEntry::<_>::L1(_) => {}
|
|
RenameTableEntry::<_>::L2(entry) => {
|
|
allocated_regs[L2RegNum::value_sim(entry)] = true;
|
|
}
|
|
}
|
|
}
|
|
allocated_regs.iter().position(|v| !v)
|
|
}
|
|
fn add_renamed_with_new_id(
|
|
&mut self,
|
|
unrenamed: &SimValue<MOpInstance<MOp>>,
|
|
renamed: RobEntry<C>,
|
|
) {
|
|
self.l1_reg_file[renamed.unit_index()][renamed.unit_out_reg_index()] = None;
|
|
self.rob.renamed_push_back_with_new_id(unrenamed, renamed);
|
|
}
|
|
fn update_rename_table(
|
|
&mut self,
|
|
unrenamed: &SimValue<MOpInstance<MOp>>,
|
|
update: RenameTableUpdate<C>,
|
|
) {
|
|
self.rename_table.update(&update, "rename_table");
|
|
self.rob
|
|
.unrenamed_back_append_rename_table_update(unrenamed, update);
|
|
}
|
|
#[hdl]
|
|
fn try_rename(
|
|
&mut self,
|
|
insn: SimValue<MOpInstance<MOp>>,
|
|
) -> Result<(), SimValue<MOpInstance<MOp>>> {
|
|
if self.rob.unrenamed_len() >= self.config.get().rob_size.get() {
|
|
return Err(insn);
|
|
}
|
|
if self.rob.renamed_len() >= self.config.get().rob_size.get() {
|
|
return Err(insn);
|
|
}
|
|
let unit_kind = UnitMOp::kind_sim(&insn.mop);
|
|
#[hdl(sim)]
|
|
if let MOp::TransformedMove(move_reg_mop) = &insn.mop {
|
|
let mut src_regs = [MOpRegNum::CONST_ZERO_REG_NUM; 1];
|
|
MOpTrait::for_each_src_reg_sim_ref(move_reg_mop, &mut |src_reg, index| {
|
|
src_regs[index] = src_reg.as_int() as u32;
|
|
});
|
|
let [src_reg] = src_regs;
|
|
let renamed_reg = self.rename_table.entries[src_reg as usize].clone();
|
|
println!(
|
|
"moving from {src_reg:#x} renamed: {:?}",
|
|
RenameTableEntry::debug_sim(&renamed_reg),
|
|
);
|
|
let unrenamed_dest_regs =
|
|
MOpDestReg::regs_sim(MOpTrait::dest_reg_sim_ref(move_reg_mop));
|
|
assert!(self.rob.incomplete_back_entry.is_none());
|
|
for unrenamed_reg_num in unrenamed_dest_regs {
|
|
self.update_rename_table(
|
|
&insn,
|
|
RenameTableUpdate::Write {
|
|
unrenamed_reg_num,
|
|
new: renamed_reg.clone(),
|
|
},
|
|
);
|
|
}
|
|
self.rob.finished_unrenamed_push_back(&insn);
|
|
return Ok(());
|
|
}
|
|
#[derive(Clone, Copy)]
|
|
struct ChosenUnit {
|
|
unit_index: usize,
|
|
out_reg_num: Option<usize>,
|
|
space_available: usize,
|
|
}
|
|
impl ChosenUnit {
|
|
fn is_better_than(self, other: Self) -> bool {
|
|
let Self {
|
|
unit_index: _,
|
|
out_reg_num,
|
|
space_available,
|
|
} = self;
|
|
if out_reg_num.is_some() != other.out_reg_num.is_some() {
|
|
out_reg_num.is_some()
|
|
} else {
|
|
space_available > other.space_available
|
|
}
|
|
}
|
|
}
|
|
let mut chosen_unit = None;
|
|
for (unit_index, unit_config) in self.config.get().units.iter().enumerate() {
|
|
if unit_config.kind != unit_kind {
|
|
continue;
|
|
}
|
|
let cur_unit = ChosenUnit {
|
|
unit_index,
|
|
out_reg_num: self.find_free_unit_out_reg(unit_index),
|
|
space_available: self.space_available_for_unit(unit_index),
|
|
};
|
|
let chosen_unit = chosen_unit.get_or_insert(cur_unit);
|
|
if cur_unit.is_better_than(*chosen_unit) {
|
|
*chosen_unit = cur_unit;
|
|
}
|
|
}
|
|
let Some(ChosenUnit {
|
|
unit_index,
|
|
out_reg_num,
|
|
space_available,
|
|
}) = chosen_unit
|
|
else {
|
|
panic!(
|
|
"there are no units of kind: {unit_kind:?}:\n{:?}",
|
|
self.config,
|
|
);
|
|
};
|
|
if space_available == 0 {
|
|
return Err(insn);
|
|
}
|
|
let Some(out_reg_num) = out_reg_num else {
|
|
return if self.space_available_for_unit(self.l2_reg_file_unit_index) > 0
|
|
&& let Some(l2_reg_index) = self.find_free_l2_reg()
|
|
{
|
|
todo!("maybe start a L2 register file store");
|
|
} else {
|
|
Err(insn)
|
|
};
|
|
};
|
|
let out_reg_num_sim = UnitOutRegNum[self.config].new_sim(out_reg_num);
|
|
#[hdl(sim)]
|
|
let MOpInstance::<_> {
|
|
fetch_block_id,
|
|
id: _,
|
|
pc,
|
|
predicted_next_pc,
|
|
size_in_bytes,
|
|
is_first_mop_in_insn,
|
|
mop,
|
|
} = &insn;
|
|
let mut needed_load = None;
|
|
let unrenamed_dest_regs = MOpDestReg::regs_sim(MOpTrait::dest_reg_sim_ref(mop));
|
|
let renamed_dest_reg = #[hdl(sim)]
|
|
PRegNum::<_> {
|
|
unit_num: UnitNum[self.config].from_index_sim(unit_index),
|
|
unit_out_reg: out_reg_num_sim,
|
|
};
|
|
let mop = MOpTrait::map_regs_sim(
|
|
mop,
|
|
&renamed_dest_reg,
|
|
CpuConfigPRegNumWidth[self.config],
|
|
&mut |src_reg, index| {
|
|
let renamed = &self.rename_table.entries[src_reg.as_int() as usize];
|
|
println!(
|
|
"renaming src[{index}] from {src_reg:?} to {:?}",
|
|
RenameTableEntry::debug_sim(renamed),
|
|
);
|
|
#[hdl(sim)]
|
|
match renamed {
|
|
RenameTableEntry::<_>::L1(v) => v.cast_to_bits(),
|
|
RenameTableEntry::<_>::L2(v) => {
|
|
needed_load.get_or_insert_with(|| v.clone());
|
|
PRegNum[self.config]
|
|
.const_zero()
|
|
.cast_to_bits()
|
|
.into_sim_value()
|
|
}
|
|
}
|
|
},
|
|
);
|
|
if let Some(needed_load) = needed_load {
|
|
return if let Some(out_reg) = self.find_free_unit_out_reg(self.l2_reg_file_unit_index)
|
|
&& self.space_available_for_unit(self.l2_reg_file_unit_index) > 0
|
|
{
|
|
let dest = #[hdl(sim)]
|
|
PRegNum::<_> {
|
|
unit_num: UnitNum[self.config].from_index_sim(self.l2_reg_file_unit_index),
|
|
unit_out_reg: UnitOutRegNum[self.config].new_sim(out_reg),
|
|
};
|
|
self.update_rename_table(
|
|
&insn,
|
|
RenameTableUpdate::UpdateForReadL2Reg {
|
|
dest: dest.clone(),
|
|
src: needed_load.clone(),
|
|
},
|
|
);
|
|
self.add_renamed_with_new_id(
|
|
&insn,
|
|
RobEntry::new(
|
|
#[hdl(sim)]
|
|
MOpInstance::<_> {
|
|
fetch_block_id,
|
|
id: MOpId.zero(), // filled in by add_renamed_with_new_id
|
|
pc,
|
|
predicted_next_pc,
|
|
size_in_bytes,
|
|
is_first_mop_in_insn,
|
|
mop: ReadL2RegMOp::read_l2_reg::<RenamedMOp<C>>(
|
|
dest,
|
|
repeat(RenamedSrcRegUInt[self.config].zero(), ConstUsize),
|
|
needed_load,
|
|
),
|
|
},
|
|
),
|
|
);
|
|
Ok(())
|
|
} else {
|
|
Err(insn)
|
|
};
|
|
}
|
|
let mop = UnitMOp::with_transformed_move_op_sim(
|
|
mop,
|
|
RenamedMOp[self.config].TransformedMove,
|
|
|_move_reg| unreachable!(),
|
|
);
|
|
let renamed_dest_reg = #[hdl(sim)]
|
|
(RenameTableEntry[self.config]).L1(renamed_dest_reg);
|
|
for unrenamed_reg_num in unrenamed_dest_regs {
|
|
self.update_rename_table(
|
|
&insn,
|
|
RenameTableUpdate::Write {
|
|
unrenamed_reg_num,
|
|
new: renamed_dest_reg.clone(),
|
|
},
|
|
);
|
|
}
|
|
self.add_renamed_with_new_id(
|
|
&insn,
|
|
RobEntry::new(
|
|
#[hdl(sim)]
|
|
MOpInstance::<_> {
|
|
fetch_block_id,
|
|
id: MOpId.zero(), // filled in by add_renamed_with_new_id
|
|
pc,
|
|
predicted_next_pc,
|
|
size_in_bytes,
|
|
is_first_mop_in_insn,
|
|
mop,
|
|
},
|
|
),
|
|
);
|
|
self.rob.finished_unrenamed_push_back(&insn);
|
|
Ok(())
|
|
}
|
|
#[hdl]
|
|
fn get_unit_start(&self, unit_index: usize) -> SimValue<HdlOption<UnitStart<C>>> {
|
|
let ret_ty = HdlOption[UnitStart[self.config]];
|
|
if self.is_canceling() {
|
|
let retval = #[hdl(sim)]
|
|
ret_ty.HdlNone();
|
|
return retval; // separate variable to work around rust-analyzer parse error
|
|
}
|
|
let zero_reg = PRegNum[self.config].const_zero().into_sim_value();
|
|
let zero_value = zeroed(PRegValue);
|
|
for rob in self.rob.renamed() {
|
|
if let MOpExecutionProgress::NotStarted = rob.progress
|
|
&& rob.unit_index() == unit_index
|
|
{
|
|
let mut src_values: [_; COMMON_MOP_SRC_LEN] =
|
|
std::array::from_fn(|_| Some(zero_value.clone()));
|
|
MOpTrait::for_each_src_reg_sim_ref(&rob.mop.mop, &mut |src_reg, index| {
|
|
let src_reg = src_reg.cast_bits_to(zero_reg.ty());
|
|
#[hdl(sim)]
|
|
let PRegNum::<_> {
|
|
unit_num,
|
|
unit_out_reg,
|
|
} = &src_reg;
|
|
if let Some(src_unit_index) = UnitNum::index_sim(unit_num) {
|
|
src_values[index] = self.l1_reg_file[src_unit_index]
|
|
[UnitOutRegNum::value_sim(unit_out_reg)]
|
|
.clone();
|
|
} else {
|
|
assert_eq!(src_reg, zero_reg);
|
|
src_values[index] = Some(zeroed(PRegValue));
|
|
}
|
|
});
|
|
if src_values.iter().all(|v| v.is_some()) {
|
|
let src_values: [SimValue<_>; 3] = src_values.map(Option::unwrap);
|
|
let retval = #[hdl(sim)]
|
|
ret_ty.HdlSome(
|
|
#[hdl(sim)]
|
|
UnitStart::<_> {
|
|
mop: &rob.mop,
|
|
src_values,
|
|
config: self.config,
|
|
},
|
|
);
|
|
return retval;
|
|
}
|
|
}
|
|
}
|
|
#[hdl(sim)]
|
|
ret_ty.HdlNone()
|
|
}
|
|
#[hdl]
|
|
fn get_unit_mop_is_no_longer_speculative(
|
|
&self,
|
|
unit_index: usize,
|
|
) -> SimValue<HdlOption<UnitMOpIsNoLongerSpeculative<C>>> {
|
|
let ret_ty = HdlOption[UnitMOpIsNoLongerSpeculative[self.config]];
|
|
if self.is_canceling() {
|
|
let retval = #[hdl(sim)]
|
|
ret_ty.HdlNone();
|
|
return retval; // separate variable to work around rust-analyzer parse error
|
|
}
|
|
for rob in self.rob.renamed() {
|
|
if rob.unit_index() == unit_index
|
|
&& !rob.is_speculative
|
|
&& !rob.sent_is_no_longer_speculative
|
|
{
|
|
let retval = #[hdl(sim)]
|
|
ret_ty.HdlSome(
|
|
#[hdl(sim)]
|
|
UnitMOpIsNoLongerSpeculative::<_> {
|
|
id: &rob.mop.id,
|
|
config: self.config,
|
|
},
|
|
);
|
|
return retval; // separate variable to work around rust-analyzer parse error
|
|
}
|
|
}
|
|
#[hdl(sim)]
|
|
ret_ty.HdlNone()
|
|
}
|
|
#[hdl]
|
|
fn unit_finished(&mut self, finished: SimValue<UnitFinished<C>>) {
|
|
#[hdl(sim)]
|
|
let UnitFinished::<_> {
|
|
id,
|
|
finished_successfully,
|
|
caused_cancel: unit_caused_cancel,
|
|
config: _,
|
|
} = finished;
|
|
assert!(!self.is_canceling());
|
|
let rob = self.rob.renamed_by_id_mut(&id);
|
|
let unit_index = rob.unit_index();
|
|
let out_reg_index = rob.unit_out_reg_index();
|
|
let RobEntry {
|
|
mop: _,
|
|
is_speculative: _,
|
|
sent_is_no_longer_speculative: _,
|
|
can_cause_cancel,
|
|
progress,
|
|
caused_cancel,
|
|
} = rob;
|
|
assert!(matches!(progress, MOpExecutionProgress::Started));
|
|
assert!(caused_cancel.is_none());
|
|
#[hdl(sim)]
|
|
if let HdlSome(finished_successfully) = finished_successfully {
|
|
#[hdl(sim)]
|
|
let UnitFinishedSuccessfully::<_> {
|
|
dest: _,
|
|
dest_value,
|
|
predictor_op,
|
|
} = finished_successfully;
|
|
let l1_reg = &mut self.l1_reg_file[unit_index][out_reg_index];
|
|
assert!(l1_reg.is_none());
|
|
*l1_reg = Some(dest_value);
|
|
*progress = MOpExecutionProgress::Finished(predictor_op);
|
|
} else {
|
|
*progress = MOpExecutionProgress::Canceled;
|
|
}
|
|
#[hdl(sim)]
|
|
if let HdlSome(unit_caused_cancel) = unit_caused_cancel {
|
|
assert!(
|
|
*can_cause_cancel,
|
|
"MOp {id:?} said it won't cause a cancel, then caused a cancel: {unit_caused_cancel:#?}"
|
|
);
|
|
*caused_cancel = Some(unit_caused_cancel);
|
|
} else {
|
|
assert!(
|
|
matches!(progress, MOpExecutionProgress::Finished(_)),
|
|
"MOp {id:?} must finish successfully and/or cause a cancel: progress={progress:?}",
|
|
);
|
|
}
|
|
}
|
|
fn get_from_post_decode_ready(&self) -> usize {
|
|
if self.is_canceling() {
|
|
0
|
|
} else {
|
|
TwiceCpuConfigFetchWidth[self.config]
|
|
.saturating_sub(self.rename_delayed.len())
|
|
.min(CpuConfigFetchWidth[self.config])
|
|
.min(
|
|
CpuConfigRobSize[self.config]
|
|
.saturating_sub(self.rename_delayed.len())
|
|
.saturating_sub(self.rob.unrenamed_len()),
|
|
)
|
|
}
|
|
}
|
|
fn handle_from_post_decode(&mut self, insns: &[SimValue<MOpInstance<MOp>>]) {
|
|
if insns.is_empty() {
|
|
return;
|
|
}
|
|
assert!(!self.is_canceling());
|
|
for insn in insns {
|
|
self.rename_delayed.push_back(insn.clone());
|
|
}
|
|
for _ in 0..CpuConfigFetchWidth[self.config] {
|
|
let Some(insn) = self.rename_delayed.pop_front() else {
|
|
break;
|
|
};
|
|
match self.try_rename(insn) {
|
|
Ok(()) => {}
|
|
Err(insn) => {
|
|
self.rename_delayed.push_front(insn);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
#[hdl]
|
|
fn finish_receive_cancel_from_post_decode(&mut self) {
|
|
let Self {
|
|
rename_delayed,
|
|
rename_table,
|
|
retire_rename_table,
|
|
rob,
|
|
next_pc_canceling,
|
|
unit_canceling: _,
|
|
l1_reg_file,
|
|
l2_reg_file_unit_index: _,
|
|
config: _,
|
|
} = self;
|
|
assert_eq!(
|
|
*next_pc_canceling,
|
|
Some(NextPcCancelingState::NeedReceiveCancel)
|
|
);
|
|
rename_delayed.clear();
|
|
rename_table.clone_from(retire_rename_table);
|
|
rob.clear();
|
|
*next_pc_canceling = None;
|
|
}
|
|
#[hdl]
|
|
fn finish_send_cancel_to_next_pc(&mut self) {
|
|
assert!(matches!(
|
|
self.next_pc_canceling,
|
|
Some(NextPcCancelingState::NeedSendCancel(_))
|
|
));
|
|
self.next_pc_canceling = Some(NextPcCancelingState::NeedReceiveCancel);
|
|
}
|
|
#[hdl]
|
|
fn peek_retiring_insns(&self) -> Vec<SimValue<NextPcPredictorOp<C>>> {
|
|
let mut retval = Vec::new();
|
|
let mut prev_caused_cancel = false;
|
|
for RobEntries {
|
|
unrenamed,
|
|
rename_table_updates: _,
|
|
renamed_entries,
|
|
} in &self.rob.entries
|
|
{
|
|
if retval.len() >= self.config.get().fetch_width.get() || prev_caused_cancel {
|
|
return retval;
|
|
}
|
|
let mut unrenamed_op = #[hdl(sim)]
|
|
NextPcPredictorOp::<_> {
|
|
call_stack_op: #[hdl(sim)]
|
|
CallStackOp.None(),
|
|
cond_br_taken: #[hdl(sim)]
|
|
HdlNone(),
|
|
config: self.config,
|
|
};
|
|
for renamed in renamed_entries {
|
|
if prev_caused_cancel {
|
|
return retval;
|
|
}
|
|
if let RobEntry {
|
|
mop,
|
|
is_speculative,
|
|
sent_is_no_longer_speculative,
|
|
can_cause_cancel,
|
|
progress: MOpExecutionProgress::Finished(renamed_op),
|
|
caused_cancel,
|
|
} = renamed
|
|
{
|
|
prev_caused_cancel = caused_cancel.is_some();
|
|
#[hdl(sim)]
|
|
let NextPcPredictorOp::<_> {
|
|
call_stack_op,
|
|
cond_br_taken,
|
|
config: _,
|
|
} = renamed_op;
|
|
#[hdl(sim)]
|
|
if let CallStackOp::None = &unrenamed_op.call_stack_op {
|
|
unrenamed_op.call_stack_op = call_stack_op.clone();
|
|
}
|
|
#[hdl(sim)]
|
|
if let HdlNone = &unrenamed_op.cond_br_taken {
|
|
unrenamed_op.cond_br_taken = cond_br_taken.clone();
|
|
}
|
|
} else {
|
|
return retval;
|
|
}
|
|
}
|
|
retval.push(unrenamed_op);
|
|
}
|
|
retval
|
|
}
|
|
#[hdl]
|
|
fn retire_peek(&self) -> SimValue<HdlOption<RetireToNextPcInterfaceInner<C>>> {
|
|
let ty = RetireToNextPcInterfaceInner[self.config];
|
|
let ret_ty = HdlOption[ty];
|
|
let next_pc_predictor_op = NextPcPredictorOp[self.config];
|
|
if let Some(NextPcCancelingState::NeedSendCancel(v)) = &self.next_pc_canceling {
|
|
#[hdl(sim)]
|
|
ret_ty.HdlSome(
|
|
#[hdl(sim)]
|
|
ty.CancelAndStartAt(v),
|
|
)
|
|
} else if self.is_canceling() {
|
|
#[hdl(sim)]
|
|
ret_ty.HdlNone()
|
|
} else {
|
|
let retiring_insns = self.peek_retiring_insns();
|
|
if retiring_insns.is_empty() {
|
|
#[hdl(sim)]
|
|
ret_ty.HdlNone()
|
|
} else {
|
|
#[hdl(sim)]
|
|
ret_ty.HdlSome(
|
|
#[hdl(sim)]
|
|
ty.RetiredInstructions(
|
|
ty.RetiredInstructions
|
|
.from_iter_sim(zeroed(next_pc_predictor_op), retiring_insns)
|
|
.expect("known to fit"),
|
|
),
|
|
)
|
|
}
|
|
}
|
|
}
|
|
#[hdl]
|
|
fn retire_one(&mut self, retire: &SimValue<NextPcPredictorOp<C>>) {
|
|
assert!(!self.is_canceling());
|
|
#[hdl(sim)]
|
|
let NextPcPredictorOp::<_> {
|
|
call_stack_op: _,
|
|
cond_br_taken: _,
|
|
config: _,
|
|
} = retire;
|
|
let Some(RobEntries {
|
|
unrenamed: _,
|
|
rename_table_updates,
|
|
renamed_entries,
|
|
}) = self.rob.entries.pop_front()
|
|
else {
|
|
unreachable!();
|
|
};
|
|
rename_table_updates
|
|
.iter()
|
|
.for_each(|v| self.retire_rename_table.update(v, "retire_rename_table"));
|
|
for RobEntry {
|
|
mop: _,
|
|
is_speculative: _,
|
|
sent_is_no_longer_speculative: _,
|
|
can_cause_cancel: _,
|
|
progress,
|
|
caused_cancel,
|
|
} in renamed_entries
|
|
{
|
|
assert!(matches!(progress, MOpExecutionProgress::Finished(_)));
|
|
if let Some(caused_cancel) = caused_cancel {
|
|
self.start_cancel(caused_cancel);
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
#[hdl]
|
|
fn start_cancel(&mut self, caused_cancel: SimValue<UnitCausedCancel<C>>) {
|
|
assert!(!self.is_canceling());
|
|
#[hdl(sim)]
|
|
let UnitCausedCancel::<_> {
|
|
id: _,
|
|
start_at_pc,
|
|
config: _,
|
|
} = caused_cancel;
|
|
self.next_pc_canceling = Some(NextPcCancelingState::NeedSendCancel(start_at_pc.as_int()));
|
|
self.unit_canceling.fill(true);
|
|
}
|
|
#[hdl]
|
|
fn step(&mut self) {
|
|
if self.is_canceling() {
|
|
return;
|
|
}
|
|
for renamed in self.rob.renamed_mut() {
|
|
let can_cause_cancel = match renamed.progress {
|
|
MOpExecutionProgress::NotStarted => break,
|
|
MOpExecutionProgress::Started => renamed.can_cause_cancel,
|
|
MOpExecutionProgress::Finished(_) => renamed.caused_cancel.is_some(),
|
|
MOpExecutionProgress::Canceled => true,
|
|
};
|
|
renamed.can_cause_cancel = can_cause_cancel;
|
|
renamed.is_speculative = false;
|
|
if can_cause_cancel {
|
|
break;
|
|
}
|
|
}
|
|
let first_renamed = self.rob.renamed().next();
|
|
if let Some(RobEntry {
|
|
mop: _,
|
|
is_speculative: _,
|
|
sent_is_no_longer_speculative: _,
|
|
can_cause_cancel: _,
|
|
progress: MOpExecutionProgress::Canceled,
|
|
caused_cancel: Some(caused_cancel),
|
|
}) = first_renamed
|
|
{
|
|
let caused_cancel = caused_cancel.clone();
|
|
self.start_cancel(caused_cancel);
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
|
|
#[hdl]
|
|
async fn rename_execute_retire_run(
|
|
mut sim: ExternModuleSimulationState,
|
|
cd: Expr<ClockDomain>,
|
|
from_post_decode: Expr<PostDecodeOutputInterface<PhantomConst<CpuConfig>>>,
|
|
to_next_pc: Expr<RetireToNextPcInterface<PhantomConst<CpuConfig>>>,
|
|
to_units: Expr<ExecuteToUnitInterfaces<PhantomConst<CpuConfig>>>,
|
|
state_for_debug: Expr<RenameExecuteRetireDebugState<PhantomConst<CpuConfig>>>,
|
|
config: PhantomConst<CpuConfig>,
|
|
) {
|
|
let mut state = RenameExecuteRetireState::new(config);
|
|
loop {
|
|
state
|
|
.write_to_next_pc_next_insns(&mut sim, to_next_pc.next_insns)
|
|
.await;
|
|
state.write_for_debug(&mut sim, state_for_debug).await;
|
|
let from_post_decode_ready = state.get_from_post_decode_ready();
|
|
assert!(from_post_decode_ready <= from_post_decode.ty().ready.end());
|
|
sim.write(from_post_decode.ready, from_post_decode_ready)
|
|
.await;
|
|
sim.write(
|
|
from_post_decode.cancel.ready,
|
|
state.next_pc_canceling == Some(NextPcCancelingState::NeedReceiveCancel),
|
|
)
|
|
.await;
|
|
let retire_peek = state.retire_peek();
|
|
sim.write(to_next_pc.inner.data, &retire_peek).await;
|
|
let is_canceling = state.is_canceling();
|
|
for (unit_index, to_unit) in ExecuteToUnitInterfaces::unit_fields(to_units)
|
|
.into_iter()
|
|
.enumerate()
|
|
{
|
|
#[hdl]
|
|
let ExecuteToUnitInterface::<_> {
|
|
start,
|
|
cancel_all,
|
|
is_no_longer_speculative,
|
|
cant_cause_cancel,
|
|
finished,
|
|
config: _,
|
|
} = to_unit;
|
|
sim.write(start.data, state.get_unit_start(unit_index))
|
|
.await;
|
|
sim.write(
|
|
cancel_all.data,
|
|
if state.unit_canceling[unit_index] {
|
|
#[hdl(sim)]
|
|
HdlSome(())
|
|
} else {
|
|
#[hdl(sim)]
|
|
HdlNone()
|
|
},
|
|
)
|
|
.await;
|
|
sim.write(
|
|
is_no_longer_speculative.data,
|
|
state.get_unit_mop_is_no_longer_speculative(unit_index),
|
|
)
|
|
.await;
|
|
sim.write(cant_cause_cancel.ready, !is_canceling).await;
|
|
sim.write(finished.ready, !is_canceling).await;
|
|
}
|
|
sim.wait_for_clock_edge(cd.clk).await;
|
|
let from_post_decode_insns = sim.read_past(from_post_decode.insns, cd.clk).await;
|
|
let from_post_decode_insns = ArrayVec::elements_sim_ref(&from_post_decode_insns);
|
|
state.handle_from_post_decode(
|
|
from_post_decode_insns
|
|
.get(..from_post_decode_ready)
|
|
.unwrap_or(from_post_decode_insns),
|
|
);
|
|
for (unit_index, to_unit) in ExecuteToUnitInterfaces::unit_fields(to_units)
|
|
.into_iter()
|
|
.enumerate()
|
|
{
|
|
#[hdl]
|
|
let ExecuteToUnitInterface::<_> {
|
|
start,
|
|
cancel_all,
|
|
is_no_longer_speculative,
|
|
cant_cause_cancel,
|
|
finished,
|
|
config: _,
|
|
} = to_unit;
|
|
if sim.read_past_bool(start.ready, cd.clk).await {
|
|
#[hdl(sim)]
|
|
if let HdlSome(start) = sim.read_past(start.data, cd.clk).await {
|
|
assert!(!state.is_canceling());
|
|
let RobEntry {
|
|
mop: _,
|
|
is_speculative: _,
|
|
sent_is_no_longer_speculative: _,
|
|
can_cause_cancel: _,
|
|
progress,
|
|
caused_cancel,
|
|
} = state.rob.renamed_by_id_mut(&start.mop.id);
|
|
assert!(caused_cancel.is_none());
|
|
assert!(matches!(progress, MOpExecutionProgress::NotStarted));
|
|
*progress = MOpExecutionProgress::Started;
|
|
}
|
|
}
|
|
if sim.read_past_bool(cancel_all.ready, cd.clk).await {
|
|
#[hdl(sim)]
|
|
if let HdlSome(v) = sim.read_past(cancel_all.data, cd.clk).await {
|
|
let () = *v;
|
|
assert!(state.unit_canceling[unit_index]);
|
|
state.unit_canceling[unit_index] = false;
|
|
}
|
|
}
|
|
if sim
|
|
.read_past_bool(is_no_longer_speculative.ready, cd.clk)
|
|
.await
|
|
{
|
|
#[hdl(sim)]
|
|
if let HdlSome(is_no_longer_speculative) =
|
|
sim.read_past(is_no_longer_speculative.data, cd.clk).await
|
|
{
|
|
assert!(!state.is_canceling());
|
|
if let Some(RobEntry {
|
|
mop: _,
|
|
is_speculative,
|
|
sent_is_no_longer_speculative,
|
|
can_cause_cancel: _,
|
|
progress: _,
|
|
caused_cancel: _,
|
|
}) = state
|
|
.rob
|
|
.try_renamed_by_id_mut(&is_no_longer_speculative.id)
|
|
{
|
|
assert!(!*is_speculative);
|
|
assert!(!*sent_is_no_longer_speculative);
|
|
*sent_is_no_longer_speculative = true;
|
|
}
|
|
}
|
|
}
|
|
if sim.read_past_bool(cant_cause_cancel.ready, cd.clk).await {
|
|
#[hdl(sim)]
|
|
if let HdlSome(cant_cause_cancel) =
|
|
sim.read_past(cant_cause_cancel.data, cd.clk).await
|
|
{
|
|
#[hdl(sim)]
|
|
let UnitMOpCantCauseCancel::<_> { id, config: _ } = cant_cause_cancel;
|
|
assert!(!state.is_canceling());
|
|
let RobEntry {
|
|
mop: _,
|
|
is_speculative: _,
|
|
sent_is_no_longer_speculative: _,
|
|
can_cause_cancel,
|
|
progress,
|
|
caused_cancel,
|
|
} = state.rob.renamed_by_id_mut(&id);
|
|
assert!(caused_cancel.is_none());
|
|
assert!(!matches!(progress, MOpExecutionProgress::Canceled));
|
|
*can_cause_cancel = false;
|
|
}
|
|
}
|
|
if sim.read_past_bool(finished.ready, cd.clk).await {
|
|
#[hdl(sim)]
|
|
if let HdlSome(finished) = sim.read_past(finished.data, cd.clk).await {
|
|
state.unit_finished(finished);
|
|
}
|
|
}
|
|
}
|
|
match &mut state.next_pc_canceling {
|
|
Some(NextPcCancelingState::NeedReceiveCancel) => {
|
|
#[hdl(sim)]
|
|
if let HdlSome(_) = sim.read_past(from_post_decode.cancel.data, cd.clk).await {
|
|
state.finish_receive_cancel_from_post_decode();
|
|
}
|
|
}
|
|
Some(NextPcCancelingState::NeedSendCancel(_)) => {
|
|
if sim.read_past_bool(to_next_pc.inner.ready, cd.clk).await {
|
|
state.finish_send_cancel_to_next_pc();
|
|
}
|
|
}
|
|
None => {
|
|
if sim.read_past_bool(to_next_pc.inner.ready, cd.clk).await {
|
|
#[hdl(sim)]
|
|
if let HdlSome(v) = retire_peek {
|
|
let ops =
|
|
#[hdl(sim)]
|
|
if let RetireToNextPcInterfaceInner::<_>::RetiredInstructions(ops) = v {
|
|
ops
|
|
} else {
|
|
unreachable!()
|
|
};
|
|
for op in ArrayVec::elements_sim_ref(&ops) {
|
|
state.retire_one(op);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
state.step();
|
|
}
|
|
}
|
|
|
|
#[hdl_module(extern)]
|
|
pub fn rename_execute_retire(config: PhantomConst<CpuConfig>) {
|
|
#[hdl]
|
|
let cd: ClockDomain = m.input();
|
|
#[hdl]
|
|
let from_post_decode: PostDecodeOutputInterface<PhantomConst<CpuConfig>> =
|
|
m.input(PostDecodeOutputInterface[config]);
|
|
#[hdl]
|
|
let to_next_pc: RetireToNextPcInterface<PhantomConst<CpuConfig>> =
|
|
m.output(RetireToNextPcInterface[config]);
|
|
#[hdl]
|
|
let to_units: ExecuteToUnitInterfaces<PhantomConst<CpuConfig>> =
|
|
m.output(ExecuteToUnitInterfaces[config]);
|
|
#[hdl]
|
|
let state_for_debug: RenameExecuteRetireDebugState<PhantomConst<CpuConfig>> =
|
|
m.output(RenameExecuteRetireDebugState[config]);
|
|
m.register_clock_for_past(cd.clk);
|
|
m.extern_module_simulation_fn(
|
|
(
|
|
cd,
|
|
from_post_decode,
|
|
to_next_pc,
|
|
to_units,
|
|
state_for_debug,
|
|
config,
|
|
),
|
|
async |args, mut sim| {
|
|
let (cd, from_post_decode, to_next_pc, to_units, state_for_debug, config) = args;
|
|
sim.write(state_for_debug, state_for_debug.ty().sim_value_default())
|
|
.await;
|
|
sim.resettable(
|
|
cd,
|
|
async |mut sim: ExternModuleSimulationState| {
|
|
sim.write(from_post_decode.ready, 0usize).await;
|
|
sim.write(from_post_decode.cancel.ready, false).await;
|
|
sim.write(to_next_pc.inner.data, to_next_pc.ty().inner.data.HdlNone())
|
|
.await;
|
|
sim.write(to_next_pc.next_insns, to_next_pc.ty().next_insns.HdlNone())
|
|
.await;
|
|
for unit_field in ExecuteToUnitInterfaces::unit_fields(to_units) {
|
|
#[hdl]
|
|
let ExecuteToUnitInterface::<_> {
|
|
start,
|
|
cancel_all,
|
|
is_no_longer_speculative,
|
|
cant_cause_cancel,
|
|
finished,
|
|
config: _,
|
|
} = unit_field;
|
|
sim.write(
|
|
start.data,
|
|
#[hdl(sim)]
|
|
(start.ty().data).HdlNone(),
|
|
)
|
|
.await;
|
|
sim.write(
|
|
cancel_all.data,
|
|
#[hdl(sim)]
|
|
HdlNone(),
|
|
)
|
|
.await;
|
|
sim.write(
|
|
is_no_longer_speculative.data,
|
|
#[hdl(sim)]
|
|
(is_no_longer_speculative.ty().data).HdlNone(),
|
|
)
|
|
.await;
|
|
sim.write(cant_cause_cancel.ready, false).await;
|
|
sim.write(finished.ready, false).await;
|
|
}
|
|
},
|
|
|sim, ()| {
|
|
rename_execute_retire_run(
|
|
sim,
|
|
cd,
|
|
from_post_decode,
|
|
to_next_pc,
|
|
to_units,
|
|
state_for_debug,
|
|
config,
|
|
)
|
|
},
|
|
)
|
|
.await;
|
|
},
|
|
);
|
|
}
|