crates/cpu/src/rename_execute_retire.rs

@@ -14,7 +14,7 @@ use crate::{
         UnitNum, UnitOutRegNum, WriteL2RegMOp,
     },
     next_pc::{CallStackOp, SimValueDefault},
-    register::PRegValue,
+    register::{FlagsMode, PRegFlagsPowerISA, PRegValue},
     rename_execute_retire::{
         rename_table::{RenameTable, RenameTableDebugState, RenameTableEntry, RenameTableUpdate},
         reorder_buffer::{ReorderBuffer, ReorderBufferDebugState, RobEntry},
@@ -126,6 +126,25 @@ pub struct RetireToNextPcInterface<C: PhantomConstGet<CpuConfig>> {
 pub type RenamedMOp<C: PhantomConstGet<CpuConfig>> =
     crate::instruction::RenamedMOp<PRegNum<C>, PRegNum<C>>;
 
+#[hdl]
+pub struct GlobalState {
+    pub flags_mode: FlagsMode,
+}
+
+impl SimValueDefault for GlobalState {
+    #[hdl]
+    fn sim_value_default(self) -> SimValue<Self> {
+        let Self { flags_mode: _ } = self;
+        #[hdl(sim)]
+        Self {
+            flags_mode: FlagsMode.PowerISA(
+                #[hdl(sim)]
+                PRegFlagsPowerISA {},
+            ),
+        }
+    }
+}
+
 /// Enqueues happen in program order, they are not re-ordered by out-of-order execution.
 /// the whole `MOpInstance` is sent again in [`UnitInputsReady`] so Units can just ignore all
 /// [`UnitEnqueue`] messages if they don't need to keep track of program order -- so, pure computation
@@ -196,6 +215,7 @@ pub struct UnitMOpCantCauseCancel<C: PhantomConstGet<CpuConfig>> {
 #[doc = simple_mermaid::mermaid!("rename_execute_retire/unit.mermaid")]
 #[hdl(no_static)]
 pub struct ExecuteToUnitInterface<C: PhantomConstGet<CpuConfig>> {
+    pub global_state: GlobalState,
     /// Enqueues happen in program order, they are not re-ordered by out-of-order execution.
     pub enqueue: ReadyValid<UnitEnqueue<C>>,
     /// if [`Self::unit_outputs_ready`] is `false`, then this is always [`HdlNone`]
@@ -228,6 +248,7 @@ impl<C: PhantomConstCpuConfig> SimValueDefault for RenameExecuteRetireDebugState
     #[hdl]
     fn sim_value_default(self) -> SimValue<Self> {
         let Self {
+            global_state,
             rename_delayed,
             rename_table,
             retire_rename_table,
@@ -241,6 +262,7 @@ impl<C: PhantomConstCpuConfig> SimValueDefault for RenameExecuteRetireDebugState
         let empty_string = SimOnlyValue::new(String::new());
         #[hdl(sim)]
         Self {
+            global_state: global_state.sim_value_default(),
             rename_delayed: zeroed(rename_delayed),
             rename_table: zeroed(rename_table),
             retire_rename_table: zeroed(retire_rename_table),
@@ -515,6 +537,7 @@ struct RenameDelayedEntry<C: PhantomConstGet<CpuConfig>> {
 
 #[hdl(no_static)]
 pub struct RenameExecuteRetireDebugState<C: PhantomConstGet<CpuConfig>> {
+    global_state: GlobalState,
     rename_delayed: ArrayVec<RenameDelayedEntry<C>, TwiceCpuConfigFetchWidth<C>>,
     rename_table: RenameTableDebugState<C>,
     retire_rename_table: RenameTableDebugState<C>,
@@ -531,6 +554,7 @@ pub struct RenameExecuteRetireDebugState<C: PhantomConstGet<CpuConfig>> {
 
 #[derive(Debug)]
 struct RenameExecuteRetireState<C: PhantomConstCpuConfig> {
+    global_state: SimValue<GlobalState>,
     rename_delayed: VecDeque<SimValue<RenameDelayedEntry<C>>>,
     rename_table: RenameTable<C>,
     retire_rename_table: RenameTable<C>,
@@ -546,6 +570,7 @@ struct RenameExecuteRetireState<C: PhantomConstCpuConfig> {
 impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
     fn new(config: C) -> Self {
         Self {
+            global_state: GlobalState.sim_value_default(),
             rename_delayed: VecDeque::with_capacity(TwiceCpuConfigFetchWidth[config]),
             rename_table: RenameTable::new(config),
             retire_rename_table: RenameTable::new(config),
@@ -632,6 +657,7 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
         state_for_debug: Expr<RenameExecuteRetireDebugState<C>>,
     ) {
         let Self {
+            global_state,
             rename_delayed,
             rename_table,
             retire_rename_table,
@@ -647,6 +673,7 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
             state_for_debug,
             #[hdl(sim)]
             RenameExecuteRetireDebugState::<_> {
+                global_state,
                 rename_delayed: state_for_debug
                     .ty()
                     .rename_delayed
@@ -1387,6 +1414,7 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
     #[hdl]
     fn finish_receive_cancel_from_post_decode(&mut self) {
         let Self {
+            global_state: _,
             rename_delayed,
             rename_table,
             retire_rename_table,
@@ -1686,6 +1714,7 @@ async fn rename_execute_retire_run(
         {
             #[hdl]
             let ExecuteToUnitInterface::<_> {
+                global_state,
                 enqueue,
                 inputs_ready,
                 is_no_longer_speculative,
@@ -1696,6 +1725,7 @@ async fn rename_execute_retire_run(
                 cancel_all,
                 config: _,
             } = to_unit;
+            sim.write(global_state, &state.global_state).await;
             sim.write(enqueue.data, state.get_unit_enqueue(unit_index))
                 .await;
             sim.write(inputs_ready, state.get_unit_inputs_ready(unit_index))
@@ -1732,6 +1762,7 @@ async fn rename_execute_retire_run(
         {
             #[hdl]
             let ExecuteToUnitInterface::<_> {
+                global_state: _,
                 enqueue,
                 inputs_ready,
                 is_no_longer_speculative,
@@ -1923,6 +1954,7 @@ pub fn rename_execute_retire(config: PhantomConst<CpuConfig>) {
                     for to_unit in ExecuteToUnitInterfaces::unit_fields(to_units) {
                         #[hdl]
                         let ExecuteToUnitInterface::<_> {
+                            global_state,
                             enqueue,
                             inputs_ready,
                             is_no_longer_speculative,
@@ -1933,6 +1965,8 @@ pub fn rename_execute_retire(config: PhantomConst<CpuConfig>) {
                             cancel_all,
                             config: _,
                         } = to_unit;
+                        sim.write(global_state, GlobalState.sim_value_default())
+                            .await;
                         sim.write(
                             enqueue.data,
                             #[hdl(sim)]

crates/cpu/src/unit.rs

@@ -2,14 +2,12 @@
 // See Notices.txt for copyright information
 
 use crate::{
-    config::{CpuConfig, PhantomConstCpuConfig},
+    config::CpuConfig,
     instruction::{
         AluBranchMOp, LoadStoreMOp, MOp, MOpDestReg, MOpInto, MOpRegNum, MOpTrait,
-        MOpVariantVisitOps, MOpVariantVisitor, MOpVisitVariants, PRegNum, RenamedMOp,
+        MOpVariantVisitOps, MOpVariantVisitor, MOpVisitVariants, RenamedMOp, mop_enum,
-        UnitOutRegNum, mop_enum,
     },
-    register::{FlagsMode, PRegValue},
+    rename_execute_retire::ExecuteToUnitInterface,
-    unit::unit_base::UnitToRegAlloc,
 };
 use fayalite::{
     bundle::{Bundle, BundleType},
@@ -20,7 +18,6 @@ use serde::{Deserialize, Serialize};
 use std::ops::ControlFlow;
 
 pub mod alu_branch;
-pub mod unit_base;
 
 macro_rules! all_units {
     (
@@ -342,92 +339,23 @@ all_units! {
     }
 }
 
-#[hdl]
-pub struct GlobalState {
-    pub flags_mode: FlagsMode,
-}
-
-#[hdl(cmp_eq)]
-pub struct UnitResultCompleted<ExtraOut> {
-    pub value: PRegValue,
-    pub extra_out: ExtraOut,
-}
-
-#[hdl(cmp_eq, no_static)]
-pub struct UnitOutputWrite<C: PhantomConstGet<CpuConfig>> {
-    pub which: UnitOutRegNum<C>,
-    pub value: PRegValue,
-}
-
-#[hdl(cmp_eq)]
-pub struct TrapData {
-    // TODO
-}
-
-#[hdl]
-pub enum UnitResult<ExtraOut> {
-    Completed(UnitResultCompleted<ExtraOut>),
-    Trap(TrapData),
-}
-
-impl<ExtraOut: Type> UnitResult<ExtraOut> {
-    pub fn extra_out_ty(self) -> ExtraOut {
-        self.Completed.extra_out
-    }
-}
-
-#[hdl(no_static)]
-pub struct UnitOutput<C: PhantomConstGet<CpuConfig>, ExtraOut> {
-    pub which: UnitOutRegNum<C>,
-    pub result: UnitResult<ExtraOut>,
-}
-
-impl<C: PhantomConstCpuConfig, ExtraOut: Type> UnitOutput<C, ExtraOut> {
-    pub fn extra_out_ty(self) -> ExtraOut {
-        self.result.extra_out_ty()
-    }
-}
-
-#[hdl(cmp_eq, no_static)]
-pub struct UnitCancelInput<C: PhantomConstGet<CpuConfig>> {
-    pub which: UnitOutRegNum<C>,
-}
-
 pub trait UnitTrait:
     'static + Send + Sync + std::fmt::Debug + fayalite::intern::SupportsPtrEqWithTypeId
 {
     type Type: BundleType;
-    type ExtraOut: Type;
-    type MOp: Type;
 
     fn ty(&self) -> Self::Type;
-    fn extra_out_ty(&self) -> Self::ExtraOut;
-    fn mop_ty(&self) -> Self::MOp;
-
     fn unit_kind(&self) -> UnitKind;
-
-    fn extract_mop(
-        &self,
-        mop: Expr<
-            RenamedMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, PRegNum<PhantomConst<CpuConfig>>>,
-        >,
-    ) -> Expr<HdlOption<Self::MOp>>;
-
     fn module(&self) -> Interned<Module<Self::Type>>;
-
+    fn cd(&self, this: Expr<Self::Type>) -> Option<Expr<ClockDomain>>;
-    fn unit_to_reg_alloc(
+    fn from_execute(
         &self,
         this: Expr<Self::Type>,
-    ) -> Expr<UnitToRegAlloc<PhantomConst<CpuConfig>, Self::MOp, Self::ExtraOut>>;
+    ) -> Expr<ExecuteToUnitInterface<PhantomConst<CpuConfig>>>;
-
-    fn cd(&self, this: Expr<Self::Type>) -> Expr<ClockDomain>;
-
-    fn global_state(&self, this: Expr<Self::Type>) -> Expr<GlobalState>;
-
     fn to_dyn(&self) -> DynUnit;
 }
 
-type DynUnitTrait = dyn UnitTrait<Type = Bundle, ExtraOut = CanonicalType, MOp = CanonicalType>;
+type DynUnitTrait = dyn UnitTrait<Type = Bundle>;
 
 impl fayalite::intern::InternedCompare for DynUnitTrait {
     type InternedCompareKey = fayalite::intern::PtrEqWithTypeId;
@@ -439,59 +367,34 @@ impl fayalite::intern::InternedCompare for DynUnitTrait {
 #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
 pub struct DynUnit {
     ty: Bundle,
-    extra_out_ty: CanonicalType,
-    mop_ty: CanonicalType,
     unit_kind: UnitKind,
     unit: Interned<DynUnitTrait>,
 }
 
 impl UnitTrait for DynUnit {
     type Type = Bundle;
-    type ExtraOut = CanonicalType;
-    type MOp = CanonicalType;
 
     fn ty(&self) -> Self::Type {
         self.ty
     }
 
-    fn extra_out_ty(&self) -> Self::ExtraOut {
-        self.extra_out_ty
-    }
-
-    fn mop_ty(&self) -> Self::MOp {
-        self.mop_ty
-    }
-
     fn unit_kind(&self) -> UnitKind {
         self.unit_kind
     }
 
-    fn extract_mop(
-        &self,
-        mop: Expr<
-            RenamedMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, PRegNum<PhantomConst<CpuConfig>>>,
-        >,
-    ) -> Expr<HdlOption<Self::MOp>> {
-        self.unit.extract_mop(mop)
-    }
-
     fn module(&self) -> Interned<Module<Self::Type>> {
         self.unit.module()
     }
 
-    fn unit_to_reg_alloc(
+    fn cd(&self, this: Expr<Self::Type>) -> Option<Expr<ClockDomain>> {
-        &self,
-        this: Expr<Self::Type>,
-    ) -> Expr<UnitToRegAlloc<PhantomConst<CpuConfig>, Self::MOp, Self::ExtraOut>> {
-        self.unit.unit_to_reg_alloc(this)
-    }
-
-    fn cd(&self, this: Expr<Self::Type>) -> Expr<ClockDomain> {
         self.unit.cd(this)
     }
 
-    fn global_state(&self, this: Expr<Self::Type>) -> Expr<GlobalState> {
+    fn from_execute(
-        self.unit.global_state(this)
+        &self,
+        this: Expr<Self::Type>,
+    ) -> Expr<ExecuteToUnitInterface<PhantomConst<CpuConfig>>> {
+        self.unit.from_execute(this)
     }
 
     fn to_dyn(&self) -> DynUnit {
@@ -504,61 +407,34 @@ pub struct DynUnitWrapper<T>(pub T);
 
 impl<T: UnitTrait + Clone + std::hash::Hash + Eq> UnitTrait for DynUnitWrapper<T> {
     type Type = Bundle;
-    type ExtraOut = CanonicalType;
-    type MOp = CanonicalType;
 
     fn ty(&self) -> Self::Type {
         Bundle::from_canonical(self.0.ty().canonical())
     }
 
-    fn extra_out_ty(&self) -> Self::ExtraOut {
-        self.0.extra_out_ty().canonical()
-    }
-
-    fn mop_ty(&self) -> Self::MOp {
-        self.0.mop_ty().canonical()
-    }
-
     fn unit_kind(&self) -> UnitKind {
         self.0.unit_kind()
     }
 
-    fn extract_mop(
-        &self,
-        mop: Expr<
-            RenamedMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, PRegNum<PhantomConst<CpuConfig>>>,
-        >,
-    ) -> Expr<HdlOption<Self::MOp>> {
-        Expr::from_enum(Expr::as_enum(self.0.extract_mop(mop)))
-    }
-
     fn module(&self) -> Interned<Module<Self::Type>> {
         self.0.module().canonical().intern_sized()
     }
 
-    fn unit_to_reg_alloc(
+    fn cd(&self, this: Expr<Self::Type>) -> Option<Expr<ClockDomain>> {
-        &self,
-        this: Expr<Self::Type>,
-    ) -> Expr<UnitToRegAlloc<PhantomConst<CpuConfig>, Self::MOp, Self::ExtraOut>> {
-        Expr::from_bundle(Expr::as_bundle(
-            self.0.unit_to_reg_alloc(Expr::from_bundle(this)),
-        ))
-    }
-
-    fn cd(&self, this: Expr<Self::Type>) -> Expr<ClockDomain> {
         self.0.cd(Expr::from_bundle(this))
     }
 
-    fn global_state(&self, this: Expr<Self::Type>) -> Expr<GlobalState> {
+    fn from_execute(
-        self.0.global_state(Expr::from_bundle(this))
+        &self,
+        this: Expr<Self::Type>,
+    ) -> Expr<ExecuteToUnitInterface<PhantomConst<CpuConfig>>> {
+        self.0.from_execute(Expr::from_bundle(this))
     }
 
     fn to_dyn(&self) -> DynUnit {
         let unit = self.intern();
         DynUnit {
             ty: unit.ty(),
-            extra_out_ty: unit.extra_out_ty(),
-            mop_ty: unit.mop_ty(),
             unit_kind: unit.unit_kind(),
             unit: Interned::cast_unchecked(unit, |v: &Self| -> &DynUnitTrait { v }),
         }

crates/cpu/src/unit/alu_branch.rs

@@ -2,40 +2,35 @@
 // See Notices.txt for copyright information
 
 use crate::{
-    config::CpuConfig,
+    config::{CpuConfig, PhantomConstCpuConfig},
     instruction::{
-        AddSubMOp, AluBranchMOp, AluCommonMOp, BranchMOp, COMMON_MOP_SRC_LEN, CommonMOpDefaultImm,
+        AddSubMOp, AluBranchMOp, AluCommonMOp, BranchMOp, COMMON_MOP_SRC_LEN, CommonMOp,
-        CompareMOp, LogicalFlagsMOp, LogicalMOp, MOpTrait, OutputIntegerMode, PRegNum,
+        CommonMOpDefaultImm, CompareMOp, ConditionMode, LogicalFlagsMOp, LogicalMOp,
-        ReadSpecialMOp, RenamedMOp, ShiftRotateMOp, UnitOutRegNum,
+        OutputIntegerMode, PRegNum, ReadSpecialMOp, ShiftRotateMOp,
     },
+    next_pc::CallStackOp,
     register::{
-        FlagsMode, PRegFlagsPowerISA, PRegFlagsPowerISAView, PRegFlagsViewTrait, PRegFlagsX86,
+        FlagsMode, PRegFlags, PRegFlagsPowerISA, PRegFlagsPowerISAView, PRegFlagsViewTrait,
-        PRegFlagsX86View, PRegValue, ViewUnused,
+        PRegFlagsX86, PRegFlagsX86View, PRegValue, ViewUnused,
     },
-    unit::{
+    rename_execute_retire::{
-        DynUnit, DynUnitWrapper, GlobalState, UnitKind, UnitMOp, UnitOutput, UnitResult,
+        ExecuteToUnitInterface, GlobalState, NextPcPredictorOp, RenamedMOp, UnitCausedCancel,
-        UnitResultCompleted, UnitTrait,
+        UnitFinishCauseCancel, UnitInputsReady, UnitOutputReady,
-        unit_base::{ExecuteEnd, ExecuteStart, UnitToRegAlloc, unit_base},
     },
+    unit::{DynUnit, DynUnitWrapper, UnitKind, UnitTrait},
 };
-use fayalite::{
+use fayalite::{intern::Interned, module::wire_with_loc, prelude::*};
-    intern::Interned, module::wire_with_loc, prelude::*, util::ready_valid::ReadyValid,
-};
 use std::{collections::HashMap, ops::RangeTo};
 
 #[hdl]
-fn add_sub<SrcCount: KnownSize>(
+fn add_sub<C: PhantomConstCpuConfig, SrcCount: KnownSize>(
-    mop: Expr<
+    global_state: Expr<GlobalState>,
-        AddSubMOp<
-            UnitOutRegNum<PhantomConst<CpuConfig>>,
-            PRegNum<PhantomConst<CpuConfig>>,
-            SrcCount,
-        >,
-    >,
     pc: Expr<UInt<64>>,
-    flags_mode: Expr<FlagsMode>,
+    mop: Expr<AddSubMOp<PRegNum<C>, PRegNum<C>, SrcCount>>,
-    src_values: Expr<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>,
+    src_values: Expr<Array<TraceAsString<PRegValue>, { COMMON_MOP_SRC_LEN }>>,
-) -> Expr<UnitResultCompleted<()>> {
+) -> Expr<TraceAsString<PRegValue>> {
+    #[hdl]
+    let GlobalState { flags_mode } = global_state;
     #[hdl]
     let AddSubMOp::<_, _, _> {
         alu_common,
@@ -238,373 +233,450 @@ fn add_sub<SrcCount: KnownSize>(
             );
         }
     }
-    #[hdl]
+    let retval = #[hdl]
-    UnitResultCompleted::<_> {
+    PRegValue { int_fp, flags };
-        value: #[hdl]
+    retval.to_trace_as_string()
-        PRegValue { int_fp, flags },
-        extra_out: (),
-    }
 }
 
 #[hdl]
-fn logical_flags(
+fn logical_flags<C: PhantomConstCpuConfig>(
-    mop: Expr<
+    global_state: Expr<GlobalState>,
-        LogicalFlagsMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, PRegNum<PhantomConst<CpuConfig>>>,
-    >,
-    flags_mode: Expr<FlagsMode>,
-    src_values: Expr<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>,
-) -> Expr<UnitResultCompleted<()>> {
-    // TODO: finish
-    #[hdl]
-    UnitResultCompleted::<_> {
-        value: PRegValue::zeroed(),
-        extra_out: (),
-    }
-}
-
-#[hdl]
-fn logical(
-    mop: Expr<
-        LogicalMOp<
-            UnitOutRegNum<PhantomConst<CpuConfig>>,
-            PRegNum<PhantomConst<CpuConfig>>,
-            ConstUsize<2>,
-        >,
-    >,
-    flags_mode: Expr<FlagsMode>,
-    src_values: Expr<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>,
-) -> Expr<UnitResultCompleted<()>> {
-    // TODO: finish
-    #[hdl]
-    UnitResultCompleted::<_> {
-        value: PRegValue::zeroed(),
-        extra_out: (),
-    }
-}
-
-#[hdl]
-fn logical_i(
-    mop: Expr<
-        LogicalMOp<
-            UnitOutRegNum<PhantomConst<CpuConfig>>,
-            PRegNum<PhantomConst<CpuConfig>>,
-            ConstUsize<1>,
-        >,
-    >,
-    flags_mode: Expr<FlagsMode>,
-    src_values: Expr<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>,
-) -> Expr<UnitResultCompleted<()>> {
-    // TODO: finish
-    #[hdl]
-    UnitResultCompleted::<_> {
-        value: PRegValue::zeroed(),
-        extra_out: (),
-    }
-}
-
-#[hdl]
-fn shift_rotate(
-    mop: Expr<
-        ShiftRotateMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, PRegNum<PhantomConst<CpuConfig>>>,
-    >,
-    flags_mode: Expr<FlagsMode>,
-    src_values: Expr<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>,
-) -> Expr<UnitResultCompleted<()>> {
-    // TODO: finish
-    #[hdl]
-    UnitResultCompleted::<_> {
-        value: PRegValue::zeroed(),
-        extra_out: (),
-    }
-}
-
-#[hdl]
-fn compare<SrcCount: KnownSize>(
-    mop: Expr<
-        CompareMOp<
-            UnitOutRegNum<PhantomConst<CpuConfig>>,
-            PRegNum<PhantomConst<CpuConfig>>,
-            SrcCount,
-        >,
-    >,
-    flags_mode: Expr<FlagsMode>,
-    src_values: Expr<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>,
-) -> Expr<UnitResultCompleted<()>> {
-    // TODO: finish
-    #[hdl]
-    UnitResultCompleted::<_> {
-        value: PRegValue::zeroed(),
-        extra_out: (),
-    }
-}
-
-#[hdl]
-fn branch<SrcCount: KnownSize>(
-    mop: Expr<
-        BranchMOp<
-            UnitOutRegNum<PhantomConst<CpuConfig>>,
-            PRegNum<PhantomConst<CpuConfig>>,
-            SrcCount,
-        >,
-    >,
     pc: Expr<UInt<64>>,
-    flags_mode: Expr<FlagsMode>,
+    mop: Expr<LogicalFlagsMOp<PRegNum<C>, PRegNum<C>>>,
-    src_values: Expr<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>,
+    src_values: Expr<Array<TraceAsString<PRegValue>, { COMMON_MOP_SRC_LEN }>>,
-) -> Expr<UnitResultCompleted<()>> {
+) -> Expr<TraceAsString<PRegValue>> {
-    // TODO: finish
     #[hdl]
-    UnitResultCompleted::<_> {
+    let GlobalState { flags_mode } = global_state;
-        value: PRegValue::zeroed(),
+    // TODO: finish
-        extra_out: (),
+    PRegValue::zeroed().to_trace_as_string()
-    }
 }
 
 #[hdl]
-fn read_special(
+fn logical<C: PhantomConstCpuConfig>(
-    mop: Expr<
+    global_state: Expr<GlobalState>,
-        ReadSpecialMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, PRegNum<PhantomConst<CpuConfig>>>,
-    >,
     pc: Expr<UInt<64>>,
-    flags_mode: Expr<FlagsMode>,
+    mop: Expr<LogicalMOp<PRegNum<C>, PRegNum<C>, ConstUsize<2>>>,
-    src_values: Expr<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>,
+    src_values: Expr<Array<TraceAsString<PRegValue>, { COMMON_MOP_SRC_LEN }>>,
-) -> Expr<UnitResultCompleted<()>> {
+) -> Expr<TraceAsString<PRegValue>> {
-    // TODO: finish
     #[hdl]
-    UnitResultCompleted::<_> {
+    let GlobalState { flags_mode } = global_state;
-        value: PRegValue::zeroed(),
+    // TODO: finish
-        extra_out: (),
+    PRegValue::zeroed().to_trace_as_string()
+}
+
+#[hdl]
+fn logical_i<C: PhantomConstCpuConfig>(
+    global_state: Expr<GlobalState>,
+    pc: Expr<UInt<64>>,
+    mop: Expr<LogicalMOp<PRegNum<C>, PRegNum<C>, ConstUsize<1>>>,
+    src_values: Expr<Array<TraceAsString<PRegValue>, { COMMON_MOP_SRC_LEN }>>,
+) -> Expr<TraceAsString<PRegValue>> {
+    #[hdl]
+    let GlobalState { flags_mode } = global_state;
+    // TODO: finish
+    PRegValue::zeroed().to_trace_as_string()
+}
+
+#[hdl]
+fn shift_rotate<C: PhantomConstCpuConfig>(
+    global_state: Expr<GlobalState>,
+    pc: Expr<UInt<64>>,
+    mop: Expr<ShiftRotateMOp<PRegNum<C>, PRegNum<C>>>,
+    src_values: Expr<Array<TraceAsString<PRegValue>, { COMMON_MOP_SRC_LEN }>>,
+) -> Expr<TraceAsString<PRegValue>> {
+    #[hdl]
+    let GlobalState { flags_mode } = global_state;
+    // TODO: finish
+    PRegValue::zeroed().to_trace_as_string()
+}
+
+#[hdl]
+fn compare<C: PhantomConstCpuConfig, SrcCount: KnownSize>(
+    global_state: Expr<GlobalState>,
+    pc: Expr<UInt<64>>,
+    mop: Expr<CompareMOp<PRegNum<C>, PRegNum<C>, SrcCount>>,
+    src_values: Expr<Array<TraceAsString<PRegValue>, { COMMON_MOP_SRC_LEN }>>,
+) -> Expr<TraceAsString<PRegValue>> {
+    #[hdl]
+    let GlobalState { flags_mode } = global_state;
+    // TODO: finish
+    PRegValue::zeroed().to_trace_as_string()
+}
+
+#[hdl]
+fn branch<C: PhantomConstCpuConfig, SrcCount: KnownSize>(
+    global_state: Expr<GlobalState>,
+    pc: Expr<UInt<64>>,
+    fallthrough_pc: Expr<UInt<64>>,
+    predicted_next_pc: Expr<UInt<64>>,
+    mop: Expr<BranchMOp<PRegNum<C>, PRegNum<C>, SrcCount>>,
+    src_values: Expr<Array<TraceAsString<PRegValue>, { COMMON_MOP_SRC_LEN }>>,
+    config: C,
+) -> (
+    Expr<TraceAsString<PRegValue>>,
+    Expr<NextPcPredictorOp<C>>,
+    Expr<HdlOption<UnitCausedCancel<C>>>,
+) {
+    #[hdl]
+    let GlobalState { flags_mode } = global_state;
+    #[hdl]
+    let BranchMOp::<_, _, _> {
+        common,
+        invert_src0_cond,
+        src0_cond_mode,
+        invert_src2_eq_zero,
+        pc_relative,
+        is_call,
+        is_ret,
+    } = mop;
+    #[hdl]
+    let CommonMOp::<_, _, _, _, _> {
+        prefix_pad: _,
+        dest: _,
+        src,
+        imm,
+    } = common;
+    let [src0, src1, src2] = *src_values;
+    #[hdl]
+    let has_src0 = wire();
+    if let Some(src0) = src.as_ref().get(0) {
+        connect(has_src0, src0.cmp_ne(src0.ty().const_zero()));
+    } else {
+        connect(has_src0, false);
     }
+    #[hdl]
+    let has_src2 = wire();
+    if let Some(src2) = src.as_ref().get(2) {
+        connect(has_src2, src2.cmp_ne(src2.ty().const_zero()));
+    } else {
+        connect(has_src2, false);
+    }
+    #[hdl]
+    let src2_cond = wire();
+    #[hdl]
+    if has_src2 {
+        #[hdl]
+        if invert_src2_eq_zero {
+            connect(src2_cond, src2.int_fp.cmp_ne(0u64));
+        } else {
+            connect(src2_cond, src2.int_fp.cmp_eq(0u64));
+        }
+    } else {
+        connect(src2_cond, true);
+    }
+    #[hdl]
+    let src0_cond = wire();
+    #[hdl]
+    match flags_mode {
+        FlagsMode::PowerISA(_) => {
+            let src0_flags = PRegFlags::view::<PRegFlagsPowerISA>(src0.flags);
+            #[hdl]
+            match src0_cond_mode {
+                ConditionMode::Eq => connect(src0_cond, src0_flags.cr_eq),
+                ConditionMode::ULt => connect(src0_cond, src0_flags.cr_lt),
+                ConditionMode::UGt => connect(src0_cond, src0_flags.cr_gt),
+                ConditionMode::SLt => connect(src0_cond, src0_flags.cr_lt),
+                ConditionMode::SGt => connect(src0_cond, src0_flags.cr_gt),
+                ConditionMode::Sign => connect(src0_cond, false),
+                ConditionMode::Overflow => connect(src0_cond, src0_flags.so),
+                ConditionMode::Parity => connect(src0_cond, false),
+            };
+        }
+        FlagsMode::X86(_) => {
+            let src0_flags = PRegFlags::view::<PRegFlagsX86>(src0.flags);
+            #[hdl]
+            match src0_cond_mode {
+                ConditionMode::Eq => connect(src0_cond, src0_flags.zf),
+                ConditionMode::ULt => connect(src0_cond, src0_flags.cf),
+                ConditionMode::UGt => connect(src0_cond, !src0_flags.zf & !src0_flags.cf),
+                ConditionMode::SLt => connect(src0_cond, src0_flags.sf.cmp_ne(src0_flags.of)),
+                ConditionMode::SGt => connect(
+                    src0_cond,
+                    !src0_flags.zf & src0_flags.sf.cmp_eq(src0_flags.of),
+                ),
+                ConditionMode::Sign => connect(src0_cond, src0_flags.sf),
+                ConditionMode::Overflow => connect(src0_cond, src0_flags.of),
+                ConditionMode::Parity => connect(src0_cond, src0_flags.pf),
+            };
+        }
+    }
+    let src0_cond = src0_cond ^ invert_src0_cond;
+    #[hdl]
+    let pc_or_zero = wire();
+    #[hdl]
+    if pc_relative {
+        connect(pc_or_zero, pc);
+    } else {
+        connect(pc_or_zero, 0u64);
+    }
+    #[hdl]
+    let target_pc: UInt<64> = wire();
+    connect_any(
+        target_pc,
+        src1.int_fp
+            + CommonMOpDefaultImm::as_sint_dyn(imm).cast_to_static::<UInt<64>>()
+            + pc_or_zero,
+    );
+    #[hdl]
+    let cond_br_taken = wire();
+    connect(cond_br_taken, src0_cond & src2_cond);
+    #[hdl]
+    let is_cond = wire();
+    connect(is_cond, !cond_br_taken | has_src0 | has_src2);
+    #[hdl]
+    let next_pc = wire();
+    #[hdl]
+    if cond_br_taken {
+        connect(next_pc, target_pc);
+    } else {
+        connect(next_pc, fallthrough_pc);
+    };
+    #[hdl]
+    let cancel = wire(HdlOption[UnitCausedCancel[config]]);
+    #[hdl]
+    if next_pc.cmp_ne(predicted_next_pc) {
+        connect(
+            cancel,
+            HdlSome(
+                #[hdl]
+                UnitCausedCancel::<C> {
+                    start_at_pc: next_pc,
+                    cancel_after_retire: true,
+                    config,
+                },
+            ),
+        );
+    } else {
+        connect(cancel, cancel.ty().HdlNone());
+    };
+    let fallthrough_pc_value = #[hdl]
+    PRegValue {
+        int_fp: fallthrough_pc,
+        flags: PRegFlags::zeroed_sim(),
+    };
+    #[hdl]
+    let call_stack_op = wire();
+    #[hdl]
+    if is_ret {
+        connect(call_stack_op, CallStackOp.Pop());
+    } else if is_call {
+        connect(call_stack_op, CallStackOp.Push(fallthrough_pc));
+    } else {
+        connect(call_stack_op, CallStackOp.None());
+    }
+    #[hdl]
+    let cond_br_taken_opt = wire();
+    #[hdl]
+    if is_cond {
+        connect(cond_br_taken_opt, HdlSome(cond_br_taken));
+    } else {
+        connect(cond_br_taken_opt, HdlNone());
+    }
+    (
+        fallthrough_pc_value.into_trace_as_string(),
+        #[hdl]
+        NextPcPredictorOp::<_> {
+            call_stack_op,
+            cond_br_taken: cond_br_taken_opt,
+            config,
+        },
+        cancel,
+    )
+}
+
+#[hdl]
+fn read_special<C: PhantomConstCpuConfig>(
+    global_state: Expr<GlobalState>,
+    pc: Expr<UInt<64>>,
+    mop: Expr<ReadSpecialMOp<PRegNum<C>, PRegNum<C>>>,
+    src_values: Expr<Array<TraceAsString<PRegValue>, { COMMON_MOP_SRC_LEN }>>,
+) -> Expr<TraceAsString<PRegValue>> {
+    #[hdl]
+    let GlobalState { flags_mode } = global_state;
+    // TODO: finish
+    PRegValue::zeroed().to_trace_as_string()
 }
 
 #[hdl_module]
 pub fn alu_branch(config: PhantomConst<CpuConfig>, unit_index: usize) {
     #[hdl]
-    let cd: ClockDomain = m.input();
+    let from_execute: ExecuteToUnitInterface<PhantomConst<CpuConfig>> =
-    #[hdl]
+        m.input(ExecuteToUnitInterface[config]);
-    let unit_to_reg_alloc: UnitToRegAlloc<
+
-        PhantomConst<CpuConfig>,
+    assert_eq!(config.get().units[unit_index].kind, UnitKind::AluBranch);
-        AluBranchMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, PRegNum<PhantomConst<CpuConfig>>>,
-        (),
-    > = m.output(UnitToRegAlloc[config][AluBranchMOp[UnitOutRegNum[config]][PRegNum[config]]][()]);
-    #[hdl]
-    let global_state: GlobalState = m.input();
 
     #[hdl]
-    let unit_base = instance(unit_base(
+    let ExecuteToUnitInterface::<_> {
-        config,
+        global_state,
-        unit_index,
+        enqueue,
-        unit_to_reg_alloc.ty().input.data.HdlSome.mop,
+        inputs_ready,
-        (),
+        is_no_longer_speculative: _, // we don't care about being speculative for these instructions
-    ));
+        cant_cause_cancel,
-    connect(unit_to_reg_alloc, unit_base.unit_to_reg_alloc);
+        output_ready,
-    connect(unit_base.cd, cd);
+        finish_cause_cancel,
-    connect(unit_base.execute_start.ready, true);
+        unit_outputs_ready: _,
-    connect(unit_base.execute_end, unit_base.execute_end.ty().HdlNone());
+        cancel_all,
+        config: _,
+    } = from_execute;
+    // we ignore enqueues since we don't need to track order for these instructions
+    connect(enqueue.ready, true);
     #[hdl]
-    if let HdlSome(execute_start) = ReadyValid::firing_data(unit_base.execute_start) {
+    if let HdlSome(inputs_ready) = inputs_ready {
         #[hdl]
-        let ExecuteStart::<_, _> {
+        let UnitInputsReady::<_> {
-            mop,
+            mop: mop_instance,
-            pc,
             src_values,
             config: _,
-        } = execute_start;
+        } = inputs_ready;
+        #[hdl]
+        let fallthrough_pc: UInt<64> = wire();
+        connect_any(fallthrough_pc, mop_instance.pc + mop_instance.size_in_bytes);
+
+        #[hdl]
+        match *mop_instance.mop {
+            RenamedMOp::<_>::AluBranch(mop) => {
+                #[hdl]
+                let dest_value = wire();
+
+                #[hdl]
+                let predictor_op = wire(NextPcPredictorOp[config]);
+                connect(
+                    predictor_op,
+                    #[hdl]
+                    NextPcPredictorOp::<_> {
+                        call_stack_op: CallStackOp.None(),
+                        cond_br_taken: HdlNone(),
+                        config,
+                    },
+                );
+
+                #[hdl]
+                let caused_cancel = wire(HdlOption[UnitCausedCancel[config]]);
+                connect(caused_cancel, caused_cancel.ty().HdlNone());
+
                 #[hdl]
                 match mop {
-            AluBranchMOp::<_, _>::AddSub(mop) => connect(
+                    AluBranchMOp::<_, _>::AddSub(mop) => {
-                unit_base.execute_end,
+                        connect(
-                HdlSome(
+                            dest_value,
-                    #[hdl]
+                            add_sub(global_state, mop_instance.pc, mop, src_values),
-                    ExecuteEnd::<_, _> {
+                        );
-                        unit_output: #[hdl]
+                    }
-                        UnitOutput::<_, _> {
+                    AluBranchMOp::<_, _>::AddSubI(mop) => {
-                            which: MOpTrait::dest_reg(mop),
+                        connect(
-                            result: UnitResult[()].Completed(add_sub(
+                            dest_value,
+                            add_sub(global_state, mop_instance.pc, mop, src_values),
+                        );
+                    }
+                    AluBranchMOp::<_, _>::LogicalFlags(mop) => {
+                        connect(
+                            dest_value,
+                            logical_flags(global_state, mop_instance.pc, mop, src_values),
+                        );
+                    }
+                    AluBranchMOp::<_, _>::Logical(mop) => {
+                        connect(
+                            dest_value,
+                            logical(global_state, mop_instance.pc, mop, src_values),
+                        );
+                    }
+                    AluBranchMOp::<_, _>::LogicalI(mop) => {
+                        connect(
+                            dest_value,
+                            logical_i(global_state, mop_instance.pc, mop, src_values),
+                        );
+                    }
+                    AluBranchMOp::<_, _>::ShiftRotate(mop) => {
+                        connect(
+                            dest_value,
+                            shift_rotate(global_state, mop_instance.pc, mop, src_values),
+                        );
+                    }
+                    AluBranchMOp::<_, _>::Compare(mop) => {
+                        connect(
+                            dest_value,
+                            compare(global_state, mop_instance.pc, mop, src_values),
+                        );
+                    }
+                    AluBranchMOp::<_, _>::CompareI(mop) => {
+                        connect(
+                            dest_value,
+                            compare(global_state, mop_instance.pc, mop, src_values),
+                        );
+                    }
+                    AluBranchMOp::<_, _>::Branch(mop) => {
+                        let (dest_value_, predictor_op_, caused_cancel_) = branch(
+                            global_state,
+                            mop_instance.pc,
+                            fallthrough_pc,
+                            mop_instance.predicted_next_pc,
                             mop,
-                                pc,
-                                global_state.flags_mode,
                             src_values,
-                            )),
+                            config,
-                        },
+                        );
-                    },
+                        connect(dest_value, dest_value_);
-                ),
+                        connect(predictor_op, predictor_op_);
-            ),
+                        connect(caused_cancel, caused_cancel_);
-            AluBranchMOp::<_, _>::AddSubI(mop) => connect(
+                    }
-                unit_base.execute_end,
+                    AluBranchMOp::<_, _>::BranchI(mop) => {
-                HdlSome(
+                        let (dest_value_, predictor_op_, caused_cancel_) = branch(
-                    #[hdl]
+                            global_state,
-                    ExecuteEnd::<_, _> {
+                            mop_instance.pc,
-                        unit_output: #[hdl]
+                            fallthrough_pc,
-                        UnitOutput::<_, _> {
+                            mop_instance.predicted_next_pc,
-                            which: MOpTrait::dest_reg(mop),
-                            result: UnitResult[()].Completed(add_sub(
                             mop,
-                                pc,
-                                global_state.flags_mode,
                             src_values,
-                            )),
+                            config,
-                        },
+                        );
-                    },
+                        connect(dest_value, dest_value_);
-                ),
+                        connect(predictor_op, predictor_op_);
-            ),
+                        connect(caused_cancel, caused_cancel_);
-            AluBranchMOp::<_, _>::LogicalFlags(mop) => connect(
+                    }
-                unit_base.execute_end,
+                    AluBranchMOp::<_, _>::ReadSpecial(mop) => {
-                HdlSome(
+                        connect(
-                    #[hdl]
+                            dest_value,
-                    ExecuteEnd::<_, _> {
+                            read_special(global_state, mop_instance.pc, mop, src_values),
-                        unit_output: #[hdl]
+                        );
-                        UnitOutput::<_, _> {
-                            which: MOpTrait::dest_reg(mop),
-                            result: UnitResult[()].Completed(logical_flags(
-                                mop,
-                                global_state.flags_mode,
-                                src_values,
-                            )),
-                        },
-                    },
-                ),
-            ),
-            AluBranchMOp::<_, _>::Logical(mop) => connect(
-                unit_base.execute_end,
-                HdlSome(
-                    #[hdl]
-                    ExecuteEnd::<_, _> {
-                        unit_output: #[hdl]
-                        UnitOutput::<_, _> {
-                            which: MOpTrait::dest_reg(mop),
-                            result: UnitResult[()].Completed(logical(
-                                mop,
-                                global_state.flags_mode,
-                                src_values,
-                            )),
-                        },
-                    },
-                ),
-            ),
-            AluBranchMOp::<_, _>::LogicalI(mop) => connect(
-                unit_base.execute_end,
-                HdlSome(
-                    #[hdl]
-                    ExecuteEnd::<_, _> {
-                        unit_output: #[hdl]
-                        UnitOutput::<_, _> {
-                            which: MOpTrait::dest_reg(mop),
-                            result: UnitResult[()].Completed(logical_i(
-                                mop,
-                                global_state.flags_mode,
-                                src_values,
-                            )),
-                        },
-                    },
-                ),
-            ),
-            AluBranchMOp::<_, _>::ShiftRotate(mop) => connect(
-                unit_base.execute_end,
-                HdlSome(
-                    #[hdl]
-                    ExecuteEnd::<_, _> {
-                        unit_output: #[hdl]
-                        UnitOutput::<_, _> {
-                            which: MOpTrait::dest_reg(mop),
-                            result: UnitResult[()].Completed(shift_rotate(
-                                mop,
-                                global_state.flags_mode,
-                                src_values,
-                            )),
-                        },
-                    },
-                ),
-            ),
-            AluBranchMOp::<_, _>::Compare(mop) => connect(
-                unit_base.execute_end,
-                HdlSome(
-                    #[hdl]
-                    ExecuteEnd::<_, _> {
-                        unit_output: #[hdl]
-                        UnitOutput::<_, _> {
-                            which: MOpTrait::dest_reg(mop),
-                            result: UnitResult[()].Completed(compare(
-                                mop,
-                                global_state.flags_mode,
-                                src_values,
-                            )),
-                        },
-                    },
-                ),
-            ),
-            AluBranchMOp::<_, _>::CompareI(mop) => connect(
-                unit_base.execute_end,
-                HdlSome(
-                    #[hdl]
-                    ExecuteEnd::<_, _> {
-                        unit_output: #[hdl]
-                        UnitOutput::<_, _> {
-                            which: MOpTrait::dest_reg(mop),
-                            result: UnitResult[()].Completed(compare(
-                                mop,
-                                global_state.flags_mode,
-                                src_values,
-                            )),
-                        },
-                    },
-                ),
-            ),
-            AluBranchMOp::<_, _>::Branch(mop) => connect(
-                unit_base.execute_end,
-                HdlSome(
-                    #[hdl]
-                    ExecuteEnd::<_, _> {
-                        unit_output: #[hdl]
-                        UnitOutput::<_, _> {
-                            which: MOpTrait::dest_reg(mop),
-                            result: UnitResult[()].Completed(branch(
-                                mop,
-                                pc,
-                                global_state.flags_mode,
-                                src_values,
-                            )),
-                        },
-                    },
-                ),
-            ),
-            AluBranchMOp::<_, _>::BranchI(mop) => connect(
-                unit_base.execute_end,
-                HdlSome(
-                    #[hdl]
-                    ExecuteEnd::<_, _> {
-                        unit_output: #[hdl]
-                        UnitOutput::<_, _> {
-                            which: MOpTrait::dest_reg(mop),
-                            result: UnitResult[()].Completed(branch(
-                                mop,
-                                pc,
-                                global_state.flags_mode,
-                                src_values,
-                            )),
-                        },
-                    },
-                ),
-            ),
-            AluBranchMOp::<_, _>::ReadSpecial(mop) => connect(
-                unit_base.execute_end,
-                HdlSome(
-                    #[hdl]
-                    ExecuteEnd::<_, _> {
-                        unit_output: #[hdl]
-                        UnitOutput::<_, _> {
-                            which: MOpTrait::dest_reg(mop),
-                            result: UnitResult[()].Completed(read_special(
-                                mop,
-                                pc,
-                                global_state.flags_mode,
-                                src_values,
-                            )),
-                        },
-                    },
-                ),
-            ),
                     }
                 }
+                connect(
+                    output_ready,
+                    HdlSome(
+                        #[hdl]
+                        UnitOutputReady::<_> {
+                            id: mop_instance.id,
+                            dest_value,
+                            predictor_op,
+                        },
+                    ),
+                );
+                connect(
+                    finish_cause_cancel,
+                    HdlSome(
+                        #[hdl]
+                        UnitFinishCauseCancel::<_> {
+                            id: mop_instance.id,
+                            caused_cancel,
+                            config,
+                        },
+                    ),
+                );
+            }
+            _ => {
+                // error
+                connect(output_ready, output_ready.ty().HdlNone());
+                connect(finish_cause_cancel, finish_cause_cancel.ty().HdlNone());
+            }
+        }
+    } else {
+        connect(output_ready, output_ready.ty().HdlNone());
+        connect(finish_cause_cancel, finish_cause_cancel.ty().HdlNone());
+    }
+
+    // all outputs are immediately ready, so reporting that instructions can't cause cancels is superfluous
+    connect(cant_cause_cancel, cant_cause_cancel.ty().HdlNone());
+    // this unit is purely combinational so canceling does nothing
+    connect(cancel_all.ready, true);
 }
 
 #[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)]
@@ -624,52 +696,28 @@ impl AluBranch {
 
 impl UnitTrait for AluBranch {
     type Type = alu_branch;
-    type ExtraOut = ();
-    type MOp =
-        AluBranchMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, PRegNum<PhantomConst<CpuConfig>>>;
 
     fn ty(&self) -> Self::Type {
         self.module.io_ty()
     }
 
-    fn extra_out_ty(&self) -> Self::ExtraOut {
-        ()
-    }
-
-    fn mop_ty(&self) -> Self::MOp {
-        self.module.io_ty().unit_to_reg_alloc.mop_ty()
-    }
-
     fn unit_kind(&self) -> UnitKind {
         UnitKind::AluBranch
     }
 
-    fn extract_mop(
-        &self,
-        mop: Expr<
-            RenamedMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, PRegNum<PhantomConst<CpuConfig>>>,
-        >,
-    ) -> Expr<HdlOption<Self::MOp>> {
-        UnitMOp::alu_branch_mop(mop)
-    }
-
     fn module(&self) -> Interned<Module<Self::Type>> {
         self.module
     }
 
-    fn unit_to_reg_alloc(
+    fn cd(&self, this: Expr<Self::Type>) -> Option<Expr<ClockDomain>> {
+        None
+    }
+
+    fn from_execute(
         &self,
         this: Expr<Self::Type>,
-    ) -> Expr<UnitToRegAlloc<PhantomConst<CpuConfig>, Self::MOp, Self::ExtraOut>> {
+    ) -> Expr<ExecuteToUnitInterface<PhantomConst<CpuConfig>>> {
-        this.unit_to_reg_alloc
+        this.from_execute
-    }
-
-    fn cd(&self, this: Expr<Self::Type>) -> Expr<ClockDomain> {
-        this.cd
-    }
-
-    fn global_state(&self, this: Expr<Self::Type>) -> Expr<GlobalState> {
-        this.global_state
     }
 
     fn to_dyn(&self) -> DynUnit {

crates/cpu/src/unit/unit_base.rs

@@ -1,611 +0,0 @@
-// SPDX-License-Identifier: LGPL-3.0-or-later
-// See Notices.txt for copyright information
-
-use crate::{
-    config::{CpuConfig, CpuConfigUnitCount, PhantomConstCpuConfig},
-    instruction::{COMMON_MOP_SRC_LEN, MOpTrait, PRegNum, UnitNum, UnitOutRegNum},
-    register::PRegValue,
-    unit::{UnitCancelInput, UnitOutput, UnitOutputWrite},
-    util::tree_reduce::tree_reduce,
-};
-use fayalite::{
-    memory::splat_mask,
-    module::{memory_with_loc, wire_with_loc},
-    prelude::*,
-    ty::StaticType,
-    util::ready_valid::ReadyValid,
-};
-
-#[hdl(no_static)]
-pub struct UnitForwardingInfo<C: PhantomConstGet<CpuConfig>> {
-    pub unit_output_writes: ArrayType<HdlOption<UnitOutputWrite<C>>, CpuConfigUnitCount<C>>,
-    pub unit_reg_frees: ArrayType<HdlOption<UnitOutRegNum<C>>, CpuConfigUnitCount<C>>,
-}
-
-#[hdl]
-pub struct UnitInput<MOp: Type> {
-    pub mop: MOp,
-    pub pc: UInt<64>,
-}
-
-#[hdl(no_static)]
-pub struct UnitToRegAlloc<C: PhantomConstGet<CpuConfig>, MOp: Type, ExtraOut: Type> {
-    #[hdl(flip)]
-    pub unit_forwarding_info: UnitForwardingInfo<C>,
-    #[hdl(flip)]
-    pub input: ReadyValid<UnitInput<MOp>>,
-    #[hdl(flip)]
-    pub cancel_input: HdlOption<UnitCancelInput<C>>,
-    pub output: HdlOption<UnitOutput<C, ExtraOut>>,
-}
-
-impl<C: PhantomConstCpuConfig, MOp: Type, ExtraOut: Type> UnitToRegAlloc<C, MOp, ExtraOut> {
-    pub fn mop_ty(self) -> MOp {
-        self.input.data.HdlSome.mop
-    }
-    pub fn extra_out_ty(self) -> ExtraOut {
-        self.output.HdlSome.extra_out_ty()
-    }
-}
-
-#[hdl(no_static)]
-pub struct ExecuteStart<
-    C: PhantomConstGet<CpuConfig>,
-    MOp: Type + MOpTrait<DestReg = UnitOutRegNum<C>>,
-> {
-    pub mop: MOp,
-    pub pc: UInt<64>,
-    pub src_values: Array<PRegValue, { COMMON_MOP_SRC_LEN }>,
-    pub config: C,
-}
-
-#[hdl(no_static)]
-pub struct ExecuteEnd<C: PhantomConstGet<CpuConfig>, ExtraOut> {
-    pub unit_output: UnitOutput<C, ExtraOut>,
-}
-
-#[hdl]
-enum InFlightOpState {
-    Ready,
-    Running,
-    CanceledAndRunning,
-}
-
-impl InFlightOpState {
-    fn ready_next_state(canceling: bool, starting: bool, ending: bool) -> Expr<HdlOption<Self>> {
-        match (canceling, starting, ending) {
-            (false, false, _) => HdlSome(InFlightOpState.Ready()),
-            (false, true, false) => HdlSome(InFlightOpState.Running()),
-            (false, true, true) => HdlNone(),
-            (true, false, _) => HdlNone(),
-            (true, true, false) => HdlSome(InFlightOpState.CanceledAndRunning()),
-            (true, true, true) => HdlNone(),
-        }
-    }
-    fn running_next_state(canceling: bool, _starting: bool, ending: bool) -> Expr<HdlOption<Self>> {
-        match (canceling, ending) {
-            (false, false) => HdlSome(InFlightOpState.Running()),
-            (false, true) => HdlNone(),
-            (true, false) => HdlSome(InFlightOpState.CanceledAndRunning()),
-            (true, true) => HdlNone(),
-        }
-    }
-    fn canceled_and_running_next_state(
-        _canceling: bool,
-        _starting: bool,
-        ending: bool,
-    ) -> Expr<HdlOption<Self>> {
-        if ending {
-            HdlNone()
-        } else {
-            HdlSome(InFlightOpState.CanceledAndRunning())
-        }
-    }
-    /// FIXME: this is working around #[hdl] match not supporting matching values inside structs yet
-    #[hdl]
-    fn connect_next_state(
-        canceling: Expr<Bool>,
-        starting: Expr<Bool>,
-        ending: Expr<Bool>,
-        next_state_fn: fn(canceling: bool, starting: bool, ending: bool) -> Expr<HdlOption<Self>>,
-        next_state: Expr<HdlOption<Self>>,
-    ) {
-        #[hdl]
-        fn recurse<const N: usize>(
-            exprs: &[Expr<Bool>; N],
-            bools: &mut [bool; N],
-            f: &mut impl FnMut(&[bool; N]),
-            arg_index: usize,
-        ) {
-            if arg_index < N {
-                #[hdl]
-                if exprs[arg_index] {
-                    bools[arg_index] = true;
-                    recurse(exprs, bools, f, arg_index + 1);
-                } else {
-                    bools[arg_index] = false;
-                    recurse(exprs, bools, f, arg_index + 1);
-                }
-            } else {
-                f(bools);
-            }
-        }
-        recurse(
-            &[canceling, starting, ending],
-            &mut [false; 3],
-            &mut |&[canceling, starting, ending]| {
-                connect(next_state, next_state_fn(canceling, starting, ending))
-            },
-            0,
-        );
-    }
-}
-
-#[hdl]
-struct InFlightOp<MOp: Type> {
-    state: InFlightOpState,
-    mop: MOp,
-    pc: UInt<64>,
-    src_ready_flags: Array<Bool, { COMMON_MOP_SRC_LEN }>,
-}
-
-#[hdl]
-struct InFlightOpsSummary<OpIndexWidth: Size> {
-    empty_op_index: HdlOption<UIntType<OpIndexWidth>>,
-    ready_op_index: HdlOption<UIntType<OpIndexWidth>>,
-}
-
-impl<OpIndexWidth: Size> InFlightOpsSummary<OpIndexWidth> {
-    #[hdl]
-    fn new<MOp: Type>(
-        op_index: usize,
-        op_index_ty: UIntType<OpIndexWidth>,
-        in_flight_op: impl ToExpr<Type = HdlOption<InFlightOp<MOp>>>,
-    ) -> Expr<Self> {
-        let empty_op_index = wire_with_loc(
-            &format!("empty_op_index_{op_index}"),
-            SourceLocation::caller(),
-            HdlOption[op_index_ty],
-        );
-        connect(empty_op_index, HdlOption[op_index_ty].HdlNone());
-        let ready_op_index = wire_with_loc(
-            &format!("ready_op_index_{op_index}"),
-            SourceLocation::caller(),
-            HdlOption[op_index_ty],
-        );
-        connect(ready_op_index, HdlOption[op_index_ty].HdlNone());
-        #[hdl]
-        if let HdlSome(in_flight_op) = in_flight_op {
-            #[hdl]
-            let InFlightOp::<_> {
-                state,
-                mop: _,
-                pc: _,
-                src_ready_flags,
-            } = in_flight_op;
-            connect(ready_op_index, HdlOption[op_index_ty].HdlNone());
-            #[hdl]
-            match state {
-                InFlightOpState::Ready =>
-                {
-                    #[hdl]
-                    if src_ready_flags.cmp_eq([true; COMMON_MOP_SRC_LEN]) {
-                        connect(ready_op_index, HdlSome(op_index.cast_to(op_index_ty)));
-                    }
-                }
-                InFlightOpState::CanceledAndRunning | InFlightOpState::Running => {}
-            }
-        } else {
-            connect(empty_op_index, HdlSome(op_index.cast_to(op_index_ty)));
-        }
-        #[hdl]
-        InFlightOpsSummary::<_> {
-            empty_op_index,
-            ready_op_index,
-        }
-    }
-    #[hdl]
-    fn combine(l: impl ToExpr<Type = Self>, r: impl ToExpr<Type = Self>) -> Expr<Self> {
-        let l = l.to_expr();
-        let r = r.to_expr();
-        #[hdl]
-        InFlightOpsSummary::<_> {
-            empty_op_index: HdlOption::or(l.empty_op_index, r.empty_op_index),
-            ready_op_index: HdlOption::or(l.ready_op_index, r.ready_op_index),
-        }
-    }
-}
-
-impl InFlightOpsSummary<DynSize> {
-    fn summarize<MOp: Type, MaxInFlight: Size>(
-        in_flight_ops: impl ToExpr<Type = ArrayType<HdlOption<InFlightOp<MOp>>, MaxInFlight>>,
-    ) -> Expr<Self> {
-        let in_flight_ops = in_flight_ops.to_expr();
-        let max_in_flight = in_flight_ops.ty().len();
-        let index_range = 0..max_in_flight;
-        let index_ty = UInt::range(index_range.clone());
-        tree_reduce(
-            index_range.map(|i| Self::new(i, index_ty, in_flight_ops[i])),
-            Self::combine,
-        )
-        .expect("in_flight_ops is known to have len > 0")
-    }
-}
-
-#[hdl_module]
-pub fn unit_base<
-    MOp: Type
-        + MOpTrait<
-            DestReg = UnitOutRegNum<PhantomConst<CpuConfig>>,
-            SrcReg = PRegNum<PhantomConst<CpuConfig>>,
-        >,
-    ExtraOut: Type,
->(
-    config: PhantomConst<CpuConfig>,
-    unit_index: usize,
-    mop_ty: MOp,
-    extra_out_ty: ExtraOut,
-) {
-    #[hdl]
-    let cd: ClockDomain = m.input();
-    #[hdl]
-    let unit_to_reg_alloc: UnitToRegAlloc<PhantomConst<CpuConfig>, MOp, ExtraOut> =
-        m.output(UnitToRegAlloc[config][mop_ty][extra_out_ty]);
-    #[hdl]
-    let execute_start: ReadyValid<ExecuteStart<PhantomConst<CpuConfig>, MOp>> =
-        m.output(ReadyValid[ExecuteStart[config][mop_ty]]);
-    #[hdl]
-    let execute_end: HdlOption<ExecuteEnd<PhantomConst<CpuConfig>, ExtraOut>> =
-        m.input(HdlOption[ExecuteEnd[config][extra_out_ty]]);
-
-    connect(execute_start.data, execute_start.ty().data.HdlNone());
-
-    let max_in_flight = config.get().unit_max_in_flight(unit_index).get();
-    let in_flight_op_ty = InFlightOp[mop_ty];
-    #[hdl]
-    let in_flight_ops = reg_builder()
-        .clock_domain(cd)
-        .reset(repeat(HdlOption[in_flight_op_ty].HdlNone(), max_in_flight));
-
-    let in_flight_ops_summary_value = InFlightOpsSummary::summarize(in_flight_ops);
-    #[hdl]
-    let in_flight_ops_summary = wire(in_flight_ops_summary_value.ty());
-    connect(in_flight_ops_summary, in_flight_ops_summary_value);
-
-    connect(
-        unit_to_reg_alloc.input.ready,
-        HdlOption::is_some(in_flight_ops_summary.empty_op_index),
-    );
-
-    #[hdl]
-    let UnitForwardingInfo::<_> {
-        unit_output_writes,
-        unit_reg_frees,
-    } = unit_to_reg_alloc.unit_forwarding_info;
-    #[hdl]
-    let read_src_regs = wire(mop_ty.src_regs_ty());
-    connect(
-        read_src_regs,
-        repeat(PRegNum[config].const_zero(), ConstUsize),
-    );
-    #[hdl]
-    let read_src_values = wire();
-    connect(read_src_values, [PRegValue::zeroed(); COMMON_MOP_SRC_LEN]);
-    #[hdl]
-    let input_src_regs = wire(mop_ty.src_regs_ty());
-    connect(
-        input_src_regs,
-        repeat(PRegNum[config].const_zero(), ConstUsize),
-    );
-    #[hdl]
-    let input_src_regs_valid = wire();
-    connect(input_src_regs_valid, [true; COMMON_MOP_SRC_LEN]);
-    let mut unit_output_regs_valid: Vec<MemBuilder<Bool>> = (0..unit_output_writes.ty().len())
-        .map(|unit_index| {
-            let mut mem = memory_with_loc(
-                &format!("unit_{unit_index}_output_regs_valid"),
-                Bool,
-                SourceLocation::caller(),
-            );
-            mem.depth(1 << config.get().out_reg_num_width);
-            mem
-        })
-        .collect();
-    for unit_index in 0..unit_output_writes.ty().len() {
-        let mut unit_output_regs = memory_with_loc(
-            &format!("unit_{unit_index}_output_regs"),
-            PRegValue,
-            SourceLocation::caller(),
-        );
-        unit_output_regs.depth(1 << config.get().out_reg_num_width);
-
-        for src_index in 0..COMMON_MOP_SRC_LEN {
-            let read_port = unit_output_regs.new_read_port();
-            let p_reg_num = read_src_regs[src_index];
-            connect_any(read_port.addr, p_reg_num.unit_out_reg.value);
-            connect(read_port.en, false);
-            connect(read_port.clk, cd.clk);
-            #[hdl]
-            if UnitNum::is_index(p_reg_num.unit_num, unit_index) {
-                connect(read_port.en, true);
-                connect(read_src_values[src_index], read_port.data);
-            }
-        }
-
-        for src_index in 0..COMMON_MOP_SRC_LEN {
-            let read_port = unit_output_regs_valid[unit_index].new_read_port();
-            let p_reg_num = input_src_regs[src_index];
-            connect_any(read_port.addr, p_reg_num.unit_out_reg.value);
-            connect(read_port.en, false);
-            connect(read_port.clk, cd.clk);
-            #[hdl]
-            if UnitNum::is_index(p_reg_num.unit_num, unit_index) {
-                connect(read_port.en, true);
-                connect(input_src_regs_valid[src_index], read_port.data);
-            }
-        }
-
-        let write_port = unit_output_regs.new_write_port();
-        connect_any(write_port.addr, 0u8);
-        connect(write_port.en, false);
-        connect(write_port.clk, cd.clk);
-        connect(write_port.data, PRegValue::zeroed());
-        connect(write_port.mask, splat_mask(PRegValue, true.to_expr()));
-        let ready_write_port = unit_output_regs_valid[unit_index].new_write_port();
-        connect_any(ready_write_port.addr, 0u8);
-        connect(ready_write_port.en, false);
-        connect(ready_write_port.clk, cd.clk);
-        connect(ready_write_port.data, true);
-        connect(ready_write_port.mask, true);
-        #[hdl]
-        if let HdlSome(unit_output_write) = unit_output_writes[unit_index] {
-            connect_any(write_port.addr, unit_output_write.which.value);
-            connect(write_port.data, unit_output_write.value);
-            connect(write_port.en, true);
-            connect_any(ready_write_port.addr, unit_output_write.which.value);
-            connect(ready_write_port.en, true);
-            let p_reg_num = #[hdl]
-            PRegNum::<_> {
-                unit_num: UnitNum[config].from_index(unit_index),
-                unit_out_reg: unit_output_write.which,
-            };
-            for src_index in 0..COMMON_MOP_SRC_LEN {
-                #[hdl]
-                if input_src_regs[src_index].cmp_eq(p_reg_num) {
-                    connect(input_src_regs_valid[src_index], true);
-                }
-            }
-        }
-        let free_write_port = unit_output_regs_valid[unit_index].new_write_port();
-        connect_any(free_write_port.addr, 0u8);
-        connect(free_write_port.en, false);
-        connect(free_write_port.clk, cd.clk);
-        connect(free_write_port.data, false);
-        connect(free_write_port.mask, true);
-        #[hdl]
-        if let HdlSome(unit_reg_free) = unit_reg_frees[unit_index] {
-            connect_any(free_write_port.addr, unit_reg_free.value);
-            connect(free_write_port.en, true);
-        }
-    }
-
-    #[hdl]
-    if let HdlSome(ready_op_index) = in_flight_ops_summary.ready_op_index {
-        #[hdl]
-        if let HdlSome(in_flight_op) = in_flight_ops[ready_op_index] {
-            connect(
-                execute_start.data,
-                HdlSome(
-                    #[hdl]
-                    ExecuteStart::<_, _> {
-                        mop: in_flight_op.mop,
-                        pc: in_flight_op.pc,
-                        src_values: read_src_values,
-                        config,
-                    },
-                ),
-            );
-        }
-    }
-
-    connect(
-        unit_to_reg_alloc.output,
-        unit_to_reg_alloc.output.ty().HdlNone(),
-    );
-
-    #[hdl]
-    let input_in_flight_op = wire(HdlOption[in_flight_op_ty]);
-    connect(input_in_flight_op, HdlOption[in_flight_op_ty].HdlNone());
-    #[hdl]
-    if let HdlSome(input) = ReadyValid::firing_data(unit_to_reg_alloc.input) {
-        #[hdl]
-        let UnitInput::<_> { mop, pc } = input;
-        #[hdl]
-        let input_mop_src_regs = wire(mop_ty.src_regs_ty());
-        connect(
-            input_mop_src_regs,
-            repeat(PRegNum[config].const_zero(), ConstUsize),
-        );
-        MOp::connect_src_regs(mop, input_mop_src_regs);
-        let src_ready_flags = wire_with_loc(
-            "input_in_flight_op_src_ready_flags",
-            SourceLocation::caller(),
-            StaticType::TYPE,
-        );
-        connect(src_ready_flags, input_src_regs_valid);
-        connect(input_src_regs, input_mop_src_regs);
-        #[hdl]
-        if unit_to_reg_alloc.cancel_input.cmp_ne(HdlSome(
-            #[hdl]
-            UnitCancelInput::<_> {
-                which: MOp::dest_reg(mop),
-            },
-        )) {
-            connect(
-                input_in_flight_op,
-                HdlSome(
-                    #[hdl]
-                    InFlightOp::<_> {
-                        state: InFlightOpState.Ready(),
-                        mop,
-                        pc,
-                        src_ready_flags,
-                    },
-                ),
-            );
-        }
-        #[hdl]
-        if let HdlSome(empty_op_index) = in_flight_ops_summary.empty_op_index {
-            connect(in_flight_ops[empty_op_index], input_in_flight_op);
-        }
-    }
-
-    #[hdl]
-    let in_flight_op_next_state = wire(Array[HdlOption[InFlightOpState]][max_in_flight]);
-    #[hdl]
-    let in_flight_op_next_src_ready_flags =
-        wire(Array[in_flight_op_ty.src_ready_flags][max_in_flight]);
-    #[hdl]
-    let in_flight_op_canceling = wire(Array[Bool][max_in_flight]);
-    #[hdl]
-    let in_flight_op_execute_starting = wire(Array[Bool][max_in_flight]);
-    #[hdl]
-    let in_flight_op_execute_ending = wire(Array[Bool][max_in_flight]);
-    for in_flight_op_index in 0..max_in_flight {
-        connect(
-            in_flight_op_next_src_ready_flags[in_flight_op_index],
-            [false; COMMON_MOP_SRC_LEN],
-        );
-        connect(in_flight_op_canceling[in_flight_op_index], false);
-        connect(in_flight_op_execute_starting[in_flight_op_index], false);
-        connect(in_flight_op_execute_ending[in_flight_op_index], false);
-        #[hdl]
-        if let HdlSome(in_flight_op) = in_flight_ops[in_flight_op_index] {
-            #[hdl]
-            let InFlightOp::<_> {
-                state,
-                mop,
-                pc,
-                src_ready_flags,
-            } = in_flight_op;
-            let which = MOp::dest_reg(mop);
-            let src_regs = wire_with_loc(
-                &format!("in_flight_op_src_regs_{in_flight_op_index}"),
-                SourceLocation::caller(),
-                mop_ty.src_regs_ty(),
-            );
-            connect(src_regs, repeat(PRegNum[config].const_zero(), ConstUsize));
-            MOp::connect_src_regs(mop, src_regs);
-
-            #[hdl]
-            if in_flight_ops_summary.ready_op_index.cmp_eq(HdlSome(
-                in_flight_op_index.cast_to(in_flight_ops_summary.ty().ready_op_index.HdlSome),
-            )) {
-                connect(read_src_regs, src_regs);
-            }
-
-            connect(
-                in_flight_op_next_src_ready_flags[in_flight_op_index],
-                src_ready_flags,
-            );
-            for unit_index in 0..unit_output_writes.ty().len() {
-                #[hdl]
-                if let HdlSome(unit_output_write) = unit_output_writes[unit_index] {
-                    #[hdl]
-                    let UnitOutputWrite::<_> {
-                        which: unit_out_reg,
-                        value: _,
-                    } = unit_output_write;
-                    let p_reg_num = #[hdl]
-                    PRegNum::<_> {
-                        unit_num: UnitNum[config].from_index(unit_index),
-                        unit_out_reg,
-                    };
-                    for src_index in 0..COMMON_MOP_SRC_LEN {
-                        #[hdl]
-                        if p_reg_num.cmp_eq(src_regs[src_index]) {
-                            connect(
-                                in_flight_op_next_src_ready_flags[in_flight_op_index][src_index],
-                                true,
-                            );
-                        }
-                    }
-                }
-            }
-
-            connect(
-                in_flight_op_canceling[in_flight_op_index],
-                unit_to_reg_alloc.cancel_input.cmp_eq(HdlSome(
-                    #[hdl]
-                    UnitCancelInput::<_> { which },
-                )),
-            );
-
-            #[hdl]
-            if let HdlSome(execute_end) = execute_end {
-                #[hdl]
-                let ExecuteEnd::<_, _> { unit_output } = execute_end;
-                #[hdl]
-                if which.cmp_eq(unit_output.which) {
-                    connect(in_flight_op_execute_ending[in_flight_op_index], true);
-                    #[hdl]
-                    if !in_flight_op_canceling[in_flight_op_index] {
-                        #[hdl]
-                        match state {
-                            InFlightOpState::Running | InFlightOpState::Ready => {
-                                connect(unit_to_reg_alloc.output, HdlSome(unit_output))
-                            }
-                            InFlightOpState::CanceledAndRunning => {}
-                        }
-                    }
-                }
-            }
-            #[hdl]
-            if let HdlSome(execute_start) = ReadyValid::firing_data(execute_start) {
-                #[hdl]
-                if which.cmp_eq(MOp::dest_reg(execute_start.mop)) {
-                    connect(in_flight_op_execute_starting[in_flight_op_index], true);
-                }
-            }
-            let connect_next_state = |f| {
-                InFlightOpState::connect_next_state(
-                    in_flight_op_canceling[in_flight_op_index],
-                    in_flight_op_execute_starting[in_flight_op_index],
-                    in_flight_op_execute_ending[in_flight_op_index],
-                    f,
-                    in_flight_op_next_state[in_flight_op_index],
-                );
-            };
-            #[hdl]
-            match state {
-                InFlightOpState::Ready => connect_next_state(InFlightOpState::ready_next_state),
-                InFlightOpState::Running => connect_next_state(InFlightOpState::running_next_state),
-                InFlightOpState::CanceledAndRunning => {
-                    connect_next_state(InFlightOpState::canceled_and_running_next_state);
-                }
-            }
-            #[hdl]
-            if let HdlSome(state) = in_flight_op_next_state[in_flight_op_index] {
-                connect(
-                    in_flight_ops[in_flight_op_index],
-                    HdlSome(
-                        #[hdl]
-                        InFlightOp::<_> {
-                            state,
-                            mop,
-                            pc,
-                            src_ready_flags: in_flight_op_next_src_ready_flags[in_flight_op_index],
-                        },
-                    ),
-                );
-            } else {
-                connect(
-                    in_flight_ops[in_flight_op_index],
-                    HdlOption[in_flight_op_ty].HdlNone(),
-                );
-            }
-        } else {
-            connect(in_flight_op_next_state[in_flight_op_index], HdlNone());
-        }
-    }
-}

crates/cpu/src/util.rs

@@ -1,8 +1,15 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information
 
-use fayalite::{expr::ops::ArrayLiteral, module::wire_with_loc, prelude::*};
+use fayalite::{
-use std::num::NonZero;
+    bundle::BundleType, expr::ops::ArrayLiteral, module::wire_with_loc, prelude::*,
+    sim::vcd::VcdWriterDecls, util::RcWriter,
+};
+use std::{
+    num::NonZero,
+    panic::Location,
+    path::{Path, PathBuf},
+};
 
 pub mod array_vec;
 pub mod tree_reduce;
@@ -310,3 +317,152 @@ impl LFSR31 {
         state
     }
 }
+
+pub struct CheckedVcdOutput {
+    writer: Option<RcWriter>,
+    expected_path: PathBuf,
+    expected_contents: Result<String, (Option<PathBuf>, std::io::Error)>,
+    location: &'static Location<'static>,
+}
+
+impl CheckedVcdOutput {
+    #[must_use]
+    #[track_caller]
+    pub fn new<T: BundleType>(sim: &mut Simulation<T>, expected_path: PathBuf) -> Self {
+        let writer = RcWriter::default();
+        sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
+        Self {
+            writer: Some(writer),
+            expected_contents: std::fs::read_to_string(&expected_path).map_err(|e| {
+                eprintln!(
+                    "error: failed to read expected VCD from: {}",
+                    expected_path.display(),
+                );
+                (std::env::current_dir().ok(), e)
+            }),
+            expected_path,
+            location: Location::caller(),
+        }
+    }
+    #[must_use]
+    #[track_caller]
+    #[doc(hidden)]
+    pub fn __checked_vcd_output_macro_helper<T: BundleType>(
+        sim: &mut Simulation<T>,
+        cargo_manifest_dir: &'static str,
+        path: &'static str,
+    ) -> Self {
+        Self::new(sim, Path::new(cargo_manifest_dir).join(path))
+    }
+    pub fn with_vcd_output<R>(&self, f: impl FnOnce(&str) -> R) -> R {
+        let Some(writer) = &self.writer else {
+            unreachable!();
+        };
+        writer.clone().borrow(|output| {
+            let Ok(output) = str::from_utf8(output) else {
+                unreachable!("VcdWriter writes valid UTF-8");
+            };
+            f(output)
+        })
+    }
+    #[track_caller]
+    pub fn finish(mut self) {
+        let Ok(()) = self.finish_impl(|msg| panic!("{msg}"));
+    }
+    fn finish_impl<E>(
+        &mut self,
+        error: impl FnOnce(std::fmt::Arguments<'_>) -> E,
+    ) -> Result<(), E> {
+        let Self {
+            writer: Some(writer),
+            expected_path,
+            expected_contents,
+            location,
+        } = self
+        else {
+            // already finished
+            return Ok(());
+        };
+        let Ok(vcd) = String::from_utf8(writer.take()) else {
+            unreachable!("VcdWriter writes valid UTF-8");
+        };
+        let expected_path_d = expected_path.display();
+        if expected_contents
+            .as_ref()
+            .is_ok_and(|expected_contents| *expected_contents == vcd)
+        {
+            // avoid written output from being split from threads interleaving writes to stdout
+            let _stdout = std::io::stderr().lock();
+            // use println to get output captured by tests
+            println!("\n{location}: generated VCD matches the expected VCD in {expected_path_d}");
+            return Ok(());
+        }
+        // avoid written output from being split from threads interleaving writes to stderr
+        let _stderr = std::io::stderr().lock();
+        let error = |msg: std::fmt::Arguments<'_>| {
+            // print msg at both beginning and end so it's easier to find when the vcd is huge
+            Err(error(format_args!(
+                "\n{msg}####### VCD:\n{vcd}\n#######\n{msg}"
+            )))
+        };
+        let error = |msg: std::fmt::Arguments<'_>| match &*expected_contents {
+            Ok(_) => error(format_args!(
+                "{location}: generated VCD doesn't match the expected VCD in {expected_path_d}\n\
+                {msg}",
+            )),
+            Err((Some(current_dir), e)) => error(format_args!(
+                "{location}: generated VCD doesn't match the expected VCD in {expected_path_d}\n\
+                error: failed to read: {e}\n\
+                current dir: {current_dir}\n\
+                {msg}",
+                current_dir = current_dir.display(),
+            )),
+            Err((None, e)) => error(format_args!(
+                "{location}: generated VCD doesn't match the expected VCD in {expected_path_d}\n\
+                error: failed to read: {e}\n\
+                {msg}",
+            )),
+        };
+        const OVERWRITE_VAR_NAME: &str = "OVERWRITE_EXPECTED_VCD";
+        const OVERWRITE_VAR_VALUE: &str = "overwrite";
+        match std::env::var_os(OVERWRITE_VAR_NAME) {
+            Some(v) if v == OVERWRITE_VAR_VALUE => match std::fs::write(&expected_path, &vcd) {
+                Ok(()) => error(format_args!(
+                    "warning: since `{OVERWRITE_VAR_NAME}={OVERWRITE_VAR_VALUE}` is set -- writing the generated VCD to {expected_path_d}\n"
+                )),
+                Err(e) => error(format_args!(
+                    "error: since `{OVERWRITE_VAR_NAME}={OVERWRITE_VAR_VALUE}` is set -- tried to write the generated VCD to {expected_path_d}\n\
+                    error: failed to write: {e}"
+                )),
+            },
+            _ => error(format_args!(
+                "note: rerun the test with the environment variable `{OVERWRITE_VAR_NAME}={OVERWRITE_VAR_VALUE}`\n\
+                to update the expected output to match the generated output.\n"
+            )),
+        }
+    }
+}
+
+impl Drop for CheckedVcdOutput {
+    #[track_caller]
+    fn drop(&mut self) {
+        let _ = self.finish_impl(|msg| {
+            if std::thread::panicking() {
+                eprintln!("{msg}"); // use eprintln to get output captured by tests
+            } else {
+                panic!("{msg}");
+            }
+        });
+    }
+}
+
+#[macro_export]
+macro_rules! checked_vcd_output {
+    ($sim:expr, $path_relative_to_manifest_dir:expr $(,)?) => {
+        $crate::util::CheckedVcdOutput::__checked_vcd_output_macro_helper(
+            $sim,
+            ::std::env!("CARGO_MANIFEST_DIR"),
+            ::std::concat!($path_relative_to_manifest_dir),
+        )
+    };
+}

crates/cpu/tests/expected/rename_execute_retire_fibonacci_combinatorial.vcd

@@ -735,6 +735,15 @@ $upscope $end
 $upscope $end
 $scope struct to_units $end
 $scope struct u0_AluBranch $end
+$scope struct global_state $end
+$scope struct flags_mode $end
+$var string 1 ^CGEk \$tag $end
+$scope struct PowerISA $end
+$upscope $end
+$scope struct X86 $end
+$upscope $end
+$upscope $end
+$upscope $end
 $scope struct enqueue $end
 $scope struct data $end
 $var string 1 GsdD" \$tag $end
@@ -834,6 +843,15 @@ $upscope $end
 $var string 1 o,/9H config $end
 $upscope $end
 $scope struct u1_AluBranch $end
+$scope struct global_state $end
+$scope struct flags_mode $end
+$var string 1 GQ'Q> \$tag $end
+$scope struct PowerISA $end
+$upscope $end
+$scope struct X86 $end
+$upscope $end
+$upscope $end
+$upscope $end
 $scope struct enqueue $end
 $scope struct data $end
 $var string 1 8c+O\ \$tag $end
@@ -933,6 +951,15 @@ $upscope $end
 $var string 1 ^h`~v config $end
 $upscope $end
 $scope struct u2_AluBranch $end
+$scope struct global_state $end
+$scope struct flags_mode $end
+$var string 1 aRx5V \$tag $end
+$scope struct PowerISA $end
+$upscope $end
+$scope struct X86 $end
+$upscope $end
+$upscope $end
+$upscope $end
 $scope struct enqueue $end
 $scope struct data $end
 $var string 1 2+~8. \$tag $end
@@ -1032,6 +1059,15 @@ $upscope $end
 $var string 1 (xcO& config $end
 $upscope $end
 $scope struct u3_LoadStore $end
+$scope struct global_state $end
+$scope struct flags_mode $end
+$var string 1 ?S|U6 \$tag $end
+$scope struct PowerISA $end
+$upscope $end
+$scope struct X86 $end
+$upscope $end
+$upscope $end
+$upscope $end
 $scope struct enqueue $end
 $scope struct data $end
 $var string 1 @a:}a \$tag $end
@@ -1131,6 +1167,15 @@ $upscope $end
 $var string 1 xI$mR config $end
 $upscope $end
 $scope struct u4_TransformedMove $end
+$scope struct global_state $end
+$scope struct flags_mode $end
+$var string 1 T,bm_ \$tag $end
+$scope struct PowerISA $end
+$upscope $end
+$scope struct X86 $end
+$upscope $end
+$upscope $end
+$upscope $end
 $scope struct enqueue $end
 $scope struct data $end
 $var string 1 R]s+W \$tag $end
@@ -1232,6 +1277,15 @@ $upscope $end
 $var string 1 J1Kd= config $end
 $upscope $end
 $scope struct state_for_debug $end
+$scope struct global_state $end
+$scope struct flags_mode $end
+$var string 1 B<sY_ \$tag $end
+$scope struct PowerISA $end
+$upscope $end
+$scope struct X86 $end
+$upscope $end
+$upscope $end
+$upscope $end
 $scope struct rename_delayed $end
 $scope struct elements $end
 $scope struct \[0] $end
@@ -7535,6 +7589,15 @@ $upscope $end
 $upscope $end
 $scope module u0_AluBranch $end
 $scope struct from_execute $end
+$scope struct global_state $end
+$scope struct flags_mode $end
+$var string 1 Q3.G \$tag $end
+$scope struct PowerISA $end
+$upscope $end
+$scope struct X86 $end
+$upscope $end
+$upscope $end
+$upscope $end
 $scope struct enqueue $end
 $scope struct data $end
 $var string 1 [C%Hf \$tag $end
@@ -7636,6 +7699,15 @@ $upscope $end
 $upscope $end
 $scope module u1_AluBranch $end
 $scope struct from_execute $end
+$scope struct global_state $end
+$scope struct flags_mode $end
+$var string 1 eJlg^ \$tag $end
+$scope struct PowerISA $end
+$upscope $end
+$scope struct X86 $end
+$upscope $end
+$upscope $end
+$upscope $end
 $scope struct enqueue $end
 $scope struct data $end
 $var string 1 #"r$8 \$tag $end
@@ -7737,6 +7809,15 @@ $upscope $end
 $upscope $end
 $scope module u2_AluBranch $end
 $scope struct from_execute $end
+$scope struct global_state $end
+$scope struct flags_mode $end
+$var string 1 GN@do \$tag $end
+$scope struct PowerISA $end
+$upscope $end
+$scope struct X86 $end
+$upscope $end
+$upscope $end
+$upscope $end
 $scope struct enqueue $end
 $scope struct data $end
 $var string 1 EP<U| \$tag $end
@@ -7842,6 +7923,15 @@ $var wire 1 LCUP8 clk $end
 $var wire 1 U/A-E rst $end
 $upscope $end
 $scope struct from_execute $end
+$scope struct global_state $end
+$scope struct flags_mode $end
+$var string 1 N^wWl \$tag $end
+$scope struct PowerISA $end
+$upscope $end
+$scope struct X86 $end
+$upscope $end
+$upscope $end
+$upscope $end
 $scope struct enqueue $end
 $scope struct data $end
 $var string 1 N;QS\ \$tag $end
@@ -8285,6 +8375,15 @@ $var wire 1 %/Ado clk $end
 $var wire 1 uH]!m rst $end
 $upscope $end
 $scope struct from_execute $end
+$scope struct global_state $end
+$scope struct flags_mode $end
+$var string 1 j4FYG \$tag $end
+$scope struct PowerISA $end
+$upscope $end
+$scope struct X86 $end
+$upscope $end
+$upscope $end
+$upscope $end
 $scope struct enqueue $end
 $scope struct data $end
 $var string 1 qpx\a \$tag $end
@@ -9363,6 +9462,7 @@ b0 iXLU`
 sAddSub\x20{},\x20rzero,\x20rzero,\x20rzero,\x200x0_i26 `4f=q
 b0 J8qAt
 sPhantomConst(\"0..=20\") %JRz8
+sPowerISA\x20(0) ^CGEk
 sHdlNone\x20(0) GsdD"
 b0 }:QxN
 b0 hh!}]
@@ -9412,6 +9512,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kin
 sHdlNone\x20(0) eil|L
 0!D)]|
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"LoadStore\",\"max_in_flight\":null},{\"kind\":\"TransformedMove\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":3,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) o,/9H
+sPowerISA\x20(0) GQ'Q>
 sHdlNone\x20(0) 8c+O\
 b0 PfE*7
 b0 !}q}3
@@ -9461,6 +9562,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kin
 sHdlNone\x20(0) ^(+@*
 07at%k
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"LoadStore\",\"max_in_flight\":null},{\"kind\":\"TransformedMove\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":3,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ^h`~v
+sPowerISA\x20(0) aRx5V
 sHdlNone\x20(0) 2+~8.
 b0 e.>!d
 b0 Pf4v-
@@ -9510,6 +9612,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kin
 sHdlNone\x20(0) FM/L}
 0]G2vi
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"LoadStore\",\"max_in_flight\":null},{\"kind\":\"TransformedMove\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":3,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) (xcO&
+sPowerISA\x20(0) ?S|U6
 sHdlNone\x20(0) @a:}a
 b0 ck@eh
 b0 4rI|P
@@ -9559,6 +9662,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kin
 sHdlNone\x20(0) O}TB$
 070$9#
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"LoadStore\",\"max_in_flight\":null},{\"kind\":\"TransformedMove\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":3,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) xI$mR
+sPowerISA\x20(0) T,bm_
 sHdlNone\x20(0) R]s+W
 b0 esX't
 b0 /)"Kk
@@ -9609,6 +9713,7 @@ sHdlNone\x20(0) |0hb'
 0M"^lQ
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"LoadStore\",\"max_in_flight\":null},{\"kind\":\"TransformedMove\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":3,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) "_2i-
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"LoadStore\",\"max_in_flight\":null},{\"kind\":\"TransformedMove\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":3,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) J1Kd=
+sPowerISA\x20(0) B<sY_
 0D<c#n
 b0 e-F>7
 b0 EH[m}
@@ -13122,6 +13227,7 @@ s\"\" SmX4"
 s\"\" y.\2m
 s\"\" n?a24
 s\"\" F8i).
+sPowerISA\x20(0) Q3.G
 sHdlNone\x20(0) [C%Hf
 b0 %RtTH
 b0 8/pV|
@@ -13171,6 +13277,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kin
 sHdlNone\x20(0) u2peT
 0k,__>
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"LoadStore\",\"max_in_flight\":null},{\"kind\":\"TransformedMove\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":3,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ^pE+,
+sPowerISA\x20(0) eJlg^
 sHdlNone\x20(0) #"r$8
 b0 EYNKC
 b0 <`a(d
@@ -13220,6 +13327,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kin
 sHdlNone\x20(0) A<iL;
 0{bf:`
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"LoadStore\",\"max_in_flight\":null},{\"kind\":\"TransformedMove\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":3,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ";FVr
+sPowerISA\x20(0) GN@do
 sHdlNone\x20(0) EP<U|
 b0 /,qQx
 b0 g:=mM
@@ -13271,6 +13379,7 @@ sHdlNone\x20(0) rWrQI
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"LoadStore\",\"max_in_flight\":null},{\"kind\":\"TransformedMove\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":3,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) p4_Ao
 0LCUP8
 1U/A-E
+sPowerISA\x20(0) N^wWl
 sHdlNone\x20(0) N;QS\
 b0 ,m'YK
 b0 #zFMy
@@ -13560,6 +13669,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kin
 0BqYmm
 0%/Ado
 1uH]!m
+sPowerISA\x20(0) j4FYG
 sHdlNone\x20(0) qpx\a
 b0 4MnxU
 b0 h8|hD

crates/cpu/tests/expected/rename_execute_retire_fibonacci_non_combinatorial.vcd

@@ -735,6 +735,15 @@ $upscope $end
 $upscope $end
 $scope struct to_units $end
 $scope struct u0_AluBranch $end
+$scope struct global_state $end
+$scope struct flags_mode $end
+$var string 1 ^CGEk \$tag $end
+$scope struct PowerISA $end
+$upscope $end
+$scope struct X86 $end
+$upscope $end
+$upscope $end
+$upscope $end
 $scope struct enqueue $end
 $scope struct data $end
 $var string 1 GsdD" \$tag $end
@@ -834,6 +843,15 @@ $upscope $end
 $var string 1 o,/9H config $end
 $upscope $end
 $scope struct u1_AluBranch $end
+$scope struct global_state $end
+$scope struct flags_mode $end
+$var string 1 GQ'Q> \$tag $end
+$scope struct PowerISA $end
+$upscope $end
+$scope struct X86 $end
+$upscope $end
+$upscope $end
+$upscope $end
 $scope struct enqueue $end
 $scope struct data $end
 $var string 1 8c+O\ \$tag $end
@@ -933,6 +951,15 @@ $upscope $end
 $var string 1 ^h`~v config $end
 $upscope $end
 $scope struct u2_AluBranch $end
+$scope struct global_state $end
+$scope struct flags_mode $end
+$var string 1 aRx5V \$tag $end
+$scope struct PowerISA $end
+$upscope $end
+$scope struct X86 $end
+$upscope $end
+$upscope $end
+$upscope $end
 $scope struct enqueue $end
 $scope struct data $end
 $var string 1 2+~8. \$tag $end
@@ -1032,6 +1059,15 @@ $upscope $end
 $var string 1 (xcO& config $end
 $upscope $end
 $scope struct u3_LoadStore $end
+$scope struct global_state $end
+$scope struct flags_mode $end
+$var string 1 ?S|U6 \$tag $end
+$scope struct PowerISA $end
+$upscope $end
+$scope struct X86 $end
+$upscope $end
+$upscope $end
+$upscope $end
 $scope struct enqueue $end
 $scope struct data $end
 $var string 1 @a:}a \$tag $end
@@ -1131,6 +1167,15 @@ $upscope $end
 $var string 1 xI$mR config $end
 $upscope $end
 $scope struct u4_TransformedMove $end
+$scope struct global_state $end
+$scope struct flags_mode $end
+$var string 1 T,bm_ \$tag $end
+$scope struct PowerISA $end
+$upscope $end
+$scope struct X86 $end
+$upscope $end
+$upscope $end
+$upscope $end
 $scope struct enqueue $end
 $scope struct data $end
 $var string 1 R]s+W \$tag $end
@@ -1232,6 +1277,15 @@ $upscope $end
 $var string 1 J1Kd= config $end
 $upscope $end
 $scope struct state_for_debug $end
+$scope struct global_state $end
+$scope struct flags_mode $end
+$var string 1 B<sY_ \$tag $end
+$scope struct PowerISA $end
+$upscope $end
+$scope struct X86 $end
+$upscope $end
+$upscope $end
+$upscope $end
 $scope struct rename_delayed $end
 $scope struct elements $end
 $scope struct \[0] $end
@@ -7539,6 +7593,15 @@ $var wire 1 ~ge89 clk $end
 $var wire 1 1kyC" rst $end
 $upscope $end
 $scope struct from_execute $end
+$scope struct global_state $end
+$scope struct flags_mode $end
+$var string 1 Q3.G \$tag $end
+$scope struct PowerISA $end
+$upscope $end
+$scope struct X86 $end
+$upscope $end
+$upscope $end
+$upscope $end
 $scope struct enqueue $end
 $scope struct data $end
 $var string 1 [C%Hf \$tag $end
@@ -7638,6 +7701,15 @@ $upscope $end
 $var string 1 ^pE+, config $end
 $upscope $end
 $scope struct debug_state $end
+$scope struct global_state $end
+$scope struct flags_mode $end
+$var string 1 1Rz_e \$tag $end
+$scope struct PowerISA $end
+$upscope $end
+$scope struct X86 $end
+$upscope $end
+$upscope $end
+$upscope $end
 $scope struct ops $end
 $scope struct elements $end
 $scope struct \[0] $end
@@ -8017,6 +8089,15 @@ $var wire 1 %3;Sp clk $end
 $var wire 1 }GG*c rst $end
 $upscope $end
 $scope struct from_execute $end
+$scope struct global_state $end
+$scope struct flags_mode $end
+$var string 1 eJlg^ \$tag $end
+$scope struct PowerISA $end
+$upscope $end
+$scope struct X86 $end
+$upscope $end
+$upscope $end
+$upscope $end
 $scope struct enqueue $end
 $scope struct data $end
 $var string 1 #"r$8 \$tag $end
@@ -8116,6 +8197,15 @@ $upscope $end
 $var string 1 ";FVr config $end
 $upscope $end
 $scope struct debug_state $end
+$scope struct global_state $end
+$scope struct flags_mode $end
+$var string 1 1~`.z \$tag $end
+$scope struct PowerISA $end
+$upscope $end
+$scope struct X86 $end
+$upscope $end
+$upscope $end
+$upscope $end
 $scope struct ops $end
 $scope struct elements $end
 $scope struct \[0] $end
@@ -8495,6 +8585,15 @@ $var wire 1 BEBSD clk $end
 $var wire 1 ML]/~ rst $end
 $upscope $end
 $scope struct from_execute $end
+$scope struct global_state $end
+$scope struct flags_mode $end
+$var string 1 GN@do \$tag $end
+$scope struct PowerISA $end
+$upscope $end
+$scope struct X86 $end
+$upscope $end
+$upscope $end
+$upscope $end
 $scope struct enqueue $end
 $scope struct data $end
 $var string 1 EP<U| \$tag $end
@@ -8594,6 +8693,15 @@ $upscope $end
 $var string 1 p4_Ao config $end
 $upscope $end
 $scope struct debug_state $end
+$scope struct global_state $end
+$scope struct flags_mode $end
+$var string 1 d_WoL \$tag $end
+$scope struct PowerISA $end
+$upscope $end
+$scope struct X86 $end
+$upscope $end
+$upscope $end
+$upscope $end
 $scope struct ops $end
 $scope struct elements $end
 $scope struct \[0] $end
@@ -8973,6 +9081,15 @@ $var wire 1 LCUP8 clk $end
 $var wire 1 U/A-E rst $end
 $upscope $end
 $scope struct from_execute $end
+$scope struct global_state $end
+$scope struct flags_mode $end
+$var string 1 N^wWl \$tag $end
+$scope struct PowerISA $end
+$upscope $end
+$scope struct X86 $end
+$upscope $end
+$upscope $end
+$upscope $end
 $scope struct enqueue $end
 $scope struct data $end
 $var string 1 N;QS\ \$tag $end
@@ -9416,6 +9533,15 @@ $var wire 1 %/Ado clk $end
 $var wire 1 uH]!m rst $end
 $upscope $end
 $scope struct from_execute $end
+$scope struct global_state $end
+$scope struct flags_mode $end
+$var string 1 j4FYG \$tag $end
+$scope struct PowerISA $end
+$upscope $end
+$scope struct X86 $end
+$upscope $end
+$upscope $end
+$upscope $end
 $scope struct enqueue $end
 $scope struct data $end
 $var string 1 qpx\a \$tag $end
@@ -10494,6 +10620,7 @@ b0 iXLU`
 sAddSub\x20{},\x20rzero,\x20rzero,\x20rzero,\x200x0_i26 `4f=q
 b0 J8qAt
 sPhantomConst(\"0..=20\") %JRz8
+sPowerISA\x20(0) ^CGEk
 sHdlNone\x20(0) GsdD"
 b0 }:QxN
 b0 hh!}]
@@ -10543,6 +10670,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kin
 sHdlNone\x20(0) eil|L
 0!D)]|
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"LoadStore\",\"max_in_flight\":null},{\"kind\":\"TransformedMove\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":3,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) o,/9H
+sPowerISA\x20(0) GQ'Q>
 sHdlNone\x20(0) 8c+O\
 b0 PfE*7
 b0 !}q}3
@@ -10592,6 +10720,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kin
 sHdlNone\x20(0) ^(+@*
 07at%k
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"LoadStore\",\"max_in_flight\":null},{\"kind\":\"TransformedMove\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":3,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ^h`~v
+sPowerISA\x20(0) aRx5V
 sHdlNone\x20(0) 2+~8.
 b0 e.>!d
 b0 Pf4v-
@@ -10641,6 +10770,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kin
 sHdlNone\x20(0) FM/L}
 0]G2vi
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"LoadStore\",\"max_in_flight\":null},{\"kind\":\"TransformedMove\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":3,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) (xcO&
+sPowerISA\x20(0) ?S|U6
 sHdlNone\x20(0) @a:}a
 b0 ck@eh
 b0 4rI|P
@@ -10690,6 +10820,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kin
 sHdlNone\x20(0) O}TB$
 070$9#
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"LoadStore\",\"max_in_flight\":null},{\"kind\":\"TransformedMove\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":3,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) xI$mR
+sPowerISA\x20(0) T,bm_
 sHdlNone\x20(0) R]s+W
 b0 esX't
 b0 /)"Kk
@@ -10740,6 +10871,7 @@ sHdlNone\x20(0) |0hb'
 0M"^lQ
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"LoadStore\",\"max_in_flight\":null},{\"kind\":\"TransformedMove\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":3,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) "_2i-
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"LoadStore\",\"max_in_flight\":null},{\"kind\":\"TransformedMove\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":3,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) J1Kd=
+sPowerISA\x20(0) B<sY_
 0D<c#n
 b0 e-F>7
 b0 EH[m}
@@ -14255,6 +14387,7 @@ s\"\" n?a24
 s\"\" F8i).
 0~ge89
 11kyC"
+sPowerISA\x20(0) Q3.G
 sHdlNone\x20(0) [C%Hf
 b0 %RtTH
 b0 8/pV|
@@ -14304,6 +14437,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kin
 sHdlNone\x20(0) u2peT
 0k,__>
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"LoadStore\",\"max_in_flight\":null},{\"kind\":\"TransformedMove\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":3,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ^pE+,
+sPowerISA\x20(0) 1Rz_e
 b0 SeKza
 b0 $(}f)
 b0 VPYyn
@@ -14509,6 +14643,7 @@ sPhantomConst(\"0..=8\") kaY""
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"LoadStore\",\"max_in_flight\":null},{\"kind\":\"TransformedMove\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":3,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) d$rs<
 0%3;Sp
 1}GG*c
+sPowerISA\x20(0) eJlg^
 sHdlNone\x20(0) #"r$8
 b0 EYNKC
 b0 <`a(d
@@ -14558,6 +14693,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kin
 sHdlNone\x20(0) A<iL;
 0{bf:`
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"LoadStore\",\"max_in_flight\":null},{\"kind\":\"TransformedMove\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":3,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ";FVr
+sPowerISA\x20(0) 1~`.z
 b0 E[Fv@
 b0 oKzpD
 b0 H,?[}
@@ -14763,6 +14899,7 @@ sPhantomConst(\"0..=8\") \8'R-
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"LoadStore\",\"max_in_flight\":null},{\"kind\":\"TransformedMove\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":3,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) jV<x@
 0BEBSD
 1ML]/~
+sPowerISA\x20(0) GN@do
 sHdlNone\x20(0) EP<U|
 b0 /,qQx
 b0 g:=mM
@@ -14812,6 +14949,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kin
 sHdlNone\x20(0) rWrQI
 0C>S:u
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"LoadStore\",\"max_in_flight\":null},{\"kind\":\"TransformedMove\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":3,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) p4_Ao
+sPowerISA\x20(0) d_WoL
 b0 xo`bv
 b0 rqJ]#
 b0 0j[<w
@@ -15017,6 +15155,7 @@ sPhantomConst(\"0..=8\") 4@cK:
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"LoadStore\",\"max_in_flight\":null},{\"kind\":\"TransformedMove\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":3,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) E#:dV
 0LCUP8
 1U/A-E
+sPowerISA\x20(0) N^wWl
 sHdlNone\x20(0) N;QS\
 b0 ,m'YK
 b0 #zFMy
@@ -15306,6 +15445,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kin
 0BqYmm
 0%/Ado
 1uH]!m
+sPowerISA\x20(0) j4FYG
 sHdlNone\x20(0) qpx\a
 b0 4MnxU
 b0 h8|hD
@@ -16354,6 +16494,30 @@ b1 Nd3$v
 1BEBSD
 1LCUP8
 1%/Ado
+0OWS\?
+0!D)]|
+0?N6#F
+0k,__>
+1OWS\?
+1!D)]|
+1?N6#F
+1k,__>
+0QE<q^
+07at%k
+0>YMCs
+0{bf:`
+1QE<q^
+17at%k
+1>YMCs
+1{bf:`
+0t_zS6
+0]G2vi
+0c7WAd
+0C>S:u
+1t_zS6
+1]G2vi
+1c7WAd
+1C>S:u
 #1000000
 0spsS)
 0OkSP&

crates/cpu/tests/expected/rename_execute_retire_head_n1.vcd

@@ -683,6 +683,15 @@ $upscope $end
 $upscope $end
 $scope struct to_units $end
 $scope struct u0_AluBranch $end
+$scope struct global_state $end
+$scope struct flags_mode $end
+$var string 1 ^CGEk \$tag $end
+$scope struct PowerISA $end
+$upscope $end
+$scope struct X86 $end
+$upscope $end
+$upscope $end
+$upscope $end
 $scope struct enqueue $end
 $scope struct data $end
 $var string 1 GsdD" \$tag $end
@@ -782,6 +791,15 @@ $upscope $end
 $var string 1 o,/9H config $end
 $upscope $end
 $scope struct u1_AluBranch $end
+$scope struct global_state $end
+$scope struct flags_mode $end
+$var string 1 GQ'Q> \$tag $end
+$scope struct PowerISA $end
+$upscope $end
+$scope struct X86 $end
+$upscope $end
+$upscope $end
+$upscope $end
 $scope struct enqueue $end
 $scope struct data $end
 $var string 1 8c+O\ \$tag $end
@@ -881,6 +899,15 @@ $upscope $end
 $var string 1 ^h`~v config $end
 $upscope $end
 $scope struct u2_LoadStore $end
+$scope struct global_state $end
+$scope struct flags_mode $end
+$var string 1 FyT+} \$tag $end
+$scope struct PowerISA $end
+$upscope $end
+$scope struct X86 $end
+$upscope $end
+$upscope $end
+$upscope $end
 $scope struct enqueue $end
 $scope struct data $end
 $var string 1 !Ax^^ \$tag $end
@@ -980,6 +1007,15 @@ $upscope $end
 $var string 1 TN{?v config $end
 $upscope $end
 $scope struct u3_TransformedMove $end
+$scope struct global_state $end
+$scope struct flags_mode $end
+$var string 1 S'#K& \$tag $end
+$scope struct PowerISA $end
+$upscope $end
+$scope struct X86 $end
+$upscope $end
+$upscope $end
+$upscope $end
 $scope struct enqueue $end
 $scope struct data $end
 $var string 1 ]l$S0 \$tag $end
@@ -1081,6 +1117,15 @@ $upscope $end
 $var string 1 J1Kd= config $end
 $upscope $end
 $scope struct state_for_debug $end
+$scope struct global_state $end
+$scope struct flags_mode $end
+$var string 1 B<sY_ \$tag $end
+$scope struct PowerISA $end
+$upscope $end
+$scope struct X86 $end
+$upscope $end
+$upscope $end
+$upscope $end
 $scope struct rename_delayed $end
 $scope struct elements $end
 $scope struct \[0] $end
@@ -7067,6 +7112,15 @@ $upscope $end
 $upscope $end
 $scope module u0_AluBranch $end
 $scope struct from_execute $end
+$scope struct global_state $end
+$scope struct flags_mode $end
+$var string 1 Q3.G \$tag $end
+$scope struct PowerISA $end
+$upscope $end
+$scope struct X86 $end
+$upscope $end
+$upscope $end
+$upscope $end
 $scope struct enqueue $end
 $scope struct data $end
 $var string 1 [C%Hf \$tag $end
@@ -7168,6 +7222,15 @@ $upscope $end
 $upscope $end
 $scope module u1_AluBranch $end
 $scope struct from_execute $end
+$scope struct global_state $end
+$scope struct flags_mode $end
+$var string 1 eJlg^ \$tag $end
+$scope struct PowerISA $end
+$upscope $end
+$scope struct X86 $end
+$upscope $end
+$upscope $end
+$upscope $end
 $scope struct enqueue $end
 $scope struct data $end
 $var string 1 #"r$8 \$tag $end
@@ -7273,6 +7336,15 @@ $var wire 1 R_bmG clk $end
 $var wire 1 z[UFy rst $end
 $upscope $end
 $scope struct from_execute $end
+$scope struct global_state $end
+$scope struct flags_mode $end
+$var string 1 k/N|/ \$tag $end
+$scope struct PowerISA $end
+$upscope $end
+$scope struct X86 $end
+$upscope $end
+$upscope $end
+$upscope $end
 $scope struct enqueue $end
 $scope struct data $end
 $var string 1 iE0UB \$tag $end
@@ -7716,6 +7788,15 @@ $var wire 1 {Z\hs clk $end
 $var wire 1 s7Y>O rst $end
 $upscope $end
 $scope struct from_execute $end
+$scope struct global_state $end
+$scope struct flags_mode $end
+$var string 1 &blD1 \$tag $end
+$scope struct PowerISA $end
+$upscope $end
+$scope struct X86 $end
+$upscope $end
+$upscope $end
+$upscope $end
 $scope struct enqueue $end
 $scope struct data $end
 $var string 1 -ayw\ \$tag $end
@@ -8760,6 +8841,7 @@ b0 iXLU`
 sAddSub\x20{},\x20rzero,\x20rzero,\x20rzero,\x200x0_i26 `4f=q
 b0 J8qAt
 sPhantomConst(\"0..=20\") %JRz8
+sPowerISA\x20(0) ^CGEk
 sHdlNone\x20(0) GsdD"
 b0 }:QxN
 b0 hh!}]
@@ -8809,6 +8891,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kin
 sHdlNone\x20(0) eil|L
 0!D)]|
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"LoadStore\",\"max_in_flight\":null},{\"kind\":\"TransformedMove\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) o,/9H
+sPowerISA\x20(0) GQ'Q>
 sHdlNone\x20(0) 8c+O\
 b0 PfE*7
 b0 !}q}3
@@ -8858,6 +8941,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kin
 sHdlNone\x20(0) ^(+@*
 07at%k
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"LoadStore\",\"max_in_flight\":null},{\"kind\":\"TransformedMove\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ^h`~v
+sPowerISA\x20(0) FyT+}
 sHdlNone\x20(0) !Ax^^
 b0 2-?=1
 b0 W@&|q
@@ -8907,6 +8991,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kin
 sHdlNone\x20(0) 65[@U
 0(r:@N
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"LoadStore\",\"max_in_flight\":null},{\"kind\":\"TransformedMove\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) TN{?v
+sPowerISA\x20(0) S'#K&
 sHdlNone\x20(0) ]l$S0
 b0 STXG|
 b0 "#[9T
@@ -8957,6 +9042,7 @@ sHdlNone\x20(0) wO~6L
 0F.k*`
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"LoadStore\",\"max_in_flight\":null},{\"kind\":\"TransformedMove\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ]K$*^
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"LoadStore\",\"max_in_flight\":null},{\"kind\":\"TransformedMove\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) J1Kd=
+sPowerISA\x20(0) B<sY_
 0D<c#n
 b0 e-F>7
 b0 EH[m}
@@ -12313,6 +12399,7 @@ s\"\" SmX4"
 s\"\" y.\2m
 s\"\" n?a24
 s\"\" F8i).
+sPowerISA\x20(0) Q3.G
 sHdlNone\x20(0) [C%Hf
 b0 %RtTH
 b0 8/pV|
@@ -12362,6 +12449,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kin
 sHdlNone\x20(0) u2peT
 0k,__>
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"LoadStore\",\"max_in_flight\":null},{\"kind\":\"TransformedMove\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ^pE+,
+sPowerISA\x20(0) eJlg^
 sHdlNone\x20(0) #"r$8
 b0 EYNKC
 b0 <`a(d
@@ -12413,6 +12501,7 @@ sHdlNone\x20(0) A<iL;
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"LoadStore\",\"max_in_flight\":null},{\"kind\":\"TransformedMove\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ";FVr
 0R_bmG
 1z[UFy
+sPowerISA\x20(0) k/N|/
 sHdlNone\x20(0) iE0UB
 b0 tVnu^
 b0 v4j5$
@@ -12702,6 +12791,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kin
 0[g"k*
 0{Z\hs
 1s7Y>O
+sPowerISA\x20(0) &blD1
 sHdlNone\x20(0) -ayw\
 b0 4a?1B
 b0 #e?g^

crates/cpu/tests/expected/rename_execute_retire_save_restore_gprs.vcd

@@ -683,6 +683,15 @@ $upscope $end
 $upscope $end
 $scope struct to_units $end
 $scope struct u0_AluBranch $end
+$scope struct global_state $end
+$scope struct flags_mode $end
+$var string 1 ^CGEk \$tag $end
+$scope struct PowerISA $end
+$upscope $end
+$scope struct X86 $end
+$upscope $end
+$upscope $end
+$upscope $end
 $scope struct enqueue $end
 $scope struct data $end
 $var string 1 GsdD" \$tag $end
@@ -782,6 +791,15 @@ $upscope $end
 $var string 1 o,/9H config $end
 $upscope $end
 $scope struct u1_AluBranch $end
+$scope struct global_state $end
+$scope struct flags_mode $end
+$var string 1 GQ'Q> \$tag $end
+$scope struct PowerISA $end
+$upscope $end
+$scope struct X86 $end
+$upscope $end
+$upscope $end
+$upscope $end
 $scope struct enqueue $end
 $scope struct data $end
 $var string 1 8c+O\ \$tag $end
@@ -881,6 +899,15 @@ $upscope $end
 $var string 1 ^h`~v config $end
 $upscope $end
 $scope struct u2_LoadStore $end
+$scope struct global_state $end
+$scope struct flags_mode $end
+$var string 1 FyT+} \$tag $end
+$scope struct PowerISA $end
+$upscope $end
+$scope struct X86 $end
+$upscope $end
+$upscope $end
+$upscope $end
 $scope struct enqueue $end
 $scope struct data $end
 $var string 1 !Ax^^ \$tag $end
@@ -980,6 +1007,15 @@ $upscope $end
 $var string 1 TN{?v config $end
 $upscope $end
 $scope struct u3_TransformedMove $end
+$scope struct global_state $end
+$scope struct flags_mode $end
+$var string 1 S'#K& \$tag $end
+$scope struct PowerISA $end
+$upscope $end
+$scope struct X86 $end
+$upscope $end
+$upscope $end
+$upscope $end
 $scope struct enqueue $end
 $scope struct data $end
 $var string 1 ]l$S0 \$tag $end
@@ -1081,6 +1117,15 @@ $upscope $end
 $var string 1 J1Kd= config $end
 $upscope $end
 $scope struct state_for_debug $end
+$scope struct global_state $end
+$scope struct flags_mode $end
+$var string 1 B<sY_ \$tag $end
+$scope struct PowerISA $end
+$upscope $end
+$scope struct X86 $end
+$upscope $end
+$upscope $end
+$upscope $end
 $scope struct rename_delayed $end
 $scope struct elements $end
 $scope struct \[0] $end
@@ -7067,6 +7112,15 @@ $upscope $end
 $upscope $end
 $scope module u0_AluBranch $end
 $scope struct from_execute $end
+$scope struct global_state $end
+$scope struct flags_mode $end
+$var string 1 Q3.G \$tag $end
+$scope struct PowerISA $end
+$upscope $end
+$scope struct X86 $end
+$upscope $end
+$upscope $end
+$upscope $end
 $scope struct enqueue $end
 $scope struct data $end
 $var string 1 [C%Hf \$tag $end
@@ -7168,6 +7222,15 @@ $upscope $end
 $upscope $end
 $scope module u1_AluBranch $end
 $scope struct from_execute $end
+$scope struct global_state $end
+$scope struct flags_mode $end
+$var string 1 eJlg^ \$tag $end
+$scope struct PowerISA $end
+$upscope $end
+$scope struct X86 $end
+$upscope $end
+$upscope $end
+$upscope $end
 $scope struct enqueue $end
 $scope struct data $end
 $var string 1 #"r$8 \$tag $end
@@ -7273,6 +7336,15 @@ $var wire 1 R_bmG clk $end
 $var wire 1 z[UFy rst $end
 $upscope $end
 $scope struct from_execute $end
+$scope struct global_state $end
+$scope struct flags_mode $end
+$var string 1 k/N|/ \$tag $end
+$scope struct PowerISA $end
+$upscope $end
+$scope struct X86 $end
+$upscope $end
+$upscope $end
+$upscope $end
 $scope struct enqueue $end
 $scope struct data $end
 $var string 1 iE0UB \$tag $end
@@ -7716,6 +7788,15 @@ $var wire 1 {Z\hs clk $end
 $var wire 1 s7Y>O rst $end
 $upscope $end
 $scope struct from_execute $end
+$scope struct global_state $end
+$scope struct flags_mode $end
+$var string 1 &blD1 \$tag $end
+$scope struct PowerISA $end
+$upscope $end
+$scope struct X86 $end
+$upscope $end
+$upscope $end
+$upscope $end
 $scope struct enqueue $end
 $scope struct data $end
 $var string 1 -ayw\ \$tag $end
@@ -8760,6 +8841,7 @@ b0 iXLU`
 sAddSub\x20{},\x20rzero,\x20rzero,\x20rzero,\x200x0_i26 `4f=q
 b0 J8qAt
 sPhantomConst(\"0..=20\") %JRz8
+sPowerISA\x20(0) ^CGEk
 sHdlNone\x20(0) GsdD"
 b0 }:QxN
 b0 hh!}]
@@ -8809,6 +8891,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kin
 sHdlNone\x20(0) eil|L
 0!D)]|
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"LoadStore\",\"max_in_flight\":null},{\"kind\":\"TransformedMove\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) o,/9H
+sPowerISA\x20(0) GQ'Q>
 sHdlNone\x20(0) 8c+O\
 b0 PfE*7
 b0 !}q}3
@@ -8858,6 +8941,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kin
 sHdlNone\x20(0) ^(+@*
 07at%k
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"LoadStore\",\"max_in_flight\":null},{\"kind\":\"TransformedMove\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ^h`~v
+sPowerISA\x20(0) FyT+}
 sHdlNone\x20(0) !Ax^^
 b0 2-?=1
 b0 W@&|q
@@ -8907,6 +8991,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kin
 sHdlNone\x20(0) 65[@U
 0(r:@N
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"LoadStore\",\"max_in_flight\":null},{\"kind\":\"TransformedMove\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) TN{?v
+sPowerISA\x20(0) S'#K&
 sHdlNone\x20(0) ]l$S0
 b0 STXG|
 b0 "#[9T
@@ -8957,6 +9042,7 @@ sHdlNone\x20(0) wO~6L
 0F.k*`
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"LoadStore\",\"max_in_flight\":null},{\"kind\":\"TransformedMove\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ]K$*^
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"LoadStore\",\"max_in_flight\":null},{\"kind\":\"TransformedMove\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) J1Kd=
+sPowerISA\x20(0) B<sY_
 0D<c#n
 b0 e-F>7
 b0 EH[m}
@@ -12313,6 +12399,7 @@ s\"\" SmX4"
 s\"\" y.\2m
 s\"\" n?a24
 s\"\" F8i).
+sPowerISA\x20(0) Q3.G
 sHdlNone\x20(0) [C%Hf
 b0 %RtTH
 b0 8/pV|
@@ -12362,6 +12449,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kin
 sHdlNone\x20(0) u2peT
 0k,__>
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"LoadStore\",\"max_in_flight\":null},{\"kind\":\"TransformedMove\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ^pE+,
+sPowerISA\x20(0) eJlg^
 sHdlNone\x20(0) #"r$8
 b0 EYNKC
 b0 <`a(d
@@ -12413,6 +12501,7 @@ sHdlNone\x20(0) A<iL;
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"LoadStore\",\"max_in_flight\":null},{\"kind\":\"TransformedMove\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ";FVr
 0R_bmG
 1z[UFy
+sPowerISA\x20(0) k/N|/
 sHdlNone\x20(0) iE0UB
 b0 tVnu^
 b0 v4j5$
@@ -12702,6 +12791,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kin
 0[g"k*
 0{Z\hs
 1s7Y>O
+sPowerISA\x20(0) &blD1
 sHdlNone\x20(0) -ayw\
 b0 4a?1B
 b0 #e?g^

crates/cpu/tests/expected/rename_execute_retire_slow_loop.vcd

@@ -787,6 +787,15 @@ $upscope $end
 $upscope $end
 $scope struct to_units $end
 $scope struct u0_AluBranch $end
+$scope struct global_state $end
+$scope struct flags_mode $end
+$var string 1 ^CGEk \$tag $end
+$scope struct PowerISA $end
+$upscope $end
+$scope struct X86 $end
+$upscope $end
+$upscope $end
+$upscope $end
 $scope struct enqueue $end
 $scope struct data $end
 $var string 1 GsdD" \$tag $end
@@ -886,6 +895,15 @@ $upscope $end
 $var string 1 o,/9H config $end
 $upscope $end
 $scope struct u1_AluBranch $end
+$scope struct global_state $end
+$scope struct flags_mode $end
+$var string 1 GQ'Q> \$tag $end
+$scope struct PowerISA $end
+$upscope $end
+$scope struct X86 $end
+$upscope $end
+$upscope $end
+$upscope $end
 $scope struct enqueue $end
 $scope struct data $end
 $var string 1 8c+O\ \$tag $end
@@ -985,6 +1003,15 @@ $upscope $end
 $var string 1 ^h`~v config $end
 $upscope $end
 $scope struct u2_AluBranch $end
+$scope struct global_state $end
+$scope struct flags_mode $end
+$var string 1 aRx5V \$tag $end
+$scope struct PowerISA $end
+$upscope $end
+$scope struct X86 $end
+$upscope $end
+$upscope $end
+$upscope $end
 $scope struct enqueue $end
 $scope struct data $end
 $var string 1 2+~8. \$tag $end
@@ -1084,6 +1111,15 @@ $upscope $end
 $var string 1 (xcO& config $end
 $upscope $end
 $scope struct u3_AluBranch $end
+$scope struct global_state $end
+$scope struct flags_mode $end
+$var string 1 c2':P \$tag $end
+$scope struct PowerISA $end
+$upscope $end
+$scope struct X86 $end
+$upscope $end
+$upscope $end
+$upscope $end
 $scope struct enqueue $end
 $scope struct data $end
 $var string 1 cP,km \$tag $end
@@ -1183,6 +1219,15 @@ $upscope $end
 $var string 1 fI2Uk config $end
 $upscope $end
 $scope struct u4_LoadStore $end
+$scope struct global_state $end
+$scope struct flags_mode $end
+$var string 1 reQE) \$tag $end
+$scope struct PowerISA $end
+$upscope $end
+$scope struct X86 $end
+$upscope $end
+$upscope $end
+$upscope $end
 $scope struct enqueue $end
 $scope struct data $end
 $var string 1 o@UX\ \$tag $end
@@ -1282,6 +1327,15 @@ $upscope $end
 $var string 1 Z]?+2 config $end
 $upscope $end
 $scope struct u5_TransformedMove $end
+$scope struct global_state $end
+$scope struct flags_mode $end
+$var string 1 f9$P2 \$tag $end
+$scope struct PowerISA $end
+$upscope $end
+$scope struct X86 $end
+$upscope $end
+$upscope $end
+$upscope $end
 $scope struct enqueue $end
 $scope struct data $end
 $var string 1 `J'BS \$tag $end
@@ -1383,6 +1437,15 @@ $upscope $end
 $var string 1 J1Kd= config $end
 $upscope $end
 $scope struct state_for_debug $end
+$scope struct global_state $end
+$scope struct flags_mode $end
+$var string 1 B<sY_ \$tag $end
+$scope struct PowerISA $end
+$upscope $end
+$scope struct X86 $end
+$upscope $end
+$upscope $end
+$upscope $end
 $scope struct rename_delayed $end
 $scope struct elements $end
 $scope struct \[0] $end
@@ -8003,6 +8066,15 @@ $upscope $end
 $upscope $end
 $scope module u0_AluBranch $end
 $scope struct from_execute $end
+$scope struct global_state $end
+$scope struct flags_mode $end
+$var string 1 Q3.G \$tag $end
+$scope struct PowerISA $end
+$upscope $end
+$scope struct X86 $end
+$upscope $end
+$upscope $end
+$upscope $end
 $scope struct enqueue $end
 $scope struct data $end
 $var string 1 [C%Hf \$tag $end
@@ -8104,6 +8176,15 @@ $upscope $end
 $upscope $end
 $scope module u1_AluBranch $end
 $scope struct from_execute $end
+$scope struct global_state $end
+$scope struct flags_mode $end
+$var string 1 eJlg^ \$tag $end
+$scope struct PowerISA $end
+$upscope $end
+$scope struct X86 $end
+$upscope $end
+$upscope $end
+$upscope $end
 $scope struct enqueue $end
 $scope struct data $end
 $var string 1 #"r$8 \$tag $end
@@ -8205,6 +8286,15 @@ $upscope $end
 $upscope $end
 $scope module u2_AluBranch $end
 $scope struct from_execute $end
+$scope struct global_state $end
+$scope struct flags_mode $end
+$var string 1 GN@do \$tag $end
+$scope struct PowerISA $end
+$upscope $end
+$scope struct X86 $end
+$upscope $end
+$upscope $end
+$upscope $end
 $scope struct enqueue $end
 $scope struct data $end
 $var string 1 EP<U| \$tag $end
@@ -8306,6 +8396,15 @@ $upscope $end
 $upscope $end
 $scope module u3_AluBranch $end
 $scope struct from_execute $end
+$scope struct global_state $end
+$scope struct flags_mode $end
+$var string 1 nxV=B \$tag $end
+$scope struct PowerISA $end
+$upscope $end
+$scope struct X86 $end
+$upscope $end
+$upscope $end
+$upscope $end
 $scope struct enqueue $end
 $scope struct data $end
 $var string 1 l%cO, \$tag $end
@@ -8411,6 +8510,15 @@ $var wire 1 _J$'t clk $end
 $var wire 1 R~h'* rst $end
 $upscope $end
 $scope struct from_execute $end
+$scope struct global_state $end
+$scope struct flags_mode $end
+$var string 1 n8>ag \$tag $end
+$scope struct PowerISA $end
+$upscope $end
+$scope struct X86 $end
+$upscope $end
+$upscope $end
+$upscope $end
 $scope struct enqueue $end
 $scope struct data $end
 $var string 1 M!ed- \$tag $end
@@ -8854,6 +8962,15 @@ $var wire 1 LSE8M clk $end
 $var wire 1 `D6%M rst $end
 $upscope $end
 $scope struct from_execute $end
+$scope struct global_state $end
+$scope struct flags_mode $end
+$var string 1 orJ,: \$tag $end
+$scope struct PowerISA $end
+$upscope $end
+$scope struct X86 $end
+$upscope $end
+$upscope $end
+$upscope $end
 $scope struct enqueue $end
 $scope struct data $end
 $var string 1 zw>>/ \$tag $end
@@ -9966,6 +10083,7 @@ b0 iXLU`
 sAddSub\x20{},\x20rzero,\x20rzero,\x20rzero,\x200x0_i26 `4f=q
 b0 J8qAt
 sPhantomConst(\"0..=20\") %JRz8
+sPowerISA\x20(0) ^CGEk
 sHdlNone\x20(0) GsdD"
 b0 }:QxN
 b0 hh!}]
@@ -10015,6 +10133,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kin
 sHdlNone\x20(0) eil|L
 0!D)]|
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"LoadStore\",\"max_in_flight\":null},{\"kind\":\"TransformedMove\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":4,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) o,/9H
+sPowerISA\x20(0) GQ'Q>
 sHdlNone\x20(0) 8c+O\
 b0 PfE*7
 b0 !}q}3
@@ -10064,6 +10183,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kin
 sHdlNone\x20(0) ^(+@*
 07at%k
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"LoadStore\",\"max_in_flight\":null},{\"kind\":\"TransformedMove\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":4,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ^h`~v
+sPowerISA\x20(0) aRx5V
 sHdlNone\x20(0) 2+~8.
 b0 e.>!d
 b0 Pf4v-
@@ -10113,6 +10233,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kin
 sHdlNone\x20(0) FM/L}
 0]G2vi
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"LoadStore\",\"max_in_flight\":null},{\"kind\":\"TransformedMove\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":4,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) (xcO&
+sPowerISA\x20(0) c2':P
 sHdlNone\x20(0) cP,km
 b0 J\[T&
 b0 V-Ie/
@@ -10162,6 +10283,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kin
 sHdlNone\x20(0) 7R/2&
 0JTX?x
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"LoadStore\",\"max_in_flight\":null},{\"kind\":\"TransformedMove\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":4,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) fI2Uk
+sPowerISA\x20(0) reQE)
 sHdlNone\x20(0) o@UX\
 b0 k>VXD
 b0 bG:p6
@@ -10211,6 +10333,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kin
 sHdlNone\x20(0) hUQI@
 03h{q/
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"LoadStore\",\"max_in_flight\":null},{\"kind\":\"TransformedMove\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":4,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) Z]?+2
+sPowerISA\x20(0) f9$P2
 sHdlNone\x20(0) `J'BS
 b0 #Umg$
 b0 u*l#&
@@ -10261,6 +10384,7 @@ sHdlNone\x20(0) k2SS&
 0?Qs3<
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"LoadStore\",\"max_in_flight\":null},{\"kind\":\"TransformedMove\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":4,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) +>o)1
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"LoadStore\",\"max_in_flight\":null},{\"kind\":\"TransformedMove\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":4,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) J1Kd=
+sPowerISA\x20(0) B<sY_
 0D<c#n
 b0 e-F>7
 b0 EH[m}
@@ -13931,6 +14055,7 @@ s\"\" SmX4"
 s\"\" y.\2m
 s\"\" n?a24
 s\"\" F8i).
+sPowerISA\x20(0) Q3.G
 sHdlNone\x20(0) [C%Hf
 b0 %RtTH
 b0 8/pV|
@@ -13980,6 +14105,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kin
 sHdlNone\x20(0) u2peT
 0k,__>
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"LoadStore\",\"max_in_flight\":null},{\"kind\":\"TransformedMove\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":4,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ^pE+,
+sPowerISA\x20(0) eJlg^
 sHdlNone\x20(0) #"r$8
 b0 EYNKC
 b0 <`a(d
@@ -14029,6 +14155,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kin
 sHdlNone\x20(0) A<iL;
 0{bf:`
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"LoadStore\",\"max_in_flight\":null},{\"kind\":\"TransformedMove\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":4,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ";FVr
+sPowerISA\x20(0) GN@do
 sHdlNone\x20(0) EP<U|
 b0 /,qQx
 b0 g:=mM
@@ -14078,6 +14205,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kin
 sHdlNone\x20(0) rWrQI
 0C>S:u
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"LoadStore\",\"max_in_flight\":null},{\"kind\":\"TransformedMove\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":4,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) p4_Ao
+sPowerISA\x20(0) nxV=B
 sHdlNone\x20(0) l%cO,
 b0 A[D[<
 b0 OOnkQ
@@ -14129,6 +14257,7 @@ sHdlNone\x20(0) 1WX"Q
 sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"LoadStore\",\"max_in_flight\":null},{\"kind\":\"TransformedMove\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":4,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":6,\"log2_l1_i_cache_line_count\":8,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) [@u4X
 0_J$'t
 1R~h'*
+sPowerISA\x20(0) n8>ag
 sHdlNone\x20(0) M!ed-
 b0 %G+MX
 b0 o!Zx.
@@ -14418,6 +14547,7 @@ sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kin
 0yhGZ]
 0LSE8M
 1`D6%M
+sPowerISA\x20(0) orJ,:
 sHdlNone\x20(0) zw>>/
 b0 ?k~wf
 b0 -ev;7

crates/cpu/tests/rename_execute_retire.rs

@@ -2,6 +2,7 @@
 // See Notices.txt for copyright information
 
 use cpu::{
+    checked_vcd_output,
     config::{
         CpuConfig, CpuConfigFetchWidth, CpuConfigMaxUnitMaxInFlight, PhantomConstCpuConfig,
         UnitConfig,
@@ -15,13 +16,13 @@ use cpu::{
         ShiftRotateMode, StoreMOp, UnitNum, WriteL2RegMOp,
     },
     next_pc::CallStackOp,
-    register::{PRegFlags, PRegFlagsPowerISA, PRegValue},
+    register::{FlagsMode, PRegFlags, PRegFlagsPowerISA, PRegValue},
     rename_execute_retire::{
-        ExecuteToUnitInterface, MOpId, MOpInstance, NextPcPredictorOp, PostDecodeOutputInterface,
+        ExecuteToUnitInterface, GlobalState, MOpId, MOpInstance, NextPcPredictorOp,
-        RenamedMOp, RetireToNextPcInterface, RetireToNextPcInterfaceInner, UnitCausedCancel,
+        PostDecodeOutputInterface, RenamedMOp, RetireToNextPcInterface,
-        UnitEnqueue, UnitFinishCauseCancel, UnitInputsReady, UnitMOpCantCauseCancel,
+        RetireToNextPcInterfaceInner, UnitCausedCancel, UnitEnqueue, UnitFinishCauseCancel,
-        UnitMOpIsNoLongerSpeculative, UnitOutputReady, rename_execute_retire,
+        UnitInputsReady, UnitMOpCantCauseCancel, UnitMOpIsNoLongerSpeculative, UnitOutputReady,
-        to_unit_interfaces::ExecuteToUnitInterfaces,
+        rename_execute_retire, to_unit_interfaces::ExecuteToUnitInterfaces,
     },
     unit::{UnitKind, UnitMOp},
     util::array_vec::ArrayVec,
@@ -30,9 +31,7 @@ use fayalite::{
     bundle::BundleType,
     module::instance_with_loc,
     prelude::*,
-    sim::vcd::VcdWriterDecls,
     ty::{OpaqueSimValue, StaticType},
-    util::RcWriter,
 };
 use serde::{Deserialize, Serialize};
 use std::{
@@ -1665,10 +1664,18 @@ trait MockExecutionStateTrait: Default {
     #[hdl]
     fn run_add_sub<C: PhantomConstCpuConfig, SrcCount: KnownSize>(
         &mut self,
+        global_state: &SimValue<GlobalState>,
         pc: u64,
         mop: &SimValue<AddSubMOp<PRegNum<C>, PRegNum<C>, SrcCount>>,
         src_values: &[SimValue<TraceAsString<PRegValue>>; COMMON_MOP_SRC_LEN],
     ) -> SimValue<TraceAsString<PRegValue>> {
+        #[hdl(sim)]
+        let GlobalState { flags_mode } = global_state;
+        #[hdl(sim)]
+        match flags_mode {
+            FlagsMode::PowerISA(_) => {}
+            _ => todo!("flags_mode={flags_mode:?}"),
+        }
         #[hdl(sim)]
         let AddSubMOp::<_, _, _> {
             alu_common,
@@ -1732,9 +1739,17 @@ trait MockExecutionStateTrait: Default {
     #[hdl]
     fn run_compare<C: PhantomConstCpuConfig, SrcCount: KnownSize>(
         &mut self,
+        global_state: &SimValue<GlobalState>,
         mop: &SimValue<CompareMOp<PRegNum<C>, PRegNum<C>, SrcCount>>,
         src_values: &[SimValue<TraceAsString<PRegValue>>; COMMON_MOP_SRC_LEN],
     ) -> SimValue<TraceAsString<PRegValue>> {
+        #[hdl(sim)]
+        let GlobalState { flags_mode } = global_state;
+        #[hdl(sim)]
+        match flags_mode {
+            FlagsMode::PowerISA(_) => {}
+            _ => todo!("flags_mode={flags_mode:?}"),
+        }
         #[hdl(sim)]
         let CompareMOp::<_, _, _> {
             common,
@@ -1791,9 +1806,17 @@ trait MockExecutionStateTrait: Default {
     #[hdl]
     fn run_shift_rotate<C: PhantomConstCpuConfig>(
         &mut self,
+        global_state: &SimValue<GlobalState>,
         mop: &SimValue<ShiftRotateMOp<PRegNum<C>, PRegNum<C>>>,
         src_values: &[SimValue<TraceAsString<PRegValue>>; COMMON_MOP_SRC_LEN],
     ) -> SimValue<TraceAsString<PRegValue>> {
+        #[hdl(sim)]
+        let GlobalState { flags_mode } = global_state;
+        #[hdl(sim)]
+        match flags_mode {
+            FlagsMode::PowerISA(_) => {}
+            _ => todo!("flags_mode={flags_mode:?}"),
+        }
         #[hdl(sim)]
         let ShiftRotateMOp::<_, _> { alu_common, mode } = mop;
         #[hdl(sim)]
@@ -1973,7 +1996,7 @@ trait MockExecutionStateTrait: Default {
     #[hdl]
     fn run_branch<C: PhantomConstCpuConfig, SrcCount: KnownSize>(
         &mut self,
-        id: &SimValue<MOpId>,
+        global_state: &SimValue<GlobalState>,
         pc: u64,
         fallthrough_pc: u64,
         predicted_next_pc: u64,
@@ -1985,6 +2008,13 @@ trait MockExecutionStateTrait: Default {
         SimValue<NextPcPredictorOp<C>>,
         Option<SimValue<UnitCausedCancel<C>>>,
     ) {
+        #[hdl(sim)]
+        let GlobalState { flags_mode } = global_state;
+        #[hdl(sim)]
+        match flags_mode {
+            FlagsMode::PowerISA(_) => {}
+            _ => todo!("flags_mode={flags_mode:?}"),
+        }
         #[hdl(sim)]
         let BranchMOp::<_, _, _> {
             common,
@@ -2093,6 +2123,7 @@ trait MockExecutionStateTrait: Default {
     #[hdl]
     fn run_mop<C: PhantomConstCpuConfig>(
         &mut self,
+        global_state: &SimValue<GlobalState>,
         mop: &SimValue<MOpInstance<RenamedMOp<C>>>,
         src_values: &[SimValue<TraceAsString<PRegValue>>; COMMON_MOP_SRC_LEN],
         config: C,
@@ -2106,7 +2137,7 @@ trait MockExecutionStateTrait: Default {
         #[hdl(sim)]
         let MOpInstance::<_> {
             fetch_block_id: _,
-            id,
+            id: _,
             pc,
             predicted_next_pc,
             size_in_bytes,
@@ -2135,14 +2166,14 @@ trait MockExecutionStateTrait: Default {
                 match mop {
                     AluBranchMOp::<_, _>::AddSub(mop) => (
                         Some((
-                            self.run_add_sub(pc.as_int(), mop, src_values),
+                            self.run_add_sub(global_state, pc.as_int(), mop, src_values),
                             empty_predictor_op(),
                         )),
                         None,
                     ),
                     AluBranchMOp::<_, _>::AddSubI(mop) => (
                         Some((
-                            self.run_add_sub(pc.as_int(), mop, src_values),
+                            self.run_add_sub(global_state, pc.as_int(), mop, src_values),
                             empty_predictor_op(),
                         )),
                         None,
@@ -2157,20 +2188,29 @@ trait MockExecutionStateTrait: Default {
                         todo!("implement LogicalI")
                     }
                     AluBranchMOp::<_, _>::ShiftRotate(mop) => (
-                        Some((self.run_shift_rotate(mop, src_values), empty_predictor_op())),
+                        Some((
+                            self.run_shift_rotate(global_state, mop, src_values),
+                            empty_predictor_op(),
+                        )),
                         None,
                     ),
                     AluBranchMOp::<_, _>::Compare(mop) => (
-                        Some((self.run_compare(mop, src_values), empty_predictor_op())),
+                        Some((
+                            self.run_compare(global_state, mop, src_values),
+                            empty_predictor_op(),
+                        )),
                         None,
                     ),
                     AluBranchMOp::<_, _>::CompareI(mop) => (
-                        Some((self.run_compare(mop, src_values), empty_predictor_op())),
+                        Some((
+                            self.run_compare(global_state, mop, src_values),
+                            empty_predictor_op(),
+                        )),
                         None,
                     ),
                     AluBranchMOp::<_, _>::Branch(mop) => {
                         let (value, predictor_op, cancel) = self.run_branch(
-                            id,
+                            global_state,
                             pc.as_int(),
                             fallthrough_pc,
                             predicted_next_pc.as_int(),
@@ -2182,7 +2222,7 @@ trait MockExecutionStateTrait: Default {
                     }
                     AluBranchMOp::<_, _>::BranchI(mop) => {
                         let (value, predictor_op, cancel) = self.run_branch(
-                            id,
+                            global_state,
                             pc.as_int(),
                             fallthrough_pc,
                             predicted_next_pc.as_int(),
@@ -2270,12 +2310,16 @@ impl<C: PhantomConstCpuConfig> MockUnitOp<C> {
         }
     }
     #[hdl]
-    fn try_run<E: MockExecutionStateTrait>(&mut self, execution_state: &mut E) {
+    fn try_run<E: MockExecutionStateTrait>(
+        &mut self,
+        global_state: &SimValue<GlobalState>,
+        execution_state: &mut E,
+    ) {
         if self.output_ready.is_some() || self.caused_cancel.is_some() {
             return;
         }
         let (output, caused_cancel) =
-            execution_state.run_mop(&self.mop, &self.src_values, self.config);
+            execution_state.run_mop(global_state, &self.mop, &self.src_values, self.config);
         assert!(output.is_some() || caused_cancel.is_some());
         println!("try_run: {:#x}: {:?}", self.mop.pc.as_int(), self.mop.mop);
         println!("<- {:?}", self.src_values);
@@ -2318,6 +2362,7 @@ impl<C: PhantomConstCpuConfig> MockUnitOp<C> {
 
 #[hdl(no_static)]
 struct MockUnitDebugState<C: PhantomConstGet<CpuConfig>, E> {
+    global_state: GlobalState,
     ops: ArrayVec<MockUnitOpDebugState<C>, CpuConfigMaxUnitMaxInFlight<C>>,
     execution_state: E,
     config: C,
@@ -2325,6 +2370,7 @@ struct MockUnitDebugState<C: PhantomConstGet<CpuConfig>, E> {
 
 #[derive(Debug)]
 struct MockUnitState<C: PhantomConstCpuConfig, E> {
+    global_state: SimValue<GlobalState>,
     ops: BTreeMap<SimValue<MOpId>, MockUnitOp<C>>,
     execution_state: E,
     config: C,
@@ -2332,8 +2378,14 @@ struct MockUnitState<C: PhantomConstCpuConfig, E> {
 }
 
 impl<C: PhantomConstCpuConfig, E: MockExecutionStateTrait> MockUnitState<C, E> {
-    fn new(execution_state: E, config: C, unit_index: usize) -> Self {
+    fn new(
+        global_state: SimValue<GlobalState>,
+        execution_state: E,
+        config: C,
+        unit_index: usize,
+    ) -> Self {
         Self {
+            global_state,
             ops: BTreeMap::new(),
             execution_state,
             config,
@@ -2343,6 +2395,7 @@ impl<C: PhantomConstCpuConfig, E: MockExecutionStateTrait> MockUnitState<C, E> {
     #[hdl]
     fn debug_state(&self) -> SimValue<MockUnitDebugState<C, E::DebugState>> {
         let Self {
+            global_state,
             ops,
             execution_state,
             config,
@@ -2352,6 +2405,7 @@ impl<C: PhantomConstCpuConfig, E: MockExecutionStateTrait> MockUnitState<C, E> {
         let ret_ty = MockUnitDebugState[*config][execution_state.ty()];
         #[hdl(sim)]
         MockUnitDebugState::<_, _> {
+            global_state,
             ops: ret_ty
                 .ops
                 .from_iter_sim(
@@ -2459,7 +2513,7 @@ impl<C: PhantomConstCpuConfig, E: MockExecutionStateTrait> MockUnitState<C, E> {
             caused_cancel: None,
             config: self.config,
         };
-        op.try_run(&mut self.execution_state);
+        op.try_run(&self.global_state, &mut self.execution_state);
         self.ops.insert(op.mop.id.clone(), op);
     }
     #[hdl]
@@ -2470,6 +2524,7 @@ impl<C: PhantomConstCpuConfig, E: MockExecutionStateTrait> MockUnitState<C, E> {
     }
     fn cancel_all(&mut self) {
         let Self {
+            global_state: _,
             ops,
             execution_state: _,
             config: _,
@@ -2503,6 +2558,7 @@ fn mock_unit<#[hdl(skip)] E: MockExecutionStateTrait>(
                 async |mut sim| {
                     #[hdl]
                     let ExecuteToUnitInterface::<_> {
+                        global_state: _,
                         enqueue,
                         inputs_ready: _,
                         is_no_longer_speculative: _,
@@ -2537,6 +2593,7 @@ fn mock_unit<#[hdl(skip)] E: MockExecutionStateTrait>(
                         debug_state,
                         #[hdl(sim)]
                         MockUnitDebugState::<_, _> {
+                            global_state: zeroed(GlobalState),
                             ops: zeroed(debug_state.ty().ops),
                             execution_state: SimValue::into_bundle(E::zeroed_debug_state()),
                             config,
@@ -2569,11 +2626,17 @@ fn mock_unit<#[hdl(skip)] E: MockExecutionStateTrait>(
         unit_index: usize,
         mut sim: ExternModuleSimulationState,
     ) {
-        let mut state = MockUnitState::new(execution_state, config, unit_index);
+        let mut state = MockUnitState::new(
+            sim.read(from_execute.global_state).await,
+            execution_state,
+            config,
+            unit_index,
+        );
         loop {
             {
                 #[hdl]
                 let ExecuteToUnitInterface::<_> {
+                    global_state: _,
                     enqueue,
                     inputs_ready: _,
                     is_no_longer_speculative: _,
@@ -2599,6 +2662,7 @@ fn mock_unit<#[hdl(skip)] E: MockExecutionStateTrait>(
             {
                 #[hdl]
                 let ExecuteToUnitInterface::<_> {
+                    global_state,
                     enqueue: _, // we ignore enqueues since we don't need to track order for these instructions
                     inputs_ready,
                     is_no_longer_speculative,
@@ -2609,6 +2673,7 @@ fn mock_unit<#[hdl(skip)] E: MockExecutionStateTrait>(
                     cancel_all,
                     config: _,
                 } = from_execute;
+                state.global_state = sim.read_past(global_state, cd.clk).await;
                 #[hdl(sim)]
                 if let HdlSome(inputs_ready) = sim.read_past(inputs_ready, cd.clk).await {
                     state.handle_inputs_ready(inputs_ready);
@@ -2665,6 +2730,7 @@ fn mock_combinational_unit<#[hdl(skip)] E: MockExecutionStateTrait>(
         let (from_execute, config, unit_index) = args;
         #[hdl]
         let ExecuteToUnitInterface::<_> {
+            global_state: _,
             enqueue,
             inputs_ready: _,
             is_no_longer_speculative: _,
@@ -2708,6 +2774,7 @@ fn mock_combinational_unit<#[hdl(skip)] E: MockExecutionStateTrait>(
         loop {
             #[hdl]
             let ExecuteToUnitInterface::<_> {
+                global_state,
                 enqueue,
                 inputs_ready,
                 is_no_longer_speculative: _, // we don't care about being speculative for these instructions
@@ -2719,7 +2786,8 @@ fn mock_combinational_unit<#[hdl(skip)] E: MockExecutionStateTrait>(
                 config: _,
             } = from_execute;
             sim.write(enqueue.ready, true).await; // we ignore enqueues since we don't need to track order for these instructions
-            let mut state = MockUnitState::new(E::default(), config, unit_index);
+            let global_state = sim.read(global_state).await;
+            let mut state = MockUnitState::new(global_state, E::default(), config, unit_index);
             #[hdl(sim)]
             if let HdlSome(inputs_ready) = sim.read(inputs_ready).await {
                 state.handle_inputs_ready(inputs_ready);
@@ -3142,6 +3210,7 @@ fn mock_l2_reg_file_unit(config: PhantomConst<CpuConfig>, unit_index: usize) {
                 async |mut sim| {
                     #[hdl]
                     let ExecuteToUnitInterface::<_> {
+                        global_state: _,
                         enqueue,
                         inputs_ready: _,
                         is_no_longer_speculative: _,
@@ -3203,6 +3272,7 @@ fn mock_l2_reg_file_unit(config: PhantomConst<CpuConfig>, unit_index: usize) {
             {
                 #[hdl]
                 let ExecuteToUnitInterface::<_> {
+                    global_state: _,
                     enqueue,
                     inputs_ready: _,
                     is_no_longer_speculative: _,
@@ -3226,6 +3296,7 @@ fn mock_l2_reg_file_unit(config: PhantomConst<CpuConfig>, unit_index: usize) {
             {
                 #[hdl]
                 let ExecuteToUnitInterface::<_> {
+                    global_state: _,
                     enqueue,
                     inputs_ready,
                     is_no_longer_speculative,
@@ -3822,6 +3893,7 @@ fn mock_load_store_unit<#[hdl(skip)] MI: MakeInsns>(
                 async |mut sim| {
                     #[hdl]
                     let ExecuteToUnitInterface::<_> {
+                        global_state: _,
                         enqueue,
                         inputs_ready: _,
                         is_no_longer_speculative: _,
@@ -3901,6 +3973,7 @@ fn mock_load_store_unit<#[hdl(skip)] MI: MakeInsns>(
             {
                 #[hdl]
                 let ExecuteToUnitInterface::<_> {
+                    global_state: _,
                     enqueue,
                     inputs_ready: _,
                     is_no_longer_speculative: _,
@@ -3926,6 +3999,7 @@ fn mock_load_store_unit<#[hdl(skip)] MI: MakeInsns>(
             {
                 #[hdl]
                 let ExecuteToUnitInterface::<_> {
+                    global_state: _,
                     enqueue,
                     inputs_ready,
                     is_no_longer_speculative,
@@ -3983,10 +4057,16 @@ fn mock_load_store_unit<#[hdl(skip)] MI: MakeInsns>(
     }
 }
 
+enum AluBranchKind {
+    MockUnit,
+    MockCombinationalUnit,
+    Real,
+}
+
 #[hdl_module]
 fn rename_execute_retire_test_harness<#[hdl(skip)] MI: MakeInsns>(
     config: PhantomConst<CpuConfig>,
-    alu_branch_is_combinatorial: bool,
+    alu_branch_kind: AluBranchKind,
 ) {
     #[hdl]
     let cd: ClockDomain = m.input();
@@ -4032,15 +4112,16 @@ fn rename_execute_retire_test_harness<#[hdl(skip)] MI: MakeInsns>(
                 connect(mock_unit.from_execute, to_unit);
                 connect(started_any_l2_reg_file_ops, mock_unit.started_any);
             }
-            UnitKind::AluBranch => {
+            UnitKind::AluBranch => match alu_branch_kind {
-                if alu_branch_is_combinatorial {
+                AluBranchKind::MockCombinationalUnit => {
                     let mock_unit = instance_with_loc(
                         &dut.ty().to_units.unit_field_name(unit_index),
                         mock_combinational_unit::<()>(config, unit_index),
                         SourceLocation::caller(),
                     );
                     connect(mock_unit.from_execute, to_unit);
-                } else {
+                }
+                AluBranchKind::MockUnit => {
                     let mock_unit = instance_with_loc(
                         &dut.ty().to_units.unit_field_name(unit_index),
                         mock_unit::<()>(config, unit_index),
@@ -4049,7 +4130,15 @@ fn rename_execute_retire_test_harness<#[hdl(skip)] MI: MakeInsns>(
                     connect(mock_unit.cd, cd);
                     connect(mock_unit.from_execute, to_unit);
                 }
+                AluBranchKind::Real => {
+                    let unit = instance_with_loc(
+                        &dut.ty().to_units.unit_field_name(unit_index),
+                        cpu::unit::alu_branch::alu_branch(config, unit_index),
+                        SourceLocation::caller(),
+                    );
+                    connect(unit.from_execute, to_unit);
                 }
+            },
         }
     }
 }
@@ -4124,25 +4213,13 @@ fn test_rename_execute_retire_fibonacci_non_combinatorial() {
     config.fetch_width = NonZeroUsize::new(3).unwrap();
     let m = rename_execute_retire_test_harness::<FibonacciInsns>(
         PhantomConst::new_sized(config),
-        false,
+        AluBranchKind::MockUnit,
     );
     let mut sim = Simulation::new(m);
-    let writer = RcWriter::default();
+    let _checked_vcd_output = checked_vcd_output!(
-    sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
+        &mut sim,
-    struct DumpVcdOnDrop {
+        "tests/expected/rename_execute_retire_fibonacci_non_combinatorial.vcd",
-        writer: Option<RcWriter>,
+    );
-    }
-    impl Drop for DumpVcdOnDrop {
-        fn drop(&mut self) {
-            if let Some(mut writer) = self.writer.take() {
-                let vcd = String::from_utf8(writer.take()).unwrap();
-                println!("####### VCD:\n{vcd}\n#######");
-            }
-        }
-    }
-    let mut writer = DumpVcdOnDrop {
-        writer: Some(writer),
-    };
     sim.write_clock(sim.io().cd.clk, false);
     sim.write_reset(sim.io().cd.rst, true);
     for cycle in 0..200 {
@@ -4154,12 +4231,6 @@ fn test_rename_execute_retire_fibonacci_non_combinatorial() {
         sim.write_reset(sim.io().cd.rst, false);
     }
     assert!(sim.read_bool(sim.io().all_outputs_written));
-    // FIXME: vcd is just whatever rename_execute_retire does now, which isn't known to be correct
-    let vcd = String::from_utf8(writer.writer.take().unwrap().take()).unwrap();
-    println!("####### VCD:\n{vcd}\n#######");
-    if vcd != include_str!("expected/rename_execute_retire_fibonacci_non_combinatorial.vcd") {
-        panic!();
-    }
 }
 
 #[hdl]
@@ -4177,25 +4248,15 @@ fn test_rename_execute_retire_fibonacci_combinatorial() {
         NonZeroUsize::new(20).unwrap(),
     );
     config.fetch_width = NonZeroUsize::new(3).unwrap();
-    let m =
+    let m = rename_execute_retire_test_harness::<FibonacciInsns>(
-        rename_execute_retire_test_harness::<FibonacciInsns>(PhantomConst::new_sized(config), true);
+        PhantomConst::new_sized(config),
+        AluBranchKind::MockCombinationalUnit,
+    );
     let mut sim = Simulation::new(m);
-    let writer = RcWriter::default();
+    let _checked_vcd_output = checked_vcd_output!(
-    sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
+        &mut sim,
-    struct DumpVcdOnDrop {
+        "tests/expected/rename_execute_retire_fibonacci_combinatorial.vcd",
-        writer: Option<RcWriter>,
+    );
-    }
-    impl Drop for DumpVcdOnDrop {
-        fn drop(&mut self) {
-            if let Some(mut writer) = self.writer.take() {
-                let vcd = String::from_utf8(writer.take()).unwrap();
-                println!("####### VCD:\n{vcd}\n#######");
-            }
-        }
-    }
-    let mut writer = DumpVcdOnDrop {
-        writer: Some(writer),
-    };
     sim.write_clock(sim.io().cd.clk, false);
     sim.write_reset(sim.io().cd.rst, true);
     for cycle in 0..200 {
@@ -4207,12 +4268,6 @@ fn test_rename_execute_retire_fibonacci_combinatorial() {
         sim.write_reset(sim.io().cd.rst, false);
     }
     assert!(sim.read_bool(sim.io().all_outputs_written));
-    // FIXME: vcd is just whatever rename_execute_retire does now, which isn't known to be correct
-    let vcd = String::from_utf8(writer.writer.take().unwrap().take()).unwrap();
-    println!("####### VCD:\n{vcd}\n#######");
-    if vcd != include_str!("expected/rename_execute_retire_fibonacci_combinatorial.vcd") {
-        panic!();
-    }
 }
 
 struct SlowLoopInsns;
@@ -4310,25 +4365,15 @@ fn test_rename_execute_retire_slow_loop() {
         NonZeroUsize::new(20).unwrap(),
     );
     config.fetch_width = NonZeroUsize::new(4).unwrap();
-    let m =
+    let m = rename_execute_retire_test_harness::<SlowLoopInsns>(
-        rename_execute_retire_test_harness::<SlowLoopInsns>(PhantomConst::new_sized(config), true);
+        PhantomConst::new_sized(config),
+        AluBranchKind::MockCombinationalUnit,
+    );
     let mut sim = Simulation::new(m);
-    let writer = RcWriter::default();
+    let _checked_vcd_output = checked_vcd_output!(
-    sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
+        &mut sim,
-    struct DumpVcdOnDrop {
+        "tests/expected/rename_execute_retire_slow_loop.vcd",
-        writer: Option<RcWriter>,
+    );
-    }
-    impl Drop for DumpVcdOnDrop {
-        fn drop(&mut self) {
-            if let Some(mut writer) = self.writer.take() {
-                let vcd = String::from_utf8(writer.take()).unwrap();
-                println!("####### VCD:\n{vcd}\n#######");
-            }
-        }
-    }
-    let mut writer = DumpVcdOnDrop {
-        writer: Some(writer),
-    };
     sim.write_clock(sim.io().cd.clk, false);
     sim.write_reset(sim.io().cd.rst, true);
     for cycle in 0..350 {
@@ -4342,12 +4387,6 @@ fn test_rename_execute_retire_slow_loop() {
     assert!(sim.read_bool(sim.io().all_outputs_written));
     // make sure we're actually testing L2 reg file ops
     assert!(sim.read_bool(sim.io().started_any_l2_reg_file_ops));
-    // FIXME: vcd is just whatever rename_execute_retire does now, which isn't known to be correct
-    let vcd = String::from_utf8(writer.writer.take().unwrap().take()).unwrap();
-    println!("####### VCD:\n{vcd}\n#######");
-    if vcd != include_str!("expected/rename_execute_retire_slow_loop.vcd") {
-        panic!();
-    }
 }
 
 /// equivalent of Unix's `head -n1`
@@ -4449,25 +4488,13 @@ fn test_rename_execute_retire_head_n1() {
         NonZeroUsize::new(20).unwrap(),
     );
     config.fetch_width = NonZeroUsize::new(2).unwrap();
-    let m =
+    let m = rename_execute_retire_test_harness::<HeadN1Insns>(
-        rename_execute_retire_test_harness::<HeadN1Insns>(PhantomConst::new_sized(config), true);
+        PhantomConst::new_sized(config),
+        AluBranchKind::MockCombinationalUnit,
+    );
     let mut sim = Simulation::new(m);
-    let writer = RcWriter::default();
+    let _checked_vcd_output =
-    sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
+        checked_vcd_output!(&mut sim, "tests/expected/rename_execute_retire_head_n1.vcd");
-    struct DumpVcdOnDrop {
-        writer: Option<RcWriter>,
-    }
-    impl Drop for DumpVcdOnDrop {
-        fn drop(&mut self) {
-            if let Some(mut writer) = self.writer.take() {
-                let vcd = String::from_utf8(writer.take()).unwrap();
-                println!("####### VCD:\n{vcd}\n#######");
-            }
-        }
-    }
-    let mut writer = DumpVcdOnDrop {
-        writer: Some(writer),
-    };
     sim.write_clock(sim.io().cd.clk, false);
     sim.write_reset(sim.io().cd.rst, true);
     for cycle in 0..300 {
@@ -4479,12 +4506,6 @@ fn test_rename_execute_retire_head_n1() {
         sim.write_reset(sim.io().cd.rst, false);
     }
     assert!(sim.read_bool(sim.io().all_outputs_written));
-    // FIXME: vcd is just whatever rename_execute_retire does now, which isn't known to be correct
-    let vcd = String::from_utf8(writer.writer.take().unwrap().take()).unwrap();
-    println!("####### VCD:\n{vcd}\n#######");
-    if vcd != include_str!("expected/rename_execute_retire_head_n1.vcd") {
-        panic!();
-    }
 }
 
 struct SaveRestoreGprsInsns;
@@ -4566,25 +4587,49 @@ fn test_rename_execute_retire_save_restore_gprs() {
     config.fetch_width = NonZeroUsize::new(2).unwrap();
     let m = rename_execute_retire_test_harness::<SaveRestoreGprsInsns>(
         PhantomConst::new_sized(config),
-        true,
+        AluBranchKind::MockCombinationalUnit,
     );
     let mut sim = Simulation::new(m);
-    let writer = RcWriter::default();
+    let _checked_vcd_output = checked_vcd_output!(
-    sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
+        &mut sim,
-    struct DumpVcdOnDrop {
+        "tests/expected/rename_execute_retire_save_restore_gprs.vcd",
-        writer: Option<RcWriter>,
+    );
-    }
+    sim.write_clock(sim.io().cd.clk, false);
-    impl Drop for DumpVcdOnDrop {
+    sim.write_reset(sim.io().cd.rst, true);
-        fn drop(&mut self) {
+    for cycle in 0..700 {
-            if let Some(mut writer) = self.writer.take() {
+        sim.advance_time(SimDuration::from_nanos(500));
-                let vcd = String::from_utf8(writer.take()).unwrap();
+        println!("clock tick: {cycle}");
-                println!("####### VCD:\n{vcd}\n#######");
+        sim.write_clock(sim.io().cd.clk, true);
-            }
+        sim.advance_time(SimDuration::from_nanos(500));
-        }
+        sim.write_clock(sim.io().cd.clk, false);
-    }
+        sim.write_reset(sim.io().cd.rst, false);
-    let mut writer = DumpVcdOnDrop {
+    }
-        writer: Some(writer),
+    assert!(sim.read_bool(sim.io().all_outputs_written));
-    };
+}
+
+#[hdl]
+#[test]
+fn test_rename_execute_retire_real_alu_branch() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let mut config = CpuConfig::new(
+        vec![
+            UnitConfig::new(UnitKind::AluBranch),
+            UnitConfig::new(UnitKind::AluBranch),
+            UnitConfig::new(UnitKind::LoadStore),
+            UnitConfig::new(UnitKind::TransformedMove),
+        ],
+        NonZeroUsize::new(20).unwrap(),
+    );
+    config.fetch_width = NonZeroUsize::new(2).unwrap();
+    let m = rename_execute_retire_test_harness::<SaveRestoreGprsInsns>(
+        PhantomConst::new_sized(config),
+        AluBranchKind::Real,
+    );
+    let mut sim = Simulation::new(m);
+    let _checked_vcd_output = checked_vcd_output!(
+        &mut sim,
+        "tests/expected/rename_execute_retire_real_alu_branch.vcd",
+    );
     sim.write_clock(sim.io().cd.clk, false);
     sim.write_reset(sim.io().cd.rst, true);
     for cycle in 0..700 {
@@ -4596,10 +4641,4 @@ fn test_rename_execute_retire_save_restore_gprs() {
         sim.write_reset(sim.io().cd.rst, false);
     }
     assert!(sim.read_bool(sim.io().all_outputs_written));
-    // FIXME: vcd is just whatever rename_execute_retire does now, which isn't known to be correct
-    let vcd = String::from_utf8(writer.writer.take().unwrap().take()).unwrap();
-    println!("####### VCD:\n{vcd}\n#######");
-    if vcd != include_str!("expected/rename_execute_retire_save_restore_gprs.vcd") {
-        panic!();
-    }
 }