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3300e7ca01
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3300e7ca01
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33b5d59507
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559e2967a2
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5e6041a97c
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21 changed files with 593349 additions and 131461 deletions
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@ -604,7 +604,7 @@ impl DecodeState<'_> {
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}],
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[],
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),
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MOpRegNum::const_zero().value,
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[MOpRegNum::const_zero(); 2],
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(li << 2).cast_to_static(),
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!aa,
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lk,
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@ -646,7 +646,7 @@ impl DecodeState<'_> {
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#[hdl]
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let branch_ctr_reg: MOpRegNum = wire();
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let dest = MOpDestReg::new([branch_lr_dest_reg], []);
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let src1 = addr_reg.unwrap_or_else(|| MOpRegNum::const_zero()).value;
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let src1 = addr_reg.unwrap_or_else(|| MOpRegNum::const_zero());
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let imm: Expr<SInt<_>> = (bd.unwrap_or(0_hdl_i14) << 2).cast_to_static();
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let invert_src2_eq_zero = !use_eq_for_ctr_compare;
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let pc_relative = match aa {
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@ -659,7 +659,7 @@ impl DecodeState<'_> {
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branch_mop,
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BranchMOp::branch_i(
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dest,
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src1,
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[MOpRegNum::const_zero(), src1],
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imm.cast_to_static::<SInt<_>>(),
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pc_relative,
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lk,
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@ -671,8 +671,7 @@ impl DecodeState<'_> {
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branch_mop,
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BranchMOp::branch_ctr(
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dest,
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src1,
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branch_ctr_reg.value,
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[MOpRegNum::const_zero(), src1, branch_ctr_reg],
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imm,
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invert_src2_eq_zero,
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pc_relative,
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@ -685,7 +684,7 @@ impl DecodeState<'_> {
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branch_mop,
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BranchMOp::branch_cond_ctr(
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dest,
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[cr_field.value, src1, branch_ctr_reg.value],
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[cr_field, src1, branch_ctr_reg],
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imm,
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!expected_cr_bit_value,
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condition_mode,
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@ -713,10 +712,7 @@ impl DecodeState<'_> {
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this.output[0],
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AddSubMOp::add_sub_i(
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MOpDestReg::new([MOpRegNum::power_isa_ctr_reg()], []),
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[
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MOpRegNum::power_isa_ctr_reg().value,
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MOpRegNum::const_zero().value,
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],
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[MOpRegNum::power_isa_ctr_reg(), MOpRegNum::const_zero()],
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(-1).cast_to_static::<SInt<_>>(),
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OutputIntegerMode.Full64(),
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false,
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@ -789,7 +785,7 @@ impl DecodeState<'_> {
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this.output[0],
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LogicalFlagsMOp::logical_flags(
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MOpDestReg::new([bt_reg], []),
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[ba_reg.value, bb_reg.value, bt_reg.value],
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[ba_reg, bb_reg, bt_reg],
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#[hdl]
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LogicalFlagsMOpImm {
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src0_start: src0_start.cast_to(LogicalFlagsMOpImm.src0_start),
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@ -815,7 +811,7 @@ impl DecodeState<'_> {
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this.output[0],
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MoveRegMOp::move_reg(
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MOpDestReg::new([crf(bf)], []),
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[crf(bfa).value],
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[crf(bfa)],
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0i8.cast_to_static::<SInt<_>>(),
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),
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);
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@ -892,7 +888,7 @@ impl DecodeState<'_> {
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this.output[0],
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AddSubMOp::add_sub_i(
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MOpDestReg::new([ea_reg], []),
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[MOpRegNum::const_zero().value; 2],
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[MOpRegNum::const_zero(); 2],
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d,
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OutputIntegerMode.Full64(),
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false,
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@ -906,7 +902,7 @@ impl DecodeState<'_> {
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this.output[0],
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AddSubMOp::add_sub_i(
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MOpDestReg::new([ea_reg], []),
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[gpr_or_zero(ra).value, MOpRegNum::const_zero().value],
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[gpr_or_zero(ra), MOpRegNum::const_zero()],
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d,
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OutputIntegerMode.Full64(),
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false,
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@ -918,12 +914,7 @@ impl DecodeState<'_> {
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}
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connect(
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this.output[1],
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LoadMOp::load(
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MOpDestReg::new([gpr(rt)], []),
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[ea_reg.value],
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width,
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conversion,
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),
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LoadMOp::load(MOpDestReg::new([gpr(rt)], []), [ea_reg], width, conversion),
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);
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},
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);
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@ -939,7 +930,7 @@ impl DecodeState<'_> {
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this.output[0],
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AddSubMOp::add_sub_i(
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MOpDestReg::new([ea_reg], []),
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[gpr_or_zero(ra).value, gpr(rb).value],
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[gpr_or_zero(ra), gpr(rb)],
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0.cast_to_static::<SInt<_>>(),
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OutputIntegerMode.Full64(),
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false,
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@ -950,12 +941,7 @@ impl DecodeState<'_> {
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);
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connect(
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this.output[1],
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LoadMOp::load(
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MOpDestReg::new([gpr(rt)], []),
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[ea_reg.value],
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width,
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conversion,
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),
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LoadMOp::load(MOpDestReg::new([gpr(rt)], []), [ea_reg], width, conversion),
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);
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});
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} else if self.arguments == Some("RT,disp(RA)") {
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@ -969,7 +955,7 @@ impl DecodeState<'_> {
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this.output[0],
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AddSubMOp::add_sub_i(
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MOpDestReg::new([ea_reg], []),
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[gpr_or_zero(ra).value, MOpRegNum::const_zero().value],
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[gpr_or_zero(ra), MOpRegNum::const_zero()],
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(ds << 2).cast_to_static::<SInt<_>>(),
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OutputIntegerMode.Full64(),
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false,
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@ -980,12 +966,7 @@ impl DecodeState<'_> {
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);
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connect(
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this.output[1],
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LoadMOp::load(
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MOpDestReg::new([gpr(rt)], []),
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[ea_reg.value],
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width,
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conversion,
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),
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LoadMOp::load(MOpDestReg::new([gpr(rt)], []), [ea_reg], width, conversion),
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);
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});
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} else {
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@ -1005,7 +986,7 @@ impl DecodeState<'_> {
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this.output[0],
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AddSubMOp::add_sub_i(
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MOpDestReg::new([ea_reg], []),
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[gpr_or_zero(ra).value, MOpRegNum::const_zero().value],
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[gpr_or_zero(ra), MOpRegNum::const_zero()],
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d.cast_to_static::<SInt<_>>(),
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OutputIntegerMode.Full64(),
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false,
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@ -1016,12 +997,7 @@ impl DecodeState<'_> {
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);
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connect(
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this.output[1],
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LoadMOp::load(
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MOpDestReg::new([gpr(rt)], []),
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[ea_reg.value],
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width,
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conversion,
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),
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LoadMOp::load(MOpDestReg::new([gpr(rt)], []), [ea_reg], width, conversion),
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);
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});
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}
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@ -1092,7 +1068,7 @@ impl DecodeState<'_> {
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this.output[1],
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StoreMOp::store(
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MOpDestReg::new([], []),
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[ea_reg.value, gpr(rs).value],
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[ea_reg, gpr(rs)],
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width,
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LoadStoreConversion.ZeroExt(),
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),
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@ -1107,7 +1083,7 @@ impl DecodeState<'_> {
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this.output[2],
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MoveRegMOp::move_reg(
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MOpDestReg::new([gpr(ra)], []),
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[ea_reg.value],
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[ea_reg],
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0.cast_to_static::<SInt<_>>(),
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),
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);
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@ -1126,7 +1102,7 @@ impl DecodeState<'_> {
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insn,
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AddSubMOp::add_sub_i(
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MOpDestReg::new([ea_reg], []),
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[MOpRegNum::const_zero().value; 2],
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[MOpRegNum::const_zero(); 2],
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d,
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OutputIntegerMode.Full64(),
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false,
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@ -1140,7 +1116,7 @@ impl DecodeState<'_> {
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insn,
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AddSubMOp::add_sub_i(
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MOpDestReg::new([ea_reg], []),
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[gpr_or_zero(ra).value, MOpRegNum::const_zero().value],
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[gpr_or_zero(ra), MOpRegNum::const_zero()],
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d,
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OutputIntegerMode.Full64(),
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false,
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@ -1161,7 +1137,7 @@ impl DecodeState<'_> {
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insn,
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AddSubMOp::add_sub_i(
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MOpDestReg::new([ea_reg], []),
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[gpr_or_zero(ra).value, gpr(rb).value],
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[gpr_or_zero(ra), gpr(rb)],
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0.cast_to_static::<SInt<_>>(),
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OutputIntegerMode.Full64(),
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false,
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@ -1179,7 +1155,7 @@ impl DecodeState<'_> {
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insn,
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AddSubMOp::add_sub_i(
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MOpDestReg::new([ea_reg], []),
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[gpr_or_zero(ra).value, MOpRegNum::const_zero().value],
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[gpr_or_zero(ra), MOpRegNum::const_zero()],
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(ds << 2).cast_to_static::<SInt<_>>(),
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OutputIntegerMode.Full64(),
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false,
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@ -1203,7 +1179,7 @@ impl DecodeState<'_> {
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insn,
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AddSubMOp::add_sub_i(
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MOpDestReg::new([ea_reg], []),
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[gpr_or_zero(ra).value, MOpRegNum::const_zero().value],
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[gpr_or_zero(ra), MOpRegNum::const_zero()],
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d.cast_to_static::<SInt<_>>(),
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OutputIntegerMode.Full64(),
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false,
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@ -1230,7 +1206,7 @@ impl DecodeState<'_> {
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AddSubMOp::add_sub_i(
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MOpDestReg::new([gpr(rt)], []),
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#[hdl]
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[gpr_or_zero(ra).value, MOpRegNum::const_zero().value],
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[gpr_or_zero(ra), MOpRegNum::const_zero()],
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si.cast_to_static(),
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OutputIntegerMode.Full64(),
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false,
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@ -1253,7 +1229,7 @@ impl DecodeState<'_> {
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AddSubMOp::add_sub_i(
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MOpDestReg::new([gpr(rt)], []),
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#[hdl]
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[gpr_or_zero(ra).value, MOpRegNum::const_zero().value],
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[gpr_or_zero(ra), MOpRegNum::const_zero()],
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((si0 << 16) + si1.cast_to(SInt[34])).cast_to_static(),
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OutputIntegerMode.Full64(),
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false,
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@ -1280,7 +1256,7 @@ impl DecodeState<'_> {
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AddSubMOp::add_sub_i(
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MOpDestReg::new([gpr(rt)], []),
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#[hdl]
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[gpr_or_zero(ra).value, MOpRegNum::const_zero().value],
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[gpr_or_zero(ra), MOpRegNum::const_zero()],
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(si << 16).cast_to_static(),
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OutputIntegerMode.Full64(),
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false,
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@ -1307,7 +1283,7 @@ impl DecodeState<'_> {
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AddSubMOp::add_sub_i(
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MOpDestReg::new([gpr(rt)], []),
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#[hdl]
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[MOpRegNum::const_zero().value; 2],
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[MOpRegNum::const_zero(); 2],
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(4i8 + (d << 16)).cast_to_static(),
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OutputIntegerMode.Full64(),
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false,
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@ -1340,7 +1316,7 @@ impl DecodeState<'_> {
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],
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),
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#[hdl]
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[gpr(ra).value, gpr(rb).value, MOpRegNum::const_zero().value],
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[gpr(ra), gpr(rb), MOpRegNum::const_zero()],
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0i8.cast_to_static::<SInt<_>>(),
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OutputIntegerMode.Full64(),
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false,
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@ -1371,7 +1347,7 @@ impl DecodeState<'_> {
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)],
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),
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#[hdl]
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[gpr(ra).value, MOpRegNum::const_zero().value],
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[gpr(ra), MOpRegNum::const_zero()],
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si.cast_to_static(),
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OutputIntegerMode.Full64(),
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false,
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@ -1410,7 +1386,7 @@ impl DecodeState<'_> {
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],
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),
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#[hdl]
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[gpr(ra).value, gpr(rb).value, MOpRegNum::const_zero().value],
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[gpr(ra), gpr(rb), MOpRegNum::const_zero()],
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0i8.cast_to_static::<SInt<_>>(),
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OutputIntegerMode.Full64(),
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true,
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|
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@ -1440,7 +1416,7 @@ impl DecodeState<'_> {
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)],
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),
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#[hdl]
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[gpr(ra).value, MOpRegNum::const_zero().value],
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[gpr(ra), MOpRegNum::const_zero()],
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si.cast_to_static(),
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OutputIntegerMode.Full64(),
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true,
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|
|
@ -1472,7 +1448,7 @@ impl DecodeState<'_> {
|
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],
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),
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#[hdl]
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[gpr(ra).value, gpr(rb).value, MOpRegNum::const_zero().value],
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[gpr(ra), gpr(rb), MOpRegNum::const_zero()],
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0i8.cast_to_static::<SInt<_>>(),
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OutputIntegerMode.Full64(),
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false,
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|
|
@ -1505,11 +1481,7 @@ impl DecodeState<'_> {
|
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],
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),
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#[hdl]
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[
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gpr(ra).value,
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MOpRegNum::power_isa_xer_ca_ca32_reg().value,
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gpr(rb).value,
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],
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[gpr(ra), MOpRegNum::power_isa_xer_ca_ca32_reg(), gpr(rb)],
|
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0i8.cast_to_static::<SInt<_>>(),
|
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OutputIntegerMode.Full64(),
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false,
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||||
|
|
@ -1542,11 +1514,7 @@ impl DecodeState<'_> {
|
|||
],
|
||||
),
|
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#[hdl]
|
||||
[
|
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gpr(ra).value,
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MOpRegNum::power_isa_xer_ca_ca32_reg().value,
|
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gpr(rb).value,
|
||||
],
|
||||
[gpr(ra), MOpRegNum::power_isa_xer_ca_ca32_reg(), gpr(rb)],
|
||||
0i8.cast_to_static::<SInt<_>>(),
|
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OutputIntegerMode.Full64(),
|
||||
true,
|
||||
|
|
@ -1580,9 +1548,9 @@ impl DecodeState<'_> {
|
|||
),
|
||||
#[hdl]
|
||||
[
|
||||
gpr(ra).value,
|
||||
MOpRegNum::power_isa_xer_ca_ca32_reg().value,
|
||||
MOpRegNum::const_zero().value,
|
||||
gpr(ra),
|
||||
MOpRegNum::power_isa_xer_ca_ca32_reg(),
|
||||
MOpRegNum::const_zero(),
|
||||
],
|
||||
if this.mnemonic.contains('m') { -1i8 } else { 0 }
|
||||
.cast_to_static::<SInt<_>>(),
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||||
|
|
@ -1617,11 +1585,7 @@ impl DecodeState<'_> {
|
|||
],
|
||||
),
|
||||
#[hdl]
|
||||
[
|
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gpr(ra).value,
|
||||
MOpRegNum::const_zero().value,
|
||||
MOpRegNum::const_zero().value,
|
||||
],
|
||||
[gpr(ra), MOpRegNum::const_zero(), MOpRegNum::const_zero()],
|
||||
0i8.cast_to_static::<SInt<_>>(),
|
||||
OutputIntegerMode.Full64(),
|
||||
true,
|
||||
|
|
@ -1654,7 +1618,7 @@ impl DecodeState<'_> {
|
|||
this.output[0],
|
||||
CompareMOp::compare_i(
|
||||
MOpDestReg::new([crf(bf)], []),
|
||||
[gpr(ra).value],
|
||||
[gpr(ra)],
|
||||
si.cast_to_static::<SInt<_>>(),
|
||||
compare_mode,
|
||||
),
|
||||
|
|
@ -1682,7 +1646,7 @@ impl DecodeState<'_> {
|
|||
this.output[0],
|
||||
CompareMOp::compare(
|
||||
MOpDestReg::new([crf(bf)], []),
|
||||
[gpr(ra).value, gpr(rb).value],
|
||||
[gpr(ra), gpr(rb)],
|
||||
compare_mode,
|
||||
),
|
||||
);
|
||||
|
|
@ -1709,7 +1673,7 @@ impl DecodeState<'_> {
|
|||
this.output[0],
|
||||
CompareMOp::compare_i(
|
||||
MOpDestReg::new([crf(bf)], []),
|
||||
[gpr(ra).value],
|
||||
[gpr(ra)],
|
||||
ui.cast_to_static::<SInt<_>>(),
|
||||
compare_mode,
|
||||
),
|
||||
|
|
@ -1737,7 +1701,7 @@ impl DecodeState<'_> {
|
|||
this.output[0],
|
||||
CompareMOp::compare(
|
||||
MOpDestReg::new([crf(bf)], []),
|
||||
[gpr(ra).value, gpr(rb).value],
|
||||
[gpr(ra), gpr(rb)],
|
||||
compare_mode,
|
||||
),
|
||||
);
|
||||
|
|
@ -1764,7 +1728,7 @@ impl DecodeState<'_> {
|
|||
this.output[0],
|
||||
CompareMOp::compare(
|
||||
MOpDestReg::new([crf(bf)], []),
|
||||
[gpr(ra).value, gpr(rb).value],
|
||||
[gpr(ra), gpr(rb)],
|
||||
compare_mode,
|
||||
),
|
||||
);
|
||||
|
|
@ -1783,7 +1747,7 @@ impl DecodeState<'_> {
|
|||
this.output[0],
|
||||
CompareMOp::compare(
|
||||
MOpDestReg::new([crf(bf)], []),
|
||||
[gpr(ra).value, gpr(rb).value],
|
||||
[gpr(ra), gpr(rb)],
|
||||
CompareMode.CmpEqB(),
|
||||
),
|
||||
);
|
||||
|
|
@ -1815,7 +1779,7 @@ impl DecodeState<'_> {
|
|||
this.mnemonic.contains('.').to_expr(),
|
||||
)],
|
||||
),
|
||||
[gpr(rs).value],
|
||||
[gpr(rs)],
|
||||
if this.mnemonic.contains('s') {
|
||||
(ui << 16).cast_to_static::<SInt<_>>()
|
||||
} else {
|
||||
|
|
@ -1863,7 +1827,7 @@ impl DecodeState<'_> {
|
|||
this.output[0],
|
||||
LogicalMOp::logical(
|
||||
MOpDestReg::new([gpr(ra)], [(MOpRegNum::POWER_ISA_CR_0_REG_NUM, rc)]),
|
||||
[gpr(rs).value, gpr(rb).value],
|
||||
[gpr(rs), gpr(rb)],
|
||||
0.cast_to_static::<SInt<_>>(),
|
||||
OutputIntegerMode.Full64(),
|
||||
lut,
|
||||
|
|
@ -1877,7 +1841,7 @@ impl DecodeState<'_> {
|
|||
this.output[0],
|
||||
MoveRegMOp::move_reg(
|
||||
MOpDestReg::new([gpr(ra)], []),
|
||||
[gpr(rs).value],
|
||||
[gpr(rs)],
|
||||
0i8.cast_to_static::<SInt<_>>(),
|
||||
),
|
||||
);
|
||||
|
|
@ -1906,7 +1870,7 @@ impl DecodeState<'_> {
|
|||
this.output[0],
|
||||
LogicalMOp::logical_i(
|
||||
MOpDestReg::new([gpr(ra)], [(MOpRegNum::POWER_ISA_CR_0_REG_NUM, rc)]),
|
||||
[gpr(rs).value],
|
||||
[gpr(rs)],
|
||||
0.cast_to_static::<SInt<_>>(),
|
||||
output_integer_mode,
|
||||
Lut4::from_fn(|a, b| a | b),
|
||||
|
|
@ -1984,7 +1948,7 @@ impl DecodeState<'_> {
|
|||
self.output[0],
|
||||
ShiftRotateMOp::shift_rotate(
|
||||
MOpDestReg::new([gpr(ra.0)], [(MOpRegNum::POWER_ISA_CR_0_REG_NUM, rc.0)]),
|
||||
[gpr(rs.0).value, gpr(rs.0).value, gpr(rb.0).value],
|
||||
[gpr(rs.0), gpr(rs.0), gpr(rb.0)],
|
||||
#[hdl]
|
||||
ShiftRotateMOpImm {
|
||||
shift_rotate_amount: HdlNone(),
|
||||
|
|
@ -2021,20 +1985,20 @@ impl DecodeState<'_> {
|
|||
self.rotate_dest_logic_op(msb0_mask_begin, msb0_mask_end, fallback_is_src2);
|
||||
#[hdl]
|
||||
let rotate_imm_src2 = wire();
|
||||
connect(rotate_imm_src2, MOpRegNum::const_zero().value);
|
||||
connect(rotate_imm_src2, MOpRegNum::const_zero());
|
||||
// if dest_logic_op is HdlNone, we don't need to read from src2
|
||||
#[hdl]
|
||||
if let HdlSome(dest_logic_op) = dest_logic_op {
|
||||
#[hdl]
|
||||
if dest_logic_op.fallback_is_src2 {
|
||||
connect(rotate_imm_src2, gpr(ra.0).value);
|
||||
connect(rotate_imm_src2, gpr(ra.0));
|
||||
}
|
||||
}
|
||||
connect(
|
||||
self.output[0],
|
||||
ShiftRotateMOp::shift_rotate(
|
||||
MOpDestReg::new([gpr(ra.0)], [(MOpRegNum::POWER_ISA_CR_0_REG_NUM, rc.0)]),
|
||||
[gpr(rs.0).value, gpr(rs.0).value, rotate_imm_src2],
|
||||
[gpr(rs.0), gpr(rs.0), rotate_imm_src2],
|
||||
#[hdl]
|
||||
ShiftRotateMOpImm {
|
||||
shift_rotate_amount: HdlSome(rotate_amount),
|
||||
|
|
@ -2184,11 +2148,7 @@ impl DecodeState<'_> {
|
|||
[gpr(ra), MOpRegNum::power_isa_xer_ca_ca32_reg()],
|
||||
[(MOpRegNum::POWER_ISA_CR_0_REG_NUM, rc)],
|
||||
),
|
||||
[
|
||||
gpr(rs).value,
|
||||
MOpRegNum::const_zero().value,
|
||||
MOpRegNum::const_zero().value,
|
||||
],
|
||||
[gpr(rs), MOpRegNum::const_zero(), MOpRegNum::const_zero()],
|
||||
#[hdl]
|
||||
ShiftRotateMOpImm {
|
||||
shift_rotate_amount: HdlSome(sh.cast_to_static::<UInt<_>>()),
|
||||
|
|
@ -2216,11 +2176,7 @@ impl DecodeState<'_> {
|
|||
[gpr(ra), MOpRegNum::power_isa_xer_ca_ca32_reg()],
|
||||
[(MOpRegNum::POWER_ISA_CR_0_REG_NUM, rc)],
|
||||
),
|
||||
[
|
||||
gpr(rs).value,
|
||||
MOpRegNum::const_zero().value,
|
||||
MOpRegNum::const_zero().value,
|
||||
],
|
||||
[gpr(rs), MOpRegNum::const_zero(), MOpRegNum::const_zero()],
|
||||
#[hdl]
|
||||
ShiftRotateMOpImm {
|
||||
shift_rotate_amount: HdlSome(sh.rotate_right(1)),
|
||||
|
|
@ -2258,9 +2214,9 @@ impl DecodeState<'_> {
|
|||
[(MOpRegNum::POWER_ISA_CR_0_REG_NUM, rc)],
|
||||
),
|
||||
if !is_signed && is_right_shift {
|
||||
[MOpRegNum::const_zero().value, gpr(rs).value, gpr(rb).value]
|
||||
[MOpRegNum::const_zero(), gpr(rs), gpr(rb)]
|
||||
} else {
|
||||
[gpr(rs).value, MOpRegNum::const_zero().value, gpr(rb).value]
|
||||
[gpr(rs), MOpRegNum::const_zero(), gpr(rb)]
|
||||
},
|
||||
#[hdl]
|
||||
ShiftRotateMOpImm {
|
||||
|
|
@ -2296,11 +2252,7 @@ impl DecodeState<'_> {
|
|||
this.output[0],
|
||||
ShiftRotateMOp::shift_rotate(
|
||||
MOpDestReg::new([gpr(ra)], [(MOpRegNum::POWER_ISA_CR_0_REG_NUM, rc)]),
|
||||
[
|
||||
gpr(rs).value,
|
||||
MOpRegNum::const_zero().value,
|
||||
MOpRegNum::const_zero().value,
|
||||
],
|
||||
[gpr(rs), MOpRegNum::const_zero(), MOpRegNum::const_zero()],
|
||||
#[hdl]
|
||||
ShiftRotateMOpImm {
|
||||
shift_rotate_amount: HdlSome(sh.rotate_right(1)),
|
||||
|
|
@ -2330,7 +2282,7 @@ impl DecodeState<'_> {
|
|||
self.output[0],
|
||||
MoveRegMOp::move_reg(
|
||||
MOpDestReg::new([spr], []),
|
||||
[gpr(reg).value],
|
||||
[gpr(reg)],
|
||||
0.cast_to_static::<SInt<_>>(),
|
||||
),
|
||||
);
|
||||
|
|
@ -2339,7 +2291,7 @@ impl DecodeState<'_> {
|
|||
self.output[0],
|
||||
MoveRegMOp::move_reg(
|
||||
MOpDestReg::new([gpr(reg)], []),
|
||||
[spr.value],
|
||||
[spr],
|
||||
0.cast_to_static::<SInt<_>>(),
|
||||
),
|
||||
);
|
||||
|
|
@ -2355,7 +2307,7 @@ impl DecodeState<'_> {
|
|||
self.output[0],
|
||||
ReadSpecialMOp::read_special(
|
||||
MOpDestReg::new([gpr(reg)], []),
|
||||
[MOpRegNum::const_zero().value; 0],
|
||||
[MOpRegNum::const_zero(); 0],
|
||||
imm,
|
||||
),
|
||||
);
|
||||
|
|
@ -2431,9 +2383,9 @@ impl DecodeState<'_> {
|
|||
LogicalFlagsMOp::logical_flags(
|
||||
MOpDestReg::new([crf(bf)], []),
|
||||
[
|
||||
MOpRegNum::power_isa_xer_ca_ca32_reg().value,
|
||||
MOpRegNum::const_zero().value,
|
||||
MOpRegNum::power_isa_xer_so_ov_ov32_reg().value,
|
||||
MOpRegNum::power_isa_xer_ca_ca32_reg(),
|
||||
MOpRegNum::const_zero(),
|
||||
MOpRegNum::power_isa_xer_so_ov_ov32_reg(),
|
||||
],
|
||||
LogicalFlagsMOpImm::from_swizzle_fn::<PRegFlagsPowerISA>(|src0, src1, src2| {
|
||||
let mut dest = PRegFlagsPowerISAView::splat(None);
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -25,89 +25,206 @@ pub struct PowerIsaCrBitNum {
|
|||
pub bit_in_field: UInt<2>,
|
||||
}
|
||||
|
||||
impl MOpRegNum {
|
||||
pub const POWER_ISA_LR_REG_NUM: u32 = 1;
|
||||
#[hdl]
|
||||
pub fn power_isa_lr_reg() -> Expr<Self> {
|
||||
#[hdl]
|
||||
Self {
|
||||
value: Self::POWER_ISA_LR_REG_NUM.cast_to_static::<UInt<_>>(),
|
||||
}
|
||||
}
|
||||
pub const POWER_ISA_CTR_REG_NUM: u32 = 2;
|
||||
#[hdl]
|
||||
pub fn power_isa_ctr_reg() -> Expr<Self> {
|
||||
#[hdl]
|
||||
Self {
|
||||
value: Self::POWER_ISA_CTR_REG_NUM.cast_to_static::<UInt<_>>(),
|
||||
}
|
||||
}
|
||||
pub const POWER_ISA_TAR_REG_NUM: u32 = 3;
|
||||
#[hdl]
|
||||
pub fn power_isa_tar_reg() -> Expr<Self> {
|
||||
#[hdl]
|
||||
Self {
|
||||
value: Self::POWER_ISA_TAR_REG_NUM.cast_to_static::<UInt<_>>(),
|
||||
}
|
||||
}
|
||||
macro_rules! suffix_str_with_0_to_31 {
|
||||
($str:literal) => {
|
||||
suffix_str_with_0_to_31!(
|
||||
$str,
|
||||
[
|
||||
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22,
|
||||
23, 24, 25, 26, 27, 28, 29, 30, 31,
|
||||
]
|
||||
)
|
||||
};
|
||||
($str:literal, [$($num:literal),* $(,)?]) => {
|
||||
[$(concat!($str, $num)),*]
|
||||
};
|
||||
}
|
||||
|
||||
const fn fill_names_range<'a>(dest: &mut [Option<&'a str>], range: Range<u32>, src: &[&'a str]) {
|
||||
assert!((range.end - range.start) as usize == src.len());
|
||||
let mut i = 0;
|
||||
while i < src.len() {
|
||||
dest[i + range.start as usize] = Some(src[i]);
|
||||
i += 1;
|
||||
}
|
||||
}
|
||||
|
||||
macro_rules! power_isa_regs {
|
||||
(
|
||||
$(
|
||||
#[name_str = $name_str:literal, expr_fn = $expr_fn:ident, sim_fn = $sim_fn:ident]
|
||||
$(#[doc = $($doc:tt)*])*
|
||||
pub const $REG_NUM:ident: u32 = $reg_num_expr:expr;
|
||||
)*
|
||||
$(
|
||||
#[names_fn = |$names_var:ident| $names_body:expr $(,
|
||||
reg_num_fn = $reg_num_fn_multi:ident,
|
||||
expr_fn = $expr_fn_multi:ident($fn_multi_arg:ty),
|
||||
expr_imm_fn = $expr_imm_fn_multi:ident,
|
||||
sim_fn = $sim_fn_multi:ident,)?
|
||||
]
|
||||
$(#[doc = $($doc_multi:tt)*])*
|
||||
pub const $REG_NUM_MULTI:ident: Range<u32> = $reg_num_multi_expr:expr;
|
||||
)*
|
||||
) => {
|
||||
impl MOpRegNum {
|
||||
pub const POWER_ISA_REG_NAMES: &[Option<&str>; 1 << Self::WIDTH] = &{
|
||||
let mut retval = [None; _];
|
||||
$(retval[Self::$REG_NUM as usize] = Some($name_str);)*
|
||||
$({
|
||||
let $names_var = &mut retval;
|
||||
$names_body
|
||||
})*
|
||||
retval
|
||||
};
|
||||
$(
|
||||
$(#[doc = $($doc)*])*
|
||||
pub const $REG_NUM: u32 = $reg_num_expr;
|
||||
$(#[doc = $($doc)*])*
|
||||
#[hdl]
|
||||
pub fn $expr_fn() -> Expr<Self> {
|
||||
#[hdl]
|
||||
Self {
|
||||
value: Self::$REG_NUM.cast_to_static::<UInt<_>>(),
|
||||
}
|
||||
}
|
||||
$(#[doc = $($doc)*])*
|
||||
#[hdl]
|
||||
pub fn $sim_fn() -> SimValue<Self> {
|
||||
#[hdl(sim)]
|
||||
Self {
|
||||
value: Self::$REG_NUM.cast_to_static::<UInt<_>>(),
|
||||
}
|
||||
}
|
||||
)*
|
||||
$(
|
||||
$(#[doc = $($doc_multi)*])*
|
||||
pub const $REG_NUM_MULTI: Range<u32> = $reg_num_multi_expr;
|
||||
power_isa_regs! {
|
||||
@helper_fns
|
||||
#[names_fn = |$names_var| $names_body $(,
|
||||
reg_num_fn = $reg_num_fn_multi,
|
||||
expr_fn = $expr_fn_multi($fn_multi_arg),
|
||||
expr_imm_fn = $expr_imm_fn_multi,
|
||||
sim_fn = $sim_fn_multi,)?
|
||||
]
|
||||
$(#[doc = $($doc_multi)*])*
|
||||
pub const $REG_NUM_MULTI: Range<u32> = $reg_num_multi_expr;
|
||||
}
|
||||
)*
|
||||
}
|
||||
};
|
||||
(
|
||||
@helper_fns
|
||||
#[names_fn = |$names_var:ident| $names_body:expr]
|
||||
$(#[doc = $($doc_multi:tt)*])*
|
||||
pub const $REG_NUM_MULTI:ident: Range<u32> = $reg_num_multi_expr:expr;
|
||||
) => {};
|
||||
(
|
||||
@helper_fns
|
||||
#[
|
||||
names_fn = |$names_var:ident| $names_body:expr,
|
||||
reg_num_fn = $reg_num_fn_multi:ident,
|
||||
expr_fn = $expr_fn_multi:ident($fn_multi_arg:ty),
|
||||
expr_imm_fn = $expr_imm_fn_multi:ident,
|
||||
sim_fn = $sim_fn_multi:ident,
|
||||
]
|
||||
$(#[doc = $($doc_multi:tt)*])*
|
||||
pub const $REG_NUM_MULTI:ident: Range<u32> = $reg_num_multi_expr:expr;
|
||||
) => {
|
||||
$(#[doc = $($doc_multi)*])*
|
||||
pub const fn $reg_num_fn_multi(index: usize) -> u32 {
|
||||
range_u32_nth_or_panic(&Self::$REG_NUM_MULTI, index)
|
||||
}
|
||||
$(#[doc = $($doc_multi)*])*
|
||||
#[hdl]
|
||||
pub fn $expr_fn_multi(input: Expr<$fn_multi_arg>) -> Expr<Self> {
|
||||
#[hdl]
|
||||
Self {
|
||||
value: (Self::$REG_NUM_MULTI.start + input).cast_to_static::<UInt<_>>(),
|
||||
}
|
||||
}
|
||||
$(#[doc = $($doc_multi)*])*
|
||||
#[hdl]
|
||||
pub fn $expr_imm_fn_multi(input: usize) -> Expr<Self> {
|
||||
#[hdl]
|
||||
Self {
|
||||
value: Self::$reg_num_fn_multi(input).cast_to_static::<UInt<_>>(),
|
||||
}
|
||||
}
|
||||
$(#[doc = $($doc_multi)*])*
|
||||
#[hdl]
|
||||
pub fn $sim_fn_multi(reg_num: &SimValue<$fn_multi_arg>) -> SimValue<Self> {
|
||||
#[hdl(sim)]
|
||||
Self {
|
||||
value: (Self::$REG_NUM_MULTI.start + reg_num).cast_to_static::<UInt<_>>(),
|
||||
}
|
||||
}
|
||||
};
|
||||
}
|
||||
|
||||
power_isa_regs! {
|
||||
#[name_str = "lr", expr_fn = power_isa_lr_reg, sim_fn = power_isa_lr_reg_sim]
|
||||
pub const POWER_ISA_LR_REG_NUM: u32 = 1;
|
||||
#[name_str = "ctr", expr_fn = power_isa_ctr_reg, sim_fn = power_isa_ctr_reg_sim]
|
||||
pub const POWER_ISA_CTR_REG_NUM: u32 = 2;
|
||||
#[name_str = "tar", expr_fn = power_isa_tar_reg, sim_fn = power_isa_tar_reg_sim]
|
||||
pub const POWER_ISA_TAR_REG_NUM: u32 = 3;
|
||||
|
||||
#[name_str = "xer[so,ov,ov32]", expr_fn = power_isa_xer_so_ov_ov32_reg, sim_fn = power_isa_xer_so_ov_ov32_reg_sim]
|
||||
/// SO, OV, and OV32 XER bits -- in [`PRegValue.flags`]
|
||||
///
|
||||
/// [`PRegValue.flags`]: struct@crate::register::PRegValue
|
||||
pub const POWER_ISA_XER_SO_OV_OV32_REG_NUM: u32 =
|
||||
range_u32_nth_or_panic(&Self::FLAG_REG_NUMS, 0);
|
||||
|
||||
#[name_str = "xer[ca,ca32]", expr_fn = power_isa_xer_ca_ca32_reg, sim_fn = power_isa_xer_ca_ca32_reg_sim]
|
||||
/// CA and CA32 XER bits -- in [`PRegValue.flags`]
|
||||
///
|
||||
/// [`PRegValue.flags`]: struct@crate::register::PRegValue
|
||||
pub const POWER_ISA_XER_CA_CA32_REG_NUM: u32 = 4;
|
||||
|
||||
#[name_str = "xer[other]", expr_fn = power_isa_xer_other_reg, sim_fn = power_isa_xer_other_reg_sim]
|
||||
/// only the XER bits that don't exist in [`PRegValue.flags`]
|
||||
///
|
||||
/// [`PRegValue.flags`]: struct@crate::register::PRegValue
|
||||
pub const POWER_ISA_XER_OTHER_REG_NUM: u32 = 5;
|
||||
|
||||
#[name_str = "temp", expr_fn = power_isa_temp_reg, sim_fn = power_isa_temp_reg_sim]
|
||||
/// used as a temporary for things like computing the effective address before loading/storing memory
|
||||
pub const POWER_ISA_TEMP_REG_NUM: u32 = 8;
|
||||
#[hdl]
|
||||
pub fn power_isa_temp_reg() -> Expr<Self> {
|
||||
#[hdl]
|
||||
Self {
|
||||
value: Self::POWER_ISA_TEMP_REG_NUM.cast_to_static::<UInt<_>>(),
|
||||
}
|
||||
}
|
||||
|
||||
/// SO, OV, and OV32 XER bits -- in [`PRegValue.flags`]
|
||||
///
|
||||
/// [`PRegValue.flags`]: struct@crate::register::PRegValue
|
||||
#[hdl]
|
||||
pub fn power_isa_xer_so_ov_ov32_reg() -> Expr<Self> {
|
||||
#[hdl]
|
||||
Self {
|
||||
value: Self::POWER_ISA_XER_SO_OV_OV32_REG_NUM.cast_to_static::<UInt<_>>(),
|
||||
}
|
||||
}
|
||||
/// CA and CA32 XER bits -- in [`PRegValue.flags`]
|
||||
///
|
||||
/// [`PRegValue.flags`]: struct@crate::register::PRegValue
|
||||
#[hdl]
|
||||
pub fn power_isa_xer_ca_ca32_reg() -> Expr<Self> {
|
||||
#[hdl]
|
||||
Self {
|
||||
value: Self::POWER_ISA_XER_CA_CA32_REG_NUM.cast_to_static::<UInt<_>>(),
|
||||
}
|
||||
}
|
||||
/// only the XER bits that don't exist in [`PRegValue.flags`]
|
||||
///
|
||||
/// [`PRegValue.flags`]: struct@crate::register::PRegValue
|
||||
#[hdl]
|
||||
pub fn power_isa_xer_other_reg() -> Expr<Self> {
|
||||
#[hdl]
|
||||
Self {
|
||||
value: Self::POWER_ISA_XER_OTHER_REG_NUM.cast_to_static::<UInt<_>>(),
|
||||
}
|
||||
}
|
||||
|
||||
#[name_str = "cr0", expr_fn = power_isa_cr_0_reg, sim_fn = power_isa_cr_0_reg_sim]
|
||||
pub const POWER_ISA_CR_0_REG_NUM: u32 = range_u32_nth_or_panic(&Self::FLAG_REG_NUMS, 1);
|
||||
#[names_fn = |names| {
|
||||
fill_names_range(names, Self::POWER_ISA_CR_1_THRU_7_REG_NUMS, &["cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7"]);
|
||||
}]
|
||||
pub const POWER_ISA_CR_1_THRU_7_REG_NUMS: Range<u32> = 9..16;
|
||||
|
||||
#[
|
||||
names_fn = |names| {
|
||||
fill_names_range(names, Self::POWER_ISA_GPR_REG_NUMS, &suffix_str_with_0_to_31!("r"));
|
||||
},
|
||||
reg_num_fn = power_isa_gpr_reg_num,
|
||||
expr_fn = power_isa_gpr_reg(UInt<5>),
|
||||
expr_imm_fn = power_isa_gpr_reg_imm,
|
||||
sim_fn = power_isa_gpr_reg_sim,
|
||||
]
|
||||
pub const POWER_ISA_GPR_REG_NUMS: Range<u32> = 32..64;
|
||||
|
||||
#[
|
||||
names_fn = |names| {
|
||||
fill_names_range(names, Self::POWER_ISA_FPR_REG_NUMS, &suffix_str_with_0_to_31!("f"));
|
||||
},
|
||||
reg_num_fn = power_isa_fpr_reg_num,
|
||||
expr_fn = power_isa_fpr_reg(UInt<5>),
|
||||
expr_imm_fn = power_isa_fpr_reg_imm,
|
||||
sim_fn = power_isa_fpr_reg_sim,
|
||||
]
|
||||
pub const POWER_ISA_FPR_REG_NUMS: Range<u32> = 64..96;
|
||||
}
|
||||
|
||||
impl MOpRegNum {
|
||||
pub const fn power_isa_cr_reg_num(index: usize) -> u32 {
|
||||
if index == 0 {
|
||||
Self::POWER_ISA_CR_0_REG_NUM
|
||||
|
|
@ -148,31 +265,6 @@ impl MOpRegNum {
|
|||
}
|
||||
}
|
||||
|
||||
pub const POWER_ISA_GPR_REG_NUMS: Range<u32> = 32..64;
|
||||
pub const fn power_isa_gpr_reg_num(index: usize) -> u32 {
|
||||
range_u32_nth_or_panic(&Self::POWER_ISA_GPR_REG_NUMS, index)
|
||||
}
|
||||
#[hdl]
|
||||
pub fn power_isa_gpr_reg(reg_num: Expr<UInt<5>>) -> Expr<Self> {
|
||||
#[hdl]
|
||||
Self {
|
||||
value: (Self::POWER_ISA_GPR_REG_NUMS.start + reg_num).cast_to_static::<UInt<_>>(),
|
||||
}
|
||||
}
|
||||
#[hdl]
|
||||
pub fn power_isa_gpr_reg_imm(index: usize) -> Expr<Self> {
|
||||
#[hdl]
|
||||
Self {
|
||||
value: Self::power_isa_gpr_reg_num(index).cast_to_static::<UInt<_>>(),
|
||||
}
|
||||
}
|
||||
#[hdl]
|
||||
pub fn power_isa_gpr_reg_sim(reg_num: &SimValue<UInt<5>>) -> SimValue<Self> {
|
||||
#[hdl(sim)]
|
||||
Self {
|
||||
value: (Self::POWER_ISA_GPR_REG_NUMS.start + reg_num).cast_to_static::<UInt<_>>(),
|
||||
}
|
||||
}
|
||||
pub const fn power_isa_gpr_or_zero_reg_num(index: usize) -> u32 {
|
||||
if index == 0 {
|
||||
Self::CONST_ZERO_REG_NUM
|
||||
|
|
@ -208,25 +300,6 @@ impl MOpRegNum {
|
|||
.cast_to_static::<UInt<_>>(),
|
||||
}
|
||||
}
|
||||
|
||||
pub const POWER_ISA_FPR_REG_NUMS: Range<u32> = 64..96;
|
||||
pub const fn power_isa_fpr_reg_num(index: usize) -> u32 {
|
||||
range_u32_nth_or_panic(&Self::POWER_ISA_FPR_REG_NUMS, index)
|
||||
}
|
||||
#[hdl]
|
||||
pub fn power_isa_fpr_reg(reg_num: Expr<UInt<5>>) -> Expr<Self> {
|
||||
#[hdl]
|
||||
Self {
|
||||
value: (Self::POWER_ISA_FPR_REG_NUMS.start + reg_num).cast_to_static::<UInt<_>>(),
|
||||
}
|
||||
}
|
||||
#[hdl]
|
||||
pub fn power_isa_fpr_reg_sim(reg_num: &SimValue<UInt<5>>) -> SimValue<Self> {
|
||||
#[hdl(sim)]
|
||||
Self {
|
||||
value: (Self::POWER_ISA_FPR_REG_NUMS.start + reg_num).cast_to_static::<UInt<_>>(),
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#[hdl(cmp_eq)]
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@ use fayalite::{
|
|||
expr::CastToImpl,
|
||||
int::{BoolOrIntType, UIntInRange},
|
||||
prelude::*,
|
||||
ty::StaticType,
|
||||
ty::{SimValueDebug, StaticType},
|
||||
};
|
||||
use std::{any::Any, fmt};
|
||||
|
||||
|
|
@ -49,6 +49,7 @@ pub trait PRegFlagsViewTrait: Type + PRegFlagsViewTraitSealed {
|
|||
fn view_into_view_unused<T>(view: Self::View<T>) -> ViewUnused<T, PRegFlagsAllUnused>;
|
||||
fn debug_fmt<'a, T: 'a, F: FnMut(&'a T, bool) -> Option<D>, D: fmt::Debug>(
|
||||
view: &'a Self::View<T>,
|
||||
type_name: Option<&str>,
|
||||
field: F,
|
||||
f: &mut fmt::Formatter<'_>,
|
||||
) -> fmt::Result;
|
||||
|
|
@ -475,6 +476,7 @@ macro_rules! impl_view_trait {
|
|||
|
||||
fn debug_fmt<'a, T: 'a, F: FnMut(&'a T, bool) -> Option<D>, D: fmt::Debug>(
|
||||
view: &'a Self::View<T>,
|
||||
type_name: Option<&str>,
|
||||
mut field: F,
|
||||
f: &mut fmt::Formatter<'_>,
|
||||
) -> fmt::Result {
|
||||
|
|
@ -482,7 +484,7 @@ macro_rules! impl_view_trait {
|
|||
$unused: ViewUnused([$($unused_field,)*]),
|
||||
$($view_field: $flags_field,)*
|
||||
} = view;
|
||||
let mut debug_struct = f.debug_struct(stringify!($FlagsMode));
|
||||
let mut debug_struct = f.debug_struct(type_name.unwrap_or(stringify!($FlagsMode)));
|
||||
#[allow(unused_mut)]
|
||||
let mut any_skipped = false;
|
||||
$(if let Some(v) = field($flags_field, true) {
|
||||
|
|
@ -774,25 +776,40 @@ impl<T: Type> PRegFlags<T> {
|
|||
#[hdl]
|
||||
pub fn debug_fmt<V: PRegFlagsViewTrait>(
|
||||
this: &SimValue<Self>,
|
||||
type_name: Option<&str>,
|
||||
f: &mut fmt::Formatter<'_>,
|
||||
) -> fmt::Result {
|
||||
if let Some(this) = <dyn Any>::downcast_ref::<SimValue<PRegFlags>>(this) {
|
||||
V::debug_fmt(
|
||||
&PRegFlags::view_sim_ref::<V>(this),
|
||||
type_name,
|
||||
|v, _| v.then_some(*v),
|
||||
f,
|
||||
)
|
||||
} else {
|
||||
V::debug_fmt(&PRegFlags::view_sim_ref::<V>(this), |v, _| Some(*v), f)
|
||||
V::debug_fmt(
|
||||
&PRegFlags::view_sim_ref::<V>(this),
|
||||
type_name,
|
||||
|v, _| Some(*v),
|
||||
f,
|
||||
)
|
||||
}
|
||||
}
|
||||
#[hdl]
|
||||
pub fn debug_fmt_mode(this: &SimValue<Self>, mode: &SimValue<FlagsMode>) -> impl fmt::Debug {
|
||||
pub fn debug_fmt_mode(
|
||||
this: &SimValue<Self>,
|
||||
short_name: bool,
|
||||
mode: &SimValue<FlagsMode>,
|
||||
) -> impl fmt::Debug {
|
||||
fmt::from_fn(move |f| {
|
||||
#[hdl(sim)]
|
||||
match mode {
|
||||
FlagsMode::PowerISA(_) => Self::debug_fmt::<PRegFlagsPowerISA>(this, f),
|
||||
FlagsMode::X86(_) => Self::debug_fmt::<PRegFlagsX86>(this, f),
|
||||
FlagsMode::PowerISA(_) => {
|
||||
Self::debug_fmt::<PRegFlagsPowerISA>(this, short_name.then_some("Pwr"), f)
|
||||
}
|
||||
FlagsMode::X86(_) => {
|
||||
Self::debug_fmt::<PRegFlagsX86>(this, short_name.then_some("X86"), f)
|
||||
}
|
||||
}
|
||||
})
|
||||
}
|
||||
|
|
@ -819,7 +836,7 @@ impl PRegFlags {
|
|||
pub const FLAG_COUNT: usize = PRegFlagsAllUnused::UNUSED_INNER_LEN;
|
||||
}
|
||||
|
||||
#[hdl(cmp_eq)]
|
||||
#[hdl(cmp_eq, custom_debug(sim))]
|
||||
/// Unit output register's value -- a combination of an integer/fp register
|
||||
/// and flags register and CR field.
|
||||
///
|
||||
|
|
@ -830,6 +847,15 @@ pub struct PRegValue {
|
|||
pub flags: PRegFlags,
|
||||
}
|
||||
|
||||
impl SimValueDebug for PRegValue {
|
||||
fn sim_value_debug(
|
||||
value: &<Self as Type>::SimValue,
|
||||
f: &mut fmt::Formatter<'_>,
|
||||
) -> fmt::Result {
|
||||
fmt::Debug::fmt(&Self::debug_fmt::<PRegFlagsPowerISA>(value, Some("Pwr")), f)
|
||||
}
|
||||
}
|
||||
|
||||
impl PRegValue {
|
||||
#[hdl]
|
||||
pub fn zeroed() -> Expr<Self> {
|
||||
|
|
@ -848,7 +874,10 @@ impl PRegValue {
|
|||
}
|
||||
}
|
||||
#[hdl]
|
||||
pub fn debug_fmt<V: PRegFlagsViewTrait>(this: &SimValue<Self>) -> impl fmt::Debug {
|
||||
pub fn debug_fmt<V: PRegFlagsViewTrait>(
|
||||
this: &<Self as Type>::SimValue,
|
||||
flags_type_name: Option<&str>,
|
||||
) -> impl fmt::Debug {
|
||||
fmt::from_fn(move |f| {
|
||||
#[hdl(sim)]
|
||||
let Self { int_fp, flags } = this;
|
||||
|
|
@ -856,19 +885,26 @@ impl PRegValue {
|
|||
.field("int_fp", int_fp)
|
||||
.field(
|
||||
"flags",
|
||||
&fmt::from_fn(|f| PRegFlags::debug_fmt::<V>(flags, f)),
|
||||
&fmt::from_fn(|f| PRegFlags::debug_fmt::<V>(flags, flags_type_name, f)),
|
||||
)
|
||||
.finish()
|
||||
})
|
||||
}
|
||||
#[hdl]
|
||||
pub fn debug_fmt_mode(this: &SimValue<Self>, mode: &SimValue<FlagsMode>) -> impl fmt::Debug {
|
||||
pub fn debug_fmt_mode(
|
||||
this: &SimValue<Self>,
|
||||
flags_short_name: bool,
|
||||
mode: &SimValue<FlagsMode>,
|
||||
) -> impl fmt::Debug {
|
||||
fmt::from_fn(move |f| {
|
||||
#[hdl(sim)]
|
||||
let Self { int_fp, flags } = this;
|
||||
f.debug_struct("PRegValue")
|
||||
.field("int_fp", int_fp)
|
||||
.field("flags", &PRegFlags::debug_fmt_mode(flags, mode))
|
||||
.field(
|
||||
"flags",
|
||||
&PRegFlags::debug_fmt_mode(flags, flags_short_name, mode),
|
||||
)
|
||||
.finish()
|
||||
})
|
||||
}
|
||||
|
|
|
|||
|
|
@ -6,8 +6,8 @@
|
|||
|
||||
use crate::{
|
||||
config::{
|
||||
CpuConfig, CpuConfig2PowOutRegNumWidth, CpuConfigFetchWidth, CpuConfigPRegNumWidth,
|
||||
CpuConfigRobSize, CpuConfigUnitCount, PhantomConstCpuConfig, TwiceCpuConfigFetchWidth,
|
||||
CpuConfig, CpuConfig2PowOutRegNumWidth, CpuConfigFetchWidth, CpuConfigRobSize,
|
||||
CpuConfigUnitCount, PhantomConstCpuConfig, TwiceCpuConfigFetchWidth,
|
||||
},
|
||||
instruction::{
|
||||
COMMON_MOP_SRC_LEN, L2RegNum, L2RegisterFileMOp, MOp, MOpDestReg, MOpRegNum, MOpTrait,
|
||||
|
|
@ -118,10 +118,7 @@ pub struct RetireToNextPcInterface<C: PhantomConstGet<CpuConfig>> {
|
|||
|
||||
#[hdl]
|
||||
pub type RenamedMOp<C: PhantomConstGet<CpuConfig>> =
|
||||
crate::instruction::RenamedMOp<PRegNum<C>, CpuConfigPRegNumWidth<C>>;
|
||||
|
||||
#[hdl]
|
||||
pub type RenamedSrcRegUInt<C: PhantomConstGet<CpuConfig>> = UIntType<CpuConfigPRegNumWidth<C>>;
|
||||
crate::instruction::RenamedMOp<PRegNum<C>, PRegNum<C>>;
|
||||
|
||||
/// Enqueues happen in program order, they are not re-ordered by out-of-order execution.
|
||||
/// the whole `MOpInstance` is sent again in [`UnitInputsReady`] so Units can just ignore all
|
||||
|
|
@ -573,7 +570,7 @@ struct RobEntryDebugState<C: PhantomConstGet<CpuConfig>> {
|
|||
mop: MOpInstance<RenamedMOp<C>>,
|
||||
mop_in_unit_state: SimOnlyMOpInUnitState,
|
||||
is_speculative: Bool,
|
||||
finished: HdlOption<NextPcPredictorOp<C>>,
|
||||
output: HdlOption<NextPcPredictorOp<C>>,
|
||||
caused_cancel: HdlOption<UnitCausedCancel<C>>,
|
||||
}
|
||||
|
||||
|
|
@ -584,7 +581,7 @@ impl<C: PhantomConstCpuConfig> SimValueDefault for RobEntryDebugState<C> {
|
|||
mop,
|
||||
mop_in_unit_state: _,
|
||||
is_speculative: _,
|
||||
finished,
|
||||
output,
|
||||
caused_cancel,
|
||||
} = self;
|
||||
#[hdl(sim)]
|
||||
|
|
@ -592,8 +589,8 @@ impl<C: PhantomConstCpuConfig> SimValueDefault for RobEntryDebugState<C> {
|
|||
mop: zeroed(mop),
|
||||
mop_in_unit_state: SimOnlyValue::default(),
|
||||
is_speculative: false,
|
||||
finished: #[hdl(sim)]
|
||||
finished.HdlNone(),
|
||||
output: #[hdl(sim)]
|
||||
output.HdlNone(),
|
||||
caused_cancel: #[hdl(sim)]
|
||||
caused_cancel.HdlNone(),
|
||||
}
|
||||
|
|
@ -605,7 +602,7 @@ struct RobEntry<C: PhantomConstCpuConfig> {
|
|||
mop: SimValue<MOpInstance<RenamedMOp<C>>>,
|
||||
mop_in_unit_state: MOpInUnitState,
|
||||
is_speculative: bool,
|
||||
finished: Option<SimValue<NextPcPredictorOp<C>>>,
|
||||
output: Option<SimValue<NextPcPredictorOp<C>>>,
|
||||
caused_cancel: Option<SimValue<UnitCausedCancel<C>>>,
|
||||
}
|
||||
|
||||
|
|
@ -615,7 +612,7 @@ impl<C: PhantomConstCpuConfig> RobEntry<C> {
|
|||
mop,
|
||||
mop_in_unit_state: MOpInUnitState::NotYetEnqueued,
|
||||
is_speculative: true,
|
||||
finished: None,
|
||||
output: None,
|
||||
caused_cancel: None,
|
||||
}
|
||||
}
|
||||
|
|
@ -640,7 +637,7 @@ impl<C: PhantomConstCpuConfig> RobEntry<C> {
|
|||
mop,
|
||||
mop_in_unit_state,
|
||||
is_speculative,
|
||||
finished,
|
||||
output,
|
||||
caused_cancel,
|
||||
} = self;
|
||||
let ret_ty = RobEntryDebugState[config];
|
||||
|
|
@ -649,7 +646,7 @@ impl<C: PhantomConstCpuConfig> RobEntry<C> {
|
|||
mop,
|
||||
mop_in_unit_state: SimOnlyValue::new(*mop_in_unit_state),
|
||||
is_speculative,
|
||||
finished: finished.into_sim_value_with_type(ret_ty.finished),
|
||||
output: output.into_sim_value_with_type(ret_ty.output),
|
||||
caused_cancel: caused_cancel.into_sim_value_with_type(ret_ty.caused_cancel),
|
||||
}
|
||||
}
|
||||
|
|
@ -1047,8 +1044,8 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
|
|||
let masked_id = rob.mop.id.as_int() as usize & mask;
|
||||
**retval[masked_id] = fmt::from_fn(|f| {
|
||||
f.write_str(rob.mop_in_unit_state.debug_str())?;
|
||||
if rob.finished.is_some() {
|
||||
f.write_str("(finished)")?;
|
||||
if rob.output.is_some() {
|
||||
f.write_str("(output)")?;
|
||||
}
|
||||
if rob.caused_cancel.is_some() {
|
||||
f.write_str("(caused cancel)")?;
|
||||
|
|
@ -1170,7 +1167,7 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
|
|||
let PRegNum::<_> {
|
||||
unit_num,
|
||||
unit_out_reg,
|
||||
} = src_reg.cast_bits_to(PRegNum[self.config]);
|
||||
} = src_reg;
|
||||
if Some(unit_index) == UnitNum::index_sim(&unit_num) {
|
||||
allocated_regs[UnitOutRegNum::value_sim(&unit_out_reg)] = true;
|
||||
}
|
||||
|
|
@ -1247,22 +1244,26 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
|
|||
&mut self,
|
||||
insn: SimValue<MOpInstance<MOp>>,
|
||||
) -> Result<(), SimValue<MOpInstance<MOp>>> {
|
||||
println!("try_rename: insn: {insn:?}");
|
||||
if self.rob.unrenamed_len() >= self.config.get().rob_size.get() {
|
||||
println!("try_rename: unrenamed_len >= rob_size");
|
||||
return Err(insn);
|
||||
}
|
||||
if self.rob.renamed_len() >= self.config.get().rob_size.get() {
|
||||
println!("try_rename: renamed_len >= rob_size");
|
||||
return Err(insn);
|
||||
}
|
||||
let unit_kind = UnitMOp::kind_sim(&insn.mop);
|
||||
#[hdl(sim)]
|
||||
if let MOp::TransformedMove(move_reg_mop) = &insn.mop {
|
||||
let mut src_regs = [MOpRegNum::CONST_ZERO_REG_NUM; 1];
|
||||
let mut src_regs = [MOpRegNum::const_zero_sim()];
|
||||
MOpTrait::for_each_src_reg_sim_ref(move_reg_mop, &mut |src_reg, index| {
|
||||
src_regs[index] = src_reg.as_int() as u32;
|
||||
src_regs[index] = src_reg.clone();
|
||||
});
|
||||
let [src_reg] = src_regs;
|
||||
let renamed_reg = self.rename_table.entries[src_reg as usize].clone();
|
||||
println!("moving from {src_reg:#x} renamed: {renamed_reg:?}");
|
||||
let renamed_reg =
|
||||
self.rename_table.entries[MOpRegNum::reg_num_sim(&src_reg) as usize].clone();
|
||||
println!("moving from {src_reg:?} renamed: {renamed_reg:?}");
|
||||
let unrenamed_dest_regs =
|
||||
MOpDestReg::regs_sim(MOpTrait::dest_reg_sim_ref(move_reg_mop));
|
||||
assert!(self.rob.incomplete_back_entry.is_none());
|
||||
|
|
@ -1325,9 +1326,11 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
|
|||
);
|
||||
};
|
||||
if space_available == 0 {
|
||||
println!("try_rename: space_available = 0");
|
||||
return Err(insn);
|
||||
}
|
||||
let Some(out_reg_num) = out_reg_num else {
|
||||
println!("try_rename: out_reg_num = None");
|
||||
return if self.space_available_for_unit(self.l2_reg_file_unit_index) > 0
|
||||
&& let Some(l2_reg_index) = self.find_free_l2_reg()
|
||||
{
|
||||
|
|
@ -1358,19 +1361,16 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
|
|||
let mop = MOpTrait::map_regs_sim(
|
||||
mop,
|
||||
&renamed_dest_reg,
|
||||
CpuConfigPRegNumWidth[self.config],
|
||||
PRegNum[self.config],
|
||||
&mut |src_reg, index| {
|
||||
let renamed = &self.rename_table.entries[src_reg.as_int() as usize];
|
||||
let renamed = &self.rename_table.entries[MOpRegNum::reg_num_sim(&src_reg) as usize];
|
||||
println!("renaming src[{index}] from {src_reg:?} to {renamed:?}");
|
||||
#[hdl(sim)]
|
||||
match renamed {
|
||||
RenameTableEntry::<_>::L1(v) => v.cast_to_bits(),
|
||||
RenameTableEntry::<_>::L1(v) => v.clone(),
|
||||
RenameTableEntry::<_>::L2(v) => {
|
||||
needed_load.get_or_insert_with(|| v.clone());
|
||||
PRegNum[self.config]
|
||||
.const_zero()
|
||||
.cast_to_bits()
|
||||
.into_sim_value()
|
||||
PRegNum[self.config].const_zero_sim()
|
||||
}
|
||||
}
|
||||
},
|
||||
|
|
@ -1405,7 +1405,7 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
|
|||
is_last_mop_in_insn,
|
||||
mop: ReadL2RegMOp::read_l2_reg::<RenamedMOp<C>>(
|
||||
dest,
|
||||
repeat(RenamedSrcRegUInt[self.config].zero(), ConstUsize),
|
||||
repeat(PRegNum[self.config].const_zero_sim(), ConstUsize),
|
||||
needed_load,
|
||||
),
|
||||
},
|
||||
|
|
@ -1413,6 +1413,7 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
|
|||
);
|
||||
Ok(())
|
||||
} else {
|
||||
println!("try_rename: l2 reg file has no space and/or has no free output regs");
|
||||
Err(insn)
|
||||
};
|
||||
}
|
||||
|
|
@ -1494,7 +1495,6 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
|
|||
let mut src_values: [_; COMMON_MOP_SRC_LEN] =
|
||||
std::array::from_fn(|_| Some(zero_value.clone()));
|
||||
MOpTrait::for_each_src_reg_sim_ref(&rob.mop.mop, &mut |src_reg, index| {
|
||||
let src_reg = src_reg.cast_bits_to(zero_reg.ty());
|
||||
#[hdl(sim)]
|
||||
let PRegNum::<_> {
|
||||
unit_num,
|
||||
|
|
@ -1505,7 +1505,7 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
|
|||
[UnitOutRegNum::value_sim(unit_out_reg)]
|
||||
.clone();
|
||||
} else {
|
||||
assert_eq!(src_reg, zero_reg);
|
||||
assert_eq!(*src_reg, zero_reg);
|
||||
src_values[index] = Some(zeroed(PRegValue));
|
||||
}
|
||||
});
|
||||
|
|
@ -1573,15 +1573,15 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
|
|||
mop: _,
|
||||
mop_in_unit_state,
|
||||
is_speculative: _,
|
||||
finished,
|
||||
output,
|
||||
caused_cancel,
|
||||
} = rob;
|
||||
assert!(finished.is_none());
|
||||
assert!(output.is_none());
|
||||
assert!(caused_cancel.is_none());
|
||||
let l1_reg = &mut self.l1_reg_file[unit_index][out_reg_index];
|
||||
assert!(l1_reg.is_none());
|
||||
*l1_reg = Some(dest_value);
|
||||
*finished = Some(predictor_op);
|
||||
*output = Some(predictor_op);
|
||||
*mop_in_unit_state = mop_in_unit_state
|
||||
.after_output_ready()
|
||||
.expect("should be valid state for output to become ready");
|
||||
|
|
@ -1602,7 +1602,7 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
|
|||
mop: _,
|
||||
mop_in_unit_state,
|
||||
is_speculative: _,
|
||||
finished,
|
||||
output,
|
||||
caused_cancel,
|
||||
} = self.rob.renamed_by_id_mut(&id);
|
||||
assert!(caused_cancel.is_none());
|
||||
|
|
@ -1622,7 +1622,7 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
|
|||
panic!(
|
||||
"MOp {id:?} made an invalid attempt to finish/cause a cancel:\n\
|
||||
mop_in_unit_state={mop_in_unit_state:?}\n\
|
||||
finished={finished:?}\n\
|
||||
output={output:?}\n\
|
||||
caused_cancel={caused_cancel:?}"
|
||||
);
|
||||
}
|
||||
|
|
@ -1642,10 +1642,10 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
|
|||
}
|
||||
}
|
||||
fn handle_from_post_decode(&mut self, insns: &[SimValue<MOpInstance<MOp>>]) {
|
||||
if insns.is_empty() {
|
||||
if self.is_canceling() {
|
||||
assert!(insns.is_empty());
|
||||
return;
|
||||
}
|
||||
assert!(!self.is_canceling());
|
||||
for insn in insns {
|
||||
self.rename_delayed.push_back(insn.clone());
|
||||
}
|
||||
|
|
@ -1701,7 +1701,7 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
|
|||
mop: _,
|
||||
mop_in_unit_state: MOpInUnitState::FinishedAndOrCausedCancel,
|
||||
is_speculative: _,
|
||||
finished,
|
||||
output,
|
||||
caused_cancel,
|
||||
} = renamed_entry
|
||||
{
|
||||
|
|
@ -1709,7 +1709,7 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
|
|||
// only the part before the cancel needs to be ready
|
||||
break;
|
||||
}
|
||||
assert!(finished.is_some());
|
||||
assert!(output.is_some());
|
||||
} else {
|
||||
// group isn't ready
|
||||
return retval;
|
||||
|
|
@ -1746,7 +1746,7 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
|
|||
config: self.config,
|
||||
};
|
||||
for renamed in renamed_entries {
|
||||
let Some(finished) = &renamed.finished else {
|
||||
let Some(output) = &renamed.output else {
|
||||
unreachable!();
|
||||
};
|
||||
#[hdl(sim)]
|
||||
|
|
@ -1754,7 +1754,7 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
|
|||
call_stack_op,
|
||||
cond_br_taken,
|
||||
config: _,
|
||||
} = finished;
|
||||
} = output;
|
||||
#[hdl(sim)]
|
||||
if let CallStackOp::None = &unrenamed_op.call_stack_op {
|
||||
unrenamed_op.call_stack_op = call_stack_op.clone();
|
||||
|
|
@ -1832,7 +1832,7 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
|
|||
mop: _,
|
||||
mop_in_unit_state,
|
||||
is_speculative: _,
|
||||
finished: _,
|
||||
output: _,
|
||||
caused_cancel,
|
||||
} in renamed_entries
|
||||
{
|
||||
|
|
@ -1885,7 +1885,7 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
|
|||
mop: _,
|
||||
mop_in_unit_state: MOpInUnitState::FinishedAndOrCausedCancel,
|
||||
is_speculative: _,
|
||||
finished: _,
|
||||
output: _,
|
||||
caused_cancel: Some(caused_cancel),
|
||||
}) = first_renamed
|
||||
&& !*caused_cancel.cancel_after_retire
|
||||
|
|
@ -1995,10 +1995,10 @@ async fn rename_execute_retire_run(
|
|||
mop: _,
|
||||
mop_in_unit_state,
|
||||
is_speculative: _,
|
||||
finished,
|
||||
output,
|
||||
caused_cancel,
|
||||
} = state.rob.renamed_by_id_mut(&enqueue.mop.id);
|
||||
assert!(finished.is_none());
|
||||
assert!(output.is_none());
|
||||
assert!(caused_cancel.is_none());
|
||||
*mop_in_unit_state = mop_in_unit_state
|
||||
.after_enqueue()
|
||||
|
|
@ -2012,10 +2012,10 @@ async fn rename_execute_retire_run(
|
|||
mop: _,
|
||||
mop_in_unit_state,
|
||||
is_speculative: _,
|
||||
finished,
|
||||
output,
|
||||
caused_cancel,
|
||||
} = state.rob.renamed_by_id_mut(&inputs_ready.mop.id);
|
||||
assert!(finished.is_none());
|
||||
assert!(output.is_none());
|
||||
assert!(caused_cancel.is_none());
|
||||
*mop_in_unit_state = mop_in_unit_state
|
||||
.with_inputs_ready()
|
||||
|
|
@ -2030,11 +2030,9 @@ async fn rename_execute_retire_run(
|
|||
mop: _,
|
||||
mop_in_unit_state,
|
||||
is_speculative: _,
|
||||
finished,
|
||||
caused_cancel,
|
||||
output: _,
|
||||
caused_cancel: _,
|
||||
} = state.rob.renamed_by_id_mut(&is_no_longer_speculative.id);
|
||||
assert!(finished.is_none());
|
||||
assert!(caused_cancel.is_none());
|
||||
*mop_in_unit_state = mop_in_unit_state
|
||||
.without_speculative()
|
||||
.expect("UnitMOpIsNoLongerSpeculative is known to be valid");
|
||||
|
|
@ -2049,10 +2047,9 @@ async fn rename_execute_retire_run(
|
|||
mop: _,
|
||||
mop_in_unit_state,
|
||||
is_speculative: _,
|
||||
finished,
|
||||
output: _,
|
||||
caused_cancel,
|
||||
} = state.rob.renamed_by_id_mut(&id);
|
||||
assert!(finished.is_none());
|
||||
assert!(caused_cancel.is_none());
|
||||
*mop_in_unit_state = mop_in_unit_state
|
||||
.with_cant_cause_cancel()
|
||||
|
|
|
|||
|
|
@ -5,8 +5,8 @@ use crate::{
|
|||
config::{CpuConfig, PhantomConstCpuConfig},
|
||||
instruction::{
|
||||
AluBranchMOp, LoadStoreMOp, MOp, MOpDestReg, MOpInto, MOpRegNum, MOpTrait,
|
||||
MOpVariantVisitOps, MOpVariantVisitor, MOpVisitVariants, RenamedMOp, UnitOutRegNum,
|
||||
mop_enum,
|
||||
MOpVariantVisitOps, MOpVariantVisitor, MOpVisitVariants, PRegNum, RenamedMOp,
|
||||
UnitOutRegNum, mop_enum,
|
||||
},
|
||||
register::{FlagsMode, PRegValue},
|
||||
unit::unit_base::UnitToRegAlloc,
|
||||
|
|
@ -28,7 +28,7 @@ macro_rules! all_units {
|
|||
#[unit_kind = $UnitKind:ident]
|
||||
#[hdl(custom_debug(sim))]
|
||||
$(#[$enum_meta:meta])*
|
||||
$vis:vis enum $UnitMOpEnum:ident<$DestReg:ident: Type, $SrcRegWidth:ident: Size, #[MOp(get_ty = $transformed_move_op_get_ty:expr)] $TransformedMoveOp:ident: Type> {
|
||||
$vis:vis enum $UnitMOpEnum:ident<$DestReg:ident: Type, $SrcReg:ident: Type, #[MOp(get_ty = $transformed_move_op_get_ty:expr)] $TransformedMoveOp:ident: Type> {
|
||||
$(
|
||||
$(#[transformed_move $($transformed_move:tt)*])?
|
||||
#[create_dyn_unit_fn = $create_dyn_unit_fn:expr]
|
||||
|
|
@ -87,11 +87,11 @@ macro_rules! all_units {
|
|||
$(#[$enum_meta])*
|
||||
$vis enum $UnitMOpEnum<
|
||||
$DestReg: Type,
|
||||
$SrcRegWidth: Size,
|
||||
$SrcReg: Type,
|
||||
#[MOp(get_ty = $transformed_move_op_get_ty)] $TransformedMoveOp: Type,
|
||||
#[MOpVisitVariants] [
|
||||
$TransformedMoveOp: MOpVisitVariants<DestReg = $DestReg, SrcRegWidth = $SrcRegWidth>,
|
||||
$($Op: MOpVisitVariants<DestReg = $DestReg, SrcRegWidth = $SrcRegWidth>,)*
|
||||
$TransformedMoveOp: MOpVisitVariants<DestReg = $DestReg, SrcReg = $SrcReg>,
|
||||
$($Op: MOpVisitVariants<DestReg = $DestReg, SrcReg = $SrcReg>,)*
|
||||
]
|
||||
> {
|
||||
$(
|
||||
|
|
@ -101,7 +101,7 @@ macro_rules! all_units {
|
|||
}
|
||||
}
|
||||
|
||||
impl<$DestReg: Type, $SrcRegWidth: Size, $TransformedMoveOp: Type> $UnitMOpEnum<$DestReg, $SrcRegWidth, $TransformedMoveOp> {
|
||||
impl<$DestReg: Type, $SrcReg: Type, $TransformedMoveOp: Type> $UnitMOpEnum<$DestReg, $SrcReg, $TransformedMoveOp> {
|
||||
#[hdl]
|
||||
$vis fn kind(expr: impl ToExpr<Type = Self>) -> Expr<$HdlUnitKind> {
|
||||
#[hdl]
|
||||
|
|
@ -164,18 +164,18 @@ macro_rules! all_units {
|
|||
}
|
||||
}
|
||||
)*
|
||||
$vis fn with_transformed_move_op_ty<T>(self, new_transformed_move_op_ty: T) -> $UnitMOpEnum<$DestReg, $SrcRegWidth, T>
|
||||
$vis fn with_transformed_move_op_ty<T>(self, new_transformed_move_op_ty: T) -> $UnitMOpEnum<$DestReg, $SrcReg, T>
|
||||
where
|
||||
T: MOpTrait<DestReg = $DestReg, SrcRegWidth = $SrcRegWidth>,
|
||||
$TransformedMoveOp: MOpTrait<DestReg = $DestReg, SrcRegWidth = $SrcRegWidth>,
|
||||
T: MOpTrait<DestReg = $DestReg, SrcReg = $SrcReg>,
|
||||
$TransformedMoveOp: MOpTrait<DestReg = $DestReg, SrcReg = $SrcReg>,
|
||||
{
|
||||
$UnitMOpEnum[self.dest_reg_ty()][self.src_reg_width()][new_transformed_move_op_ty]
|
||||
$UnitMOpEnum[self.dest_reg_ty()][self.src_reg_ty()][new_transformed_move_op_ty]
|
||||
}
|
||||
}
|
||||
|
||||
all_units! {
|
||||
@split_by_transformed_move
|
||||
$vis enum $UnitMOpEnum<$DestReg: Type, $SrcRegWidth: Size, $TransformedMoveOp: Type> {
|
||||
$vis enum $UnitMOpEnum<$DestReg: Type, $SrcReg: Type, $TransformedMoveOp: Type> {
|
||||
$(
|
||||
$(#[transformed_move $($transformed_move)*])?
|
||||
$Unit($Op),
|
||||
|
|
@ -200,23 +200,23 @@ macro_rules! all_units {
|
|||
};
|
||||
(
|
||||
@split_by_transformed_move
|
||||
$vis:vis enum $UnitMOpEnum:ident<$DestReg:ident: Type, $SrcRegWidth:ident: Size, $TransformedMoveOp:ident: Type> {
|
||||
$vis:vis enum $UnitMOpEnum:ident<$DestReg:ident: Type, $SrcReg:ident: Type, $TransformedMoveOp:ident: Type> {
|
||||
$($BeforeUnit:ident($BeforeOp:ty),)*
|
||||
#[transformed_move]
|
||||
$TransformedMove:ident($TransformedMoveOp2:ty),
|
||||
$($AfterUnit:ident($AfterOp:ty),)*
|
||||
}
|
||||
) => {
|
||||
impl<$DestReg: Type, $SrcRegWidth: Size, $TransformedMoveOp: Type> $UnitMOpEnum<$DestReg, $SrcRegWidth, $TransformedMoveOp> {
|
||||
impl<$DestReg: Type, $SrcReg: Type, $TransformedMoveOp: Type> $UnitMOpEnum<$DestReg, $SrcReg, $TransformedMoveOp> {
|
||||
#[hdl]
|
||||
$vis fn try_with_transformed_move_op<T>(
|
||||
this: impl ToExpr<Type = Self>,
|
||||
new_transformed_move_op_ty: T,
|
||||
connect_transformed_move_op: impl FnOnce(Expr<HdlOption<$UnitMOpEnum<$DestReg, $SrcRegWidth, T>>>, Expr<$TransformedMoveOp>),
|
||||
) -> Expr<HdlOption<$UnitMOpEnum<$DestReg, $SrcRegWidth, T>>>
|
||||
connect_transformed_move_op: impl FnOnce(Expr<HdlOption<$UnitMOpEnum<$DestReg, $SrcReg, T>>>, Expr<$TransformedMoveOp>),
|
||||
) -> Expr<HdlOption<$UnitMOpEnum<$DestReg, $SrcReg, T>>>
|
||||
where
|
||||
T: MOpTrait<DestReg = $DestReg, SrcRegWidth = $SrcRegWidth>,
|
||||
$TransformedMoveOp: MOpTrait<DestReg = $DestReg, SrcRegWidth = $SrcRegWidth>,
|
||||
T: MOpTrait<DestReg = $DestReg, SrcReg = $SrcReg>,
|
||||
$TransformedMoveOp: MOpTrait<DestReg = $DestReg, SrcReg = $SrcReg>,
|
||||
{
|
||||
let this = this.to_expr();
|
||||
let new_ty = this.ty().with_transformed_move_op_ty(new_transformed_move_op_ty);
|
||||
|
|
@ -237,11 +237,11 @@ macro_rules! all_units {
|
|||
$vis fn try_with_transformed_move_op_sim<T, E>(
|
||||
this: impl ToSimValue<Type = Self>,
|
||||
new_transformed_move_op_ty: T,
|
||||
f: impl FnOnce(SimValue<$TransformedMoveOp>) -> Result<SimValue<$UnitMOpEnum<$DestReg, $SrcRegWidth, T>>, E>,
|
||||
) -> Result<SimValue<$UnitMOpEnum<$DestReg, $SrcRegWidth, T>>, E>
|
||||
f: impl FnOnce(SimValue<$TransformedMoveOp>) -> Result<SimValue<$UnitMOpEnum<$DestReg, $SrcReg, T>>, E>,
|
||||
) -> Result<SimValue<$UnitMOpEnum<$DestReg, $SrcReg, T>>, E>
|
||||
where
|
||||
T: MOpTrait<DestReg = $DestReg, SrcRegWidth = $SrcRegWidth>,
|
||||
$TransformedMoveOp: MOpTrait<DestReg = $DestReg, SrcRegWidth = $SrcRegWidth>,
|
||||
T: MOpTrait<DestReg = $DestReg, SrcReg = $SrcReg>,
|
||||
$TransformedMoveOp: MOpTrait<DestReg = $DestReg, SrcReg = $SrcReg>,
|
||||
{
|
||||
#![allow(unreachable_patterns)]
|
||||
let this = this.into_sim_value();
|
||||
|
|
@ -263,11 +263,11 @@ macro_rules! all_units {
|
|||
$vis fn with_transformed_move_op_sim<T>(
|
||||
this: impl ToSimValue<Type = Self>,
|
||||
new_transformed_move_op_ty: T,
|
||||
f: impl FnOnce(SimValue<$TransformedMoveOp>) -> SimValue<$UnitMOpEnum<$DestReg, $SrcRegWidth, T>>,
|
||||
) -> SimValue<$UnitMOpEnum<$DestReg, $SrcRegWidth, T>>
|
||||
f: impl FnOnce(SimValue<$TransformedMoveOp>) -> SimValue<$UnitMOpEnum<$DestReg, $SrcReg, T>>,
|
||||
) -> SimValue<$UnitMOpEnum<$DestReg, $SrcReg, T>>
|
||||
where
|
||||
T: MOpTrait<DestReg = $DestReg, SrcRegWidth = $SrcRegWidth>,
|
||||
$TransformedMoveOp: MOpTrait<DestReg = $DestReg, SrcRegWidth = $SrcRegWidth>,
|
||||
T: MOpTrait<DestReg = $DestReg, SrcReg = $SrcReg>,
|
||||
$TransformedMoveOp: MOpTrait<DestReg = $DestReg, SrcReg = $SrcReg>,
|
||||
{
|
||||
let Ok::<_, std::convert::Infallible>(retval) = Self::try_with_transformed_move_op_sim(this, new_transformed_move_op_ty, move |v| Ok(f(v)));
|
||||
retval
|
||||
|
|
@ -277,7 +277,7 @@ macro_rules! all_units {
|
|||
const _: () = {
|
||||
#[hdl]
|
||||
type $DestReg = MOpDestReg;
|
||||
type $SrcRegWidth = ConstUsize<{ MOpRegNum::WIDTH }>;
|
||||
type $SrcReg = MOpRegNum;
|
||||
|
||||
$(impl MOpInto<MOp> for $BeforeOp {
|
||||
fn mop_into_ty(self) -> MOp {
|
||||
|
|
@ -298,21 +298,21 @@ macro_rules! all_units {
|
|||
})*
|
||||
};
|
||||
|
||||
$(impl<$DestReg: Type, $SrcRegWidth: Size> MOpInto<RenamedMOp<$DestReg, $SrcRegWidth>> for $BeforeOp {
|
||||
fn mop_into_ty(self) -> RenamedMOp<$DestReg, $SrcRegWidth> {
|
||||
RenamedMOp[MOpTrait::dest_reg_ty(self)][MOpTrait::src_reg_width(self)]
|
||||
$(impl<$DestReg: Type, $SrcReg: Type> MOpInto<RenamedMOp<$DestReg, $SrcReg>> for $BeforeOp {
|
||||
fn mop_into_ty(self) -> RenamedMOp<$DestReg, $SrcReg> {
|
||||
RenamedMOp[MOpTrait::dest_reg_ty(self)][MOpTrait::src_reg_ty(self)]
|
||||
}
|
||||
fn mop_into(this: Expr<Self>) -> Expr<RenamedMOp<$DestReg, $SrcRegWidth>> {
|
||||
MOpInto::<RenamedMOp<$DestReg, $SrcRegWidth>>::mop_into_ty(this.ty()).$BeforeUnit(this)
|
||||
fn mop_into(this: Expr<Self>) -> Expr<RenamedMOp<$DestReg, $SrcReg>> {
|
||||
MOpInto::<RenamedMOp<$DestReg, $SrcReg>>::mop_into_ty(this.ty()).$BeforeUnit(this)
|
||||
}
|
||||
})*
|
||||
|
||||
$(impl<$DestReg: Type, $SrcRegWidth: Size> MOpInto<RenamedMOp<$DestReg, $SrcRegWidth>> for $AfterOp {
|
||||
fn mop_into_ty(self) -> RenamedMOp<$DestReg, $SrcRegWidth> {
|
||||
RenamedMOp[MOpTrait::dest_reg_ty(self)][MOpTrait::src_reg_width(self)]
|
||||
$(impl<$DestReg: Type, $SrcReg: Type> MOpInto<RenamedMOp<$DestReg, $SrcReg>> for $AfterOp {
|
||||
fn mop_into_ty(self) -> RenamedMOp<$DestReg, $SrcReg> {
|
||||
RenamedMOp[MOpTrait::dest_reg_ty(self)][MOpTrait::src_reg_ty(self)]
|
||||
}
|
||||
fn mop_into(this: Expr<Self>) -> Expr<RenamedMOp<$DestReg, $SrcRegWidth>> {
|
||||
MOpInto::<RenamedMOp<$DestReg, $SrcRegWidth>>::mop_into_ty(this.ty()).$AfterUnit(this)
|
||||
fn mop_into(this: Expr<Self>) -> Expr<RenamedMOp<$DestReg, $SrcReg>> {
|
||||
MOpInto::<RenamedMOp<$DestReg, $SrcReg>>::mop_into_ty(this.ty()).$AfterUnit(this)
|
||||
}
|
||||
})*
|
||||
};
|
||||
|
|
@ -324,21 +324,21 @@ all_units! {
|
|||
#[hdl(custom_debug(sim))]
|
||||
pub enum UnitMOp<
|
||||
DestReg: Type,
|
||||
SrcRegWidth: Size,
|
||||
#[MOp(get_ty = |this: UnitMOp<DestReg, SrcRegWidth, TransformedMoveOp>, new_dest_reg, new_src_reg_width| {
|
||||
this.TransformedMove.mapped_ty(new_dest_reg, new_src_reg_width)
|
||||
SrcReg: Type,
|
||||
#[MOp(get_ty = |this: UnitMOp<DestReg, SrcReg, TransformedMoveOp>, new_dest_reg, new_src_reg| {
|
||||
this.TransformedMove.mapped_ty(new_dest_reg, new_src_reg)
|
||||
})] TransformedMoveOp: Type
|
||||
> {
|
||||
#[create_dyn_unit_fn = |config, unit_index| alu_branch::AluBranch::new(config, unit_index).to_dyn()]
|
||||
#[extract(alu_branch_mop, alu_branch_mop_sim, alu_branch_mop_sim_ref, alu_branch_mop_sim_mut)]
|
||||
AluBranch(AluBranchMOp<DestReg, SrcRegWidth>),
|
||||
AluBranch(AluBranchMOp<DestReg, SrcReg>),
|
||||
#[transformed_move]
|
||||
#[create_dyn_unit_fn = |config, unit_index| todo!()]
|
||||
#[extract(transformed_move_mop, transformed_move_mop_sim, transformed_move_mop_sim_ref, transformed_move_mop_sim_mut)]
|
||||
TransformedMove(TransformedMoveOp),
|
||||
#[create_dyn_unit_fn = |config, unit_index| todo!()]
|
||||
#[extract(load_store_mop, load_store_mop_sim, load_store_mop_sim_ref, load_store_mop_sim_mut)]
|
||||
LoadStore(LoadStoreMOp<DestReg, SrcRegWidth>),
|
||||
LoadStore(LoadStoreMOp<DestReg, SrcReg>),
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -408,7 +408,9 @@ pub trait UnitTrait:
|
|||
|
||||
fn extract_mop(
|
||||
&self,
|
||||
mop: Expr<RenamedMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, DynSize>>,
|
||||
mop: Expr<
|
||||
RenamedMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, PRegNum<PhantomConst<CpuConfig>>>,
|
||||
>,
|
||||
) -> Expr<HdlOption<Self::MOp>>;
|
||||
|
||||
fn module(&self) -> Interned<Module<Self::Type>>;
|
||||
|
|
@ -466,7 +468,9 @@ impl UnitTrait for DynUnit {
|
|||
|
||||
fn extract_mop(
|
||||
&self,
|
||||
mop: Expr<RenamedMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, DynSize>>,
|
||||
mop: Expr<
|
||||
RenamedMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, PRegNum<PhantomConst<CpuConfig>>>,
|
||||
>,
|
||||
) -> Expr<HdlOption<Self::MOp>> {
|
||||
self.unit.extract_mop(mop)
|
||||
}
|
||||
|
|
@ -521,7 +525,9 @@ impl<T: UnitTrait + Clone + std::hash::Hash + Eq> UnitTrait for DynUnitWrapper<T
|
|||
|
||||
fn extract_mop(
|
||||
&self,
|
||||
mop: Expr<RenamedMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, DynSize>>,
|
||||
mop: Expr<
|
||||
RenamedMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, PRegNum<PhantomConst<CpuConfig>>>,
|
||||
>,
|
||||
) -> Expr<HdlOption<Self::MOp>> {
|
||||
Expr::from_enum(Expr::as_enum(self.0.extract_mop(mop)))
|
||||
}
|
||||
|
|
|
|||
|
|
@ -5,8 +5,8 @@ use crate::{
|
|||
config::CpuConfig,
|
||||
instruction::{
|
||||
AddSubMOp, AluBranchMOp, AluCommonMOp, BranchMOp, COMMON_MOP_SRC_LEN, CommonMOpDefaultImm,
|
||||
CompareMOp, LogicalFlagsMOp, LogicalMOp, MOpTrait, OutputIntegerMode, ReadSpecialMOp,
|
||||
RenamedMOp, ShiftRotateMOp, UnitOutRegNum,
|
||||
CompareMOp, LogicalFlagsMOp, LogicalMOp, MOpTrait, OutputIntegerMode, PRegNum,
|
||||
ReadSpecialMOp, RenamedMOp, ShiftRotateMOp, UnitOutRegNum,
|
||||
},
|
||||
register::{
|
||||
FlagsMode, PRegFlagsPowerISA, PRegFlagsPowerISAView, PRegFlagsViewTrait, PRegFlagsX86,
|
||||
|
|
@ -25,7 +25,13 @@ use std::{collections::HashMap, ops::RangeTo};
|
|||
|
||||
#[hdl]
|
||||
fn add_sub<SrcCount: KnownSize>(
|
||||
mop: Expr<AddSubMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, DynSize, SrcCount>>,
|
||||
mop: Expr<
|
||||
AddSubMOp<
|
||||
UnitOutRegNum<PhantomConst<CpuConfig>>,
|
||||
PRegNum<PhantomConst<CpuConfig>>,
|
||||
SrcCount,
|
||||
>,
|
||||
>,
|
||||
pc: Expr<UInt<64>>,
|
||||
flags_mode: Expr<FlagsMode>,
|
||||
src_values: Expr<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>,
|
||||
|
|
@ -242,7 +248,9 @@ fn add_sub<SrcCount: KnownSize>(
|
|||
|
||||
#[hdl]
|
||||
fn logical_flags(
|
||||
mop: Expr<LogicalFlagsMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, DynSize>>,
|
||||
mop: Expr<
|
||||
LogicalFlagsMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, PRegNum<PhantomConst<CpuConfig>>>,
|
||||
>,
|
||||
flags_mode: Expr<FlagsMode>,
|
||||
src_values: Expr<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>,
|
||||
) -> Expr<UnitResultCompleted<()>> {
|
||||
|
|
@ -256,7 +264,13 @@ fn logical_flags(
|
|||
|
||||
#[hdl]
|
||||
fn logical(
|
||||
mop: Expr<LogicalMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, DynSize, ConstUsize<2>>>,
|
||||
mop: Expr<
|
||||
LogicalMOp<
|
||||
UnitOutRegNum<PhantomConst<CpuConfig>>,
|
||||
PRegNum<PhantomConst<CpuConfig>>,
|
||||
ConstUsize<2>,
|
||||
>,
|
||||
>,
|
||||
flags_mode: Expr<FlagsMode>,
|
||||
src_values: Expr<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>,
|
||||
) -> Expr<UnitResultCompleted<()>> {
|
||||
|
|
@ -270,7 +284,13 @@ fn logical(
|
|||
|
||||
#[hdl]
|
||||
fn logical_i(
|
||||
mop: Expr<LogicalMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, DynSize, ConstUsize<1>>>,
|
||||
mop: Expr<
|
||||
LogicalMOp<
|
||||
UnitOutRegNum<PhantomConst<CpuConfig>>,
|
||||
PRegNum<PhantomConst<CpuConfig>>,
|
||||
ConstUsize<1>,
|
||||
>,
|
||||
>,
|
||||
flags_mode: Expr<FlagsMode>,
|
||||
src_values: Expr<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>,
|
||||
) -> Expr<UnitResultCompleted<()>> {
|
||||
|
|
@ -284,7 +304,9 @@ fn logical_i(
|
|||
|
||||
#[hdl]
|
||||
fn shift_rotate(
|
||||
mop: Expr<ShiftRotateMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, DynSize>>,
|
||||
mop: Expr<
|
||||
ShiftRotateMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, PRegNum<PhantomConst<CpuConfig>>>,
|
||||
>,
|
||||
flags_mode: Expr<FlagsMode>,
|
||||
src_values: Expr<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>,
|
||||
) -> Expr<UnitResultCompleted<()>> {
|
||||
|
|
@ -298,7 +320,13 @@ fn shift_rotate(
|
|||
|
||||
#[hdl]
|
||||
fn compare<SrcCount: KnownSize>(
|
||||
mop: Expr<CompareMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, DynSize, SrcCount>>,
|
||||
mop: Expr<
|
||||
CompareMOp<
|
||||
UnitOutRegNum<PhantomConst<CpuConfig>>,
|
||||
PRegNum<PhantomConst<CpuConfig>>,
|
||||
SrcCount,
|
||||
>,
|
||||
>,
|
||||
flags_mode: Expr<FlagsMode>,
|
||||
src_values: Expr<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>,
|
||||
) -> Expr<UnitResultCompleted<()>> {
|
||||
|
|
@ -312,7 +340,13 @@ fn compare<SrcCount: KnownSize>(
|
|||
|
||||
#[hdl]
|
||||
fn branch<SrcCount: KnownSize>(
|
||||
mop: Expr<BranchMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, DynSize, SrcCount>>,
|
||||
mop: Expr<
|
||||
BranchMOp<
|
||||
UnitOutRegNum<PhantomConst<CpuConfig>>,
|
||||
PRegNum<PhantomConst<CpuConfig>>,
|
||||
SrcCount,
|
||||
>,
|
||||
>,
|
||||
pc: Expr<UInt<64>>,
|
||||
flags_mode: Expr<FlagsMode>,
|
||||
src_values: Expr<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>,
|
||||
|
|
@ -327,7 +361,9 @@ fn branch<SrcCount: KnownSize>(
|
|||
|
||||
#[hdl]
|
||||
fn read_special(
|
||||
mop: Expr<ReadSpecialMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, DynSize>>,
|
||||
mop: Expr<
|
||||
ReadSpecialMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, PRegNum<PhantomConst<CpuConfig>>>,
|
||||
>,
|
||||
pc: Expr<UInt<64>>,
|
||||
flags_mode: Expr<FlagsMode>,
|
||||
src_values: Expr<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>,
|
||||
|
|
@ -347,12 +383,9 @@ pub fn alu_branch(config: PhantomConst<CpuConfig>, unit_index: usize) {
|
|||
#[hdl]
|
||||
let unit_to_reg_alloc: UnitToRegAlloc<
|
||||
PhantomConst<CpuConfig>,
|
||||
AluBranchMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, DynSize>,
|
||||
AluBranchMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, PRegNum<PhantomConst<CpuConfig>>>,
|
||||
(),
|
||||
> = m.output(
|
||||
UnitToRegAlloc[config][AluBranchMOp[UnitOutRegNum[config]][config.get().p_reg_num_width()]]
|
||||
[()],
|
||||
);
|
||||
> = m.output(UnitToRegAlloc[config][AluBranchMOp[UnitOutRegNum[config]][PRegNum[config]]][()]);
|
||||
#[hdl]
|
||||
let global_state: GlobalState = m.input();
|
||||
|
||||
|
|
@ -592,7 +625,8 @@ impl AluBranch {
|
|||
impl UnitTrait for AluBranch {
|
||||
type Type = alu_branch;
|
||||
type ExtraOut = ();
|
||||
type MOp = AluBranchMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, DynSize>;
|
||||
type MOp =
|
||||
AluBranchMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, PRegNum<PhantomConst<CpuConfig>>>;
|
||||
|
||||
fn ty(&self) -> Self::Type {
|
||||
self.module.io_ty()
|
||||
|
|
@ -612,7 +646,9 @@ impl UnitTrait for AluBranch {
|
|||
|
||||
fn extract_mop(
|
||||
&self,
|
||||
mop: Expr<RenamedMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, DynSize>>,
|
||||
mop: Expr<
|
||||
RenamedMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, PRegNum<PhantomConst<CpuConfig>>>,
|
||||
>,
|
||||
) -> Expr<HdlOption<Self::MOp>> {
|
||||
UnitMOp::alu_branch_mop(mop)
|
||||
}
|
||||
|
|
|
|||
|
|
@ -234,7 +234,11 @@ impl InFlightOpsSummary<DynSize> {
|
|||
|
||||
#[hdl_module]
|
||||
pub fn unit_base<
|
||||
MOp: Type + MOpTrait<DestReg = UnitOutRegNum<PhantomConst<CpuConfig>>, SrcRegWidth = DynSize>,
|
||||
MOp: Type
|
||||
+ MOpTrait<
|
||||
DestReg = UnitOutRegNum<PhantomConst<CpuConfig>>,
|
||||
SrcReg = PRegNum<PhantomConst<CpuConfig>>,
|
||||
>,
|
||||
ExtraOut: Type,
|
||||
>(
|
||||
config: PhantomConst<CpuConfig>,
|
||||
|
|
@ -282,7 +286,7 @@ pub fn unit_base<
|
|||
let read_src_regs = wire(mop_ty.src_regs_ty());
|
||||
connect(
|
||||
read_src_regs,
|
||||
repeat(PRegNum[config].const_zero().cast_to_bits(), ConstUsize),
|
||||
repeat(PRegNum[config].const_zero(), ConstUsize),
|
||||
);
|
||||
#[hdl]
|
||||
let read_src_values = wire();
|
||||
|
|
@ -291,7 +295,7 @@ pub fn unit_base<
|
|||
let input_src_regs = wire(mop_ty.src_regs_ty());
|
||||
connect(
|
||||
input_src_regs,
|
||||
repeat(PRegNum[config].const_zero().cast_to_bits(), ConstUsize),
|
||||
repeat(PRegNum[config].const_zero(), ConstUsize),
|
||||
);
|
||||
#[hdl]
|
||||
let input_src_regs_valid = wire();
|
||||
|
|
@ -317,7 +321,7 @@ pub fn unit_base<
|
|||
|
||||
for src_index in 0..COMMON_MOP_SRC_LEN {
|
||||
let read_port = unit_output_regs.new_read_port();
|
||||
let p_reg_num = read_src_regs[src_index].cast_bits_to(PRegNum[config]);
|
||||
let p_reg_num = read_src_regs[src_index];
|
||||
connect_any(read_port.addr, p_reg_num.unit_out_reg.value);
|
||||
connect(read_port.en, false);
|
||||
connect(read_port.clk, cd.clk);
|
||||
|
|
@ -330,7 +334,7 @@ pub fn unit_base<
|
|||
|
||||
for src_index in 0..COMMON_MOP_SRC_LEN {
|
||||
let read_port = unit_output_regs_valid[unit_index].new_read_port();
|
||||
let p_reg_num = input_src_regs[src_index].cast_bits_to(PRegNum[config]);
|
||||
let p_reg_num = input_src_regs[src_index];
|
||||
connect_any(read_port.addr, p_reg_num.unit_out_reg.value);
|
||||
connect(read_port.en, false);
|
||||
connect(read_port.clk, cd.clk);
|
||||
|
|
@ -367,7 +371,7 @@ pub fn unit_base<
|
|||
};
|
||||
for src_index in 0..COMMON_MOP_SRC_LEN {
|
||||
#[hdl]
|
||||
if input_src_regs[src_index].cmp_eq(p_reg_num.cast_to_bits()) {
|
||||
if input_src_regs[src_index].cmp_eq(p_reg_num) {
|
||||
connect(input_src_regs_valid[src_index], true);
|
||||
}
|
||||
}
|
||||
|
|
@ -420,7 +424,7 @@ pub fn unit_base<
|
|||
let input_mop_src_regs = wire(mop_ty.src_regs_ty());
|
||||
connect(
|
||||
input_mop_src_regs,
|
||||
repeat(PRegNum[config].const_zero().cast_to_bits(), ConstUsize),
|
||||
repeat(PRegNum[config].const_zero(), ConstUsize),
|
||||
);
|
||||
MOp::connect_src_regs(mop, input_mop_src_regs);
|
||||
let src_ready_flags = wire_with_loc(
|
||||
|
|
@ -490,10 +494,7 @@ pub fn unit_base<
|
|||
SourceLocation::caller(),
|
||||
mop_ty.src_regs_ty(),
|
||||
);
|
||||
connect(
|
||||
src_regs,
|
||||
repeat(PRegNum[config].const_zero().cast_to_bits(), ConstUsize),
|
||||
);
|
||||
connect(src_regs, repeat(PRegNum[config].const_zero(), ConstUsize));
|
||||
MOp::connect_src_regs(mop, src_regs);
|
||||
|
||||
#[hdl]
|
||||
|
|
@ -522,7 +523,7 @@ pub fn unit_base<
|
|||
};
|
||||
for src_index in 0..COMMON_MOP_SRC_LEN {
|
||||
#[hdl]
|
||||
if p_reg_num.cast_to_bits().cmp_eq(src_regs[src_index]) {
|
||||
if p_reg_num.cmp_eq(src_regs[src_index]) {
|
||||
connect(
|
||||
in_flight_op_next_src_ready_flags[in_flight_op_index][src_index],
|
||||
true,
|
||||
|
|
|
|||
260685
crates/cpu/tests/expected/rename_execute_retire_fibonacci.vcd
generated
260685
crates/cpu/tests/expected/rename_execute_retire_fibonacci.vcd
generated
File diff suppressed because it is too large
Load diff
412643
crates/cpu/tests/expected/rename_execute_retire_slow_loop.vcd
generated
Normal file
412643
crates/cpu/tests/expected/rename_execute_retire_slow_loop.vcd
generated
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -3,8 +3,8 @@
|
|||
|
||||
use cpu::{
|
||||
config::{
|
||||
CpuConfig, CpuConfigFetchWidth, CpuConfigMaxUnitMaxInFlight, CpuConfigPRegNumWidth,
|
||||
PhantomConstCpuConfig, UnitConfig,
|
||||
CpuConfig, CpuConfigFetchWidth, CpuConfigMaxUnitMaxInFlight, PhantomConstCpuConfig,
|
||||
UnitConfig,
|
||||
},
|
||||
instruction::{
|
||||
AddSubMOp, AluBranchMOp, AluCommonMOp, BranchMOp, COMMON_MOP_SRC_LEN, CommonMOp,
|
||||
|
|
@ -246,7 +246,7 @@ impl InsnsBuilder {
|
|||
move |labels| {
|
||||
[BranchMOp::branch_i(
|
||||
MOpDestReg::new([], []),
|
||||
MOpRegNum::const_zero().value,
|
||||
[MOpRegNum::const_zero(); 2],
|
||||
labels[target.0]
|
||||
.pc()
|
||||
.wrapping_sub(pc)
|
||||
|
|
@ -264,7 +264,7 @@ impl InsnsBuilder {
|
|||
format!("blr"),
|
||||
[BranchMOp::branch_i(
|
||||
MOpDestReg::new([], []),
|
||||
MOpRegNum::power_isa_lr_reg().value,
|
||||
[MOpRegNum::const_zero(), MOpRegNum::power_isa_lr_reg()],
|
||||
0i8.cast_to_static::<SInt<_>>(),
|
||||
false,
|
||||
false,
|
||||
|
|
@ -281,9 +281,9 @@ impl InsnsBuilder {
|
|||
[BranchMOp::branch_cond_ctr(
|
||||
MOpDestReg::new([], []),
|
||||
[
|
||||
MOpRegNum::power_isa_cr_reg_imm(0).value,
|
||||
MOpRegNum::const_zero().value,
|
||||
MOpRegNum::const_zero().value,
|
||||
MOpRegNum::power_isa_cr_reg_imm(0),
|
||||
MOpRegNum::const_zero(),
|
||||
MOpRegNum::const_zero(),
|
||||
],
|
||||
labels[target.0]
|
||||
.pc()
|
||||
|
|
@ -291,7 +291,34 @@ impl InsnsBuilder {
|
|||
.cast_to_static::<SInt<_>>(),
|
||||
true,
|
||||
ConditionMode.SGt(),
|
||||
true,
|
||||
true,
|
||||
false,
|
||||
false,
|
||||
)]
|
||||
},
|
||||
));
|
||||
}
|
||||
fn power_isa_beq(&mut self, target: InsnsBuilderLabel) {
|
||||
let pc = self.pc;
|
||||
self.add_insn(Insn::new_lazy(
|
||||
4,
|
||||
format!("beq {}", self.labels[target.0].name),
|
||||
move |labels| {
|
||||
[BranchMOp::branch_cond_ctr(
|
||||
MOpDestReg::new_sim(&[], &[]),
|
||||
[
|
||||
MOpRegNum::power_isa_cr_reg_imm(0),
|
||||
MOpRegNum::const_zero(),
|
||||
MOpRegNum::const_zero(),
|
||||
],
|
||||
labels[target.0]
|
||||
.pc()
|
||||
.wrapping_sub(pc)
|
||||
.cast_to_static::<SInt<_>>(),
|
||||
false,
|
||||
ConditionMode.Eq(),
|
||||
true,
|
||||
true,
|
||||
false,
|
||||
false,
|
||||
|
|
@ -307,7 +334,7 @@ impl InsnsBuilder {
|
|||
move |labels| {
|
||||
[BranchMOp::branch_i(
|
||||
MOpDestReg::new([MOpRegNum::power_isa_lr_reg()], []),
|
||||
MOpRegNum::const_zero().value,
|
||||
[MOpRegNum::const_zero(); 2],
|
||||
labels[target.0]
|
||||
.pc()
|
||||
.wrapping_sub(pc)
|
||||
|
|
@ -326,9 +353,9 @@ impl InsnsBuilder {
|
|||
[AddSubMOp::add_sub(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(dest)], &[]),
|
||||
[
|
||||
MOpRegNum::power_isa_gpr_reg_imm(src1).value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm(src2).value,
|
||||
MOpRegNum::const_zero().value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm(src1),
|
||||
MOpRegNum::power_isa_gpr_reg_imm(src2),
|
||||
MOpRegNum::const_zero(),
|
||||
],
|
||||
0i8.cast_to_static::<SInt<_>>(),
|
||||
OutputIntegerMode.Full64(),
|
||||
|
|
@ -346,8 +373,8 @@ impl InsnsBuilder {
|
|||
[AddSubMOp::add_sub_i(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(dest)], &[]),
|
||||
[
|
||||
MOpRegNum::power_isa_gpr_or_zero_reg_imm(src).value,
|
||||
MOpRegNum::const_zero().value,
|
||||
MOpRegNum::power_isa_gpr_or_zero_reg_imm(src),
|
||||
MOpRegNum::const_zero(),
|
||||
],
|
||||
imm.cast_to_static::<SInt<_>>(),
|
||||
OutputIntegerMode.Full64(),
|
||||
|
|
@ -364,7 +391,7 @@ impl InsnsBuilder {
|
|||
format!("cmpldi {dest}, {src}, {imm:#x}"),
|
||||
[CompareMOp::compare_i(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(dest)], &[]),
|
||||
[MOpRegNum::power_isa_gpr_reg_imm(src).value],
|
||||
[MOpRegNum::power_isa_gpr_reg_imm(src)],
|
||||
imm.cast_to_static::<SInt<_>>(),
|
||||
CompareMode.U64(),
|
||||
)],
|
||||
|
|
@ -378,8 +405,8 @@ impl InsnsBuilder {
|
|||
AddSubMOp::add_sub_i(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]),
|
||||
[
|
||||
MOpRegNum::power_isa_gpr_or_zero_reg_imm(src).value,
|
||||
MOpRegNum::const_zero().value,
|
||||
MOpRegNum::power_isa_gpr_or_zero_reg_imm(src),
|
||||
MOpRegNum::const_zero(),
|
||||
],
|
||||
disp.cast_to_static::<SInt<_>>(),
|
||||
OutputIntegerMode.Full64(),
|
||||
|
|
@ -390,7 +417,7 @@ impl InsnsBuilder {
|
|||
),
|
||||
LoadMOp::load(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(dest)], &[]),
|
||||
[MOpRegNum::power_isa_temp_reg().value],
|
||||
[MOpRegNum::power_isa_temp_reg()],
|
||||
LoadStoreWidth.Width64Bit(),
|
||||
LoadStoreConversion.ZeroExt(),
|
||||
),
|
||||
|
|
@ -405,8 +432,8 @@ impl InsnsBuilder {
|
|||
AddSubMOp::add_sub_i(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]),
|
||||
[
|
||||
MOpRegNum::power_isa_gpr_or_zero_reg_imm(addr_src).value,
|
||||
MOpRegNum::const_zero().value,
|
||||
MOpRegNum::power_isa_gpr_or_zero_reg_imm(addr_src),
|
||||
MOpRegNum::const_zero(),
|
||||
],
|
||||
disp.cast_to_static::<SInt<_>>(),
|
||||
OutputIntegerMode.Full64(),
|
||||
|
|
@ -418,8 +445,8 @@ impl InsnsBuilder {
|
|||
StoreMOp::store(
|
||||
MOpDestReg::new_sim(&[], &[]),
|
||||
[
|
||||
MOpRegNum::power_isa_temp_reg().value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm(value_src).value,
|
||||
MOpRegNum::power_isa_temp_reg(),
|
||||
MOpRegNum::power_isa_gpr_reg_imm(value_src),
|
||||
],
|
||||
LoadStoreWidth.Width64Bit(),
|
||||
LoadStoreConversion.ZeroExt(),
|
||||
|
|
@ -433,7 +460,7 @@ impl InsnsBuilder {
|
|||
format!("mflr {dest}"),
|
||||
[MoveRegMOp::move_reg(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(dest)], &[]),
|
||||
[MOpRegNum::power_isa_lr_reg().value],
|
||||
[MOpRegNum::power_isa_lr_reg()],
|
||||
0i8.cast_to_static::<SInt<_>>(),
|
||||
)],
|
||||
));
|
||||
|
|
@ -444,7 +471,7 @@ impl InsnsBuilder {
|
|||
format!("mtlr {src}"),
|
||||
[MoveRegMOp::move_reg(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_LR_REG_NUM], &[]),
|
||||
[MOpRegNum::power_isa_gpr_reg_imm(src).value],
|
||||
[MOpRegNum::power_isa_gpr_reg_imm(src)],
|
||||
0i8.cast_to_static::<SInt<_>>(),
|
||||
)],
|
||||
));
|
||||
|
|
@ -455,7 +482,7 @@ impl InsnsBuilder {
|
|||
format!("mr {dest}, {src}"),
|
||||
[MoveRegMOp::move_reg(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(dest)], &[]),
|
||||
[MOpRegNum::power_isa_gpr_reg_imm(src).value],
|
||||
[MOpRegNum::power_isa_gpr_reg_imm(src)],
|
||||
0i8.cast_to_static::<SInt<_>>(),
|
||||
)],
|
||||
));
|
||||
|
|
@ -579,7 +606,7 @@ impl BrPredState {
|
|||
}
|
||||
fn predict_branch<SrcCount: KnownSize>(
|
||||
&mut self,
|
||||
mop: &SimValue<BranchMOp<MOpDestReg, ConstUsize<{ MOpRegNum::WIDTH }>, SrcCount>>,
|
||||
mop: &SimValue<BranchMOp<MOpDestReg, MOpRegNum, SrcCount>>,
|
||||
branch_pc: u64,
|
||||
fallthrough_pc: u64,
|
||||
) -> u64 {
|
||||
|
|
@ -590,7 +617,7 @@ impl BrPredState {
|
|||
}
|
||||
let mut src_regs = [MOpRegNum::CONST_ZERO_REG_NUM; 3];
|
||||
MOpTrait::for_each_src_reg_sim_ref(mop, &mut |reg, index| {
|
||||
src_regs[index] = reg.cast_to_static::<UInt<32>>().as_int();
|
||||
src_regs[index] = MOpRegNum::reg_num_sim(reg);
|
||||
});
|
||||
if src_regs[1] != MOpRegNum::CONST_ZERO_REG_NUM {
|
||||
// indirect branch -- this test doesn't implement predicting them, so just use the fallthrough_pc
|
||||
|
|
@ -1268,11 +1295,16 @@ impl MockMemory {
|
|||
#[hdl]
|
||||
fn run_mop<C: PhantomConstCpuConfig>(
|
||||
&mut self,
|
||||
mop: &SimValue<MOpInstance<LoadStoreMOp<PRegNum<C>, CpuConfigPRegNumWidth<C>>>>,
|
||||
mop: &SimValue<MOpInstance<LoadStoreMOp<PRegNum<C>, PRegNum<C>>>>,
|
||||
src_values: &[SimValue<PRegValue>; COMMON_MOP_SRC_LEN],
|
||||
is_speculative: bool,
|
||||
) -> Result<SimValue<PRegValue>, AddressCantBeSpeculativelyAccessed> {
|
||||
#[hdl(sim)]
|
||||
println!("MockMemory::run_mop: {:#x}: {:?}", mop.pc.as_int(), mop.mop);
|
||||
println!(
|
||||
"<- {}{src_values:?}",
|
||||
if is_speculative { "(speculative) " } else { "" },
|
||||
);
|
||||
let retval = #[hdl(sim)]
|
||||
match &mop.mop {
|
||||
LoadStoreMOp::<_, _>::Load(mop) => {
|
||||
#[hdl(sim)]
|
||||
|
|
@ -1323,13 +1355,11 @@ impl MockMemory {
|
|||
}
|
||||
}
|
||||
};
|
||||
Ok(
|
||||
#[hdl(sim)]
|
||||
PRegValue {
|
||||
int_fp: loaded,
|
||||
flags: PRegFlags::zeroed_sim(),
|
||||
},
|
||||
)
|
||||
#[hdl(sim)]
|
||||
PRegValue {
|
||||
int_fp: loaded,
|
||||
flags: PRegFlags::zeroed_sim(),
|
||||
}
|
||||
}
|
||||
LoadStoreMOp::<_, _>::Store(mop) => {
|
||||
#[hdl(sim)]
|
||||
|
|
@ -1363,9 +1393,11 @@ impl MockMemory {
|
|||
}
|
||||
}
|
||||
}
|
||||
Ok(PRegValue::zeroed_sim())
|
||||
PRegValue::zeroed_sim()
|
||||
}
|
||||
}
|
||||
};
|
||||
println!("-> {retval:?}");
|
||||
Ok(retval)
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1389,7 +1421,7 @@ trait MockExecutionStateTrait: Default {
|
|||
fn run_add_sub<C: PhantomConstCpuConfig, SrcCount: KnownSize>(
|
||||
&mut self,
|
||||
pc: u64,
|
||||
mop: &SimValue<AddSubMOp<PRegNum<C>, CpuConfigPRegNumWidth<C>, SrcCount>>,
|
||||
mop: &SimValue<AddSubMOp<PRegNum<C>, PRegNum<C>, SrcCount>>,
|
||||
src_values: &[SimValue<PRegValue>; COMMON_MOP_SRC_LEN],
|
||||
) -> SimValue<PRegValue> {
|
||||
#[hdl(sim)]
|
||||
|
|
@ -1453,7 +1485,7 @@ trait MockExecutionStateTrait: Default {
|
|||
#[hdl]
|
||||
fn run_compare<C: PhantomConstCpuConfig, SrcCount: KnownSize>(
|
||||
&mut self,
|
||||
mop: &SimValue<CompareMOp<PRegNum<C>, CpuConfigPRegNumWidth<C>, SrcCount>>,
|
||||
mop: &SimValue<CompareMOp<PRegNum<C>, PRegNum<C>, SrcCount>>,
|
||||
src_values: &[SimValue<PRegValue>; COMMON_MOP_SRC_LEN],
|
||||
) -> SimValue<PRegValue> {
|
||||
#[hdl(sim)]
|
||||
|
|
@ -1513,7 +1545,7 @@ trait MockExecutionStateTrait: Default {
|
|||
pc: u64,
|
||||
fallthrough_pc: u64,
|
||||
predicted_next_pc: u64,
|
||||
mop: &SimValue<BranchMOp<PRegNum<C>, CpuConfigPRegNumWidth<C>, SrcCount>>,
|
||||
mop: &SimValue<BranchMOp<PRegNum<C>, PRegNum<C>, SrcCount>>,
|
||||
src_values: &[SimValue<PRegValue>; COMMON_MOP_SRC_LEN],
|
||||
config: C,
|
||||
) -> (
|
||||
|
|
@ -1539,12 +1571,14 @@ trait MockExecutionStateTrait: Default {
|
|||
imm,
|
||||
} = common;
|
||||
let [src0, src1, src2] = src_values;
|
||||
let has_src0 = src.as_ref().get(0).is_some_and(|src0| {
|
||||
src0.cast_bits_to(PRegNum[config]) != PRegNum[config].const_zero().into_sim_value()
|
||||
});
|
||||
let has_src2 = src.as_ref().get(2).is_some_and(|src2| {
|
||||
src2.cast_bits_to(PRegNum[config]) != PRegNum[config].const_zero().into_sim_value()
|
||||
});
|
||||
let has_src0 = src
|
||||
.as_ref()
|
||||
.get(0)
|
||||
.is_some_and(|src0| *src0 != PRegNum[config].const_zero_sim());
|
||||
let has_src2 = src
|
||||
.as_ref()
|
||||
.get(2)
|
||||
.is_some_and(|src2| *src2 != PRegNum[config].const_zero_sim());
|
||||
let src2_cond = if has_src2 {
|
||||
let _ = invert_src2_eq_zero;
|
||||
let _ = src2;
|
||||
|
|
@ -1833,17 +1867,9 @@ impl<C: PhantomConstCpuConfig> MockUnitOp<C> {
|
|||
execution_state.run_mop(&self.mop, &self.src_values, self.config);
|
||||
assert!(output.is_some() || caused_cancel.is_some());
|
||||
println!("try_run: {:#x}: {:?}", self.mop.pc.as_int(), self.mop.mop);
|
||||
println!(
|
||||
"<- {:?}",
|
||||
self.src_values
|
||||
.each_ref()
|
||||
.map(PRegValue::debug_fmt::<PRegFlagsPowerISA>),
|
||||
);
|
||||
println!("<- {:?}", self.src_values);
|
||||
self.output_ready = output.map(|(dest_value, predictor_op)| {
|
||||
println!(
|
||||
"-> {:?}",
|
||||
PRegValue::debug_fmt::<PRegFlagsPowerISA>(&dest_value),
|
||||
);
|
||||
println!("-> {dest_value:?}");
|
||||
#[hdl(sim)]
|
||||
let NextPcPredictorOp::<_> {
|
||||
call_stack_op,
|
||||
|
|
@ -2236,7 +2262,7 @@ fn mock_unit<#[hdl(skip)] E: MockExecutionStateTrait>(
|
|||
|
||||
#[hdl(no_static)]
|
||||
struct MockLoadStoreOpDebugState<C: PhantomConstGet<CpuConfig>> {
|
||||
mop: MOpInstance<LoadStoreMOp<PRegNum<C>, CpuConfigPRegNumWidth<C>>>,
|
||||
mop: MOpInstance<LoadStoreMOp<PRegNum<C>, PRegNum<C>>>,
|
||||
is_speculative: Bool,
|
||||
src_values: HdlOption<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>,
|
||||
dest_value: HdlOption<PRegValue>,
|
||||
|
|
@ -2248,7 +2274,7 @@ struct MockLoadStoreOpDebugState<C: PhantomConstGet<CpuConfig>> {
|
|||
|
||||
#[derive(Debug)]
|
||||
struct MockLoadStoreOp<C: PhantomConstCpuConfig> {
|
||||
mop: SimValue<MOpInstance<LoadStoreMOp<PRegNum<C>, CpuConfigPRegNumWidth<C>>>>,
|
||||
mop: SimValue<MOpInstance<LoadStoreMOp<PRegNum<C>, PRegNum<C>>>>,
|
||||
is_speculative: bool,
|
||||
src_values: Option<[SimValue<PRegValue>; COMMON_MOP_SRC_LEN]>,
|
||||
dest_value: Option<SimValue<PRegValue>>,
|
||||
|
|
@ -2983,3 +3009,135 @@ fn test_rename_execute_retire_fibonacci() {
|
|||
panic!();
|
||||
}
|
||||
}
|
||||
|
||||
struct SlowLoopInsns;
|
||||
|
||||
impl SlowLoopInsns {
|
||||
const CONSTANTS_ADDR: u64 = 0x4000;
|
||||
const CONSTANTS_COUNT: usize = 5;
|
||||
const CONSTANTS_STEP: usize = 8;
|
||||
const LOG2_RESULT_FACTOR: u32 = 2;
|
||||
}
|
||||
|
||||
impl MakeInsns for SlowLoopInsns {
|
||||
fn make_insns() -> Insns {
|
||||
let mut b = InsnsBuilder::new();
|
||||
|
||||
let slow_loop = b.new_label("slow_loop");
|
||||
b.power_isa_ld(3, 0, MockMemory::IO_ADDR as i16); // load input
|
||||
b.power_isa_addi(1, 0, 0x4000); // setup stack pointer
|
||||
b.power_isa_bl(slow_loop);
|
||||
b.power_isa_std(3, 0, MockMemory::IO_ADDR as i16); // store output
|
||||
let done = b.new_defined_label("done");
|
||||
b.power_isa_b(done);
|
||||
|
||||
b.set_pc(0x1000);
|
||||
b.define_label(slow_loop);
|
||||
|
||||
let loop_header = b.new_defined_label("loop_header");
|
||||
b.power_isa_addi(4, 0, 0); // clear sum
|
||||
b.power_isa_cmpldi(0, 3, 0);
|
||||
let loop_done = b.new_label("loop_done");
|
||||
b.power_isa_beq(loop_done); // if input == 0 goto loop_done
|
||||
|
||||
// long sequence of loads to provoke L2 register file store
|
||||
let start_reg = 5;
|
||||
assert!(
|
||||
start_reg + Self::CONSTANTS_COUNT <= 32,
|
||||
"too many constants to load them all into PowerISA GPRs",
|
||||
);
|
||||
for i in 0..Self::CONSTANTS_COUNT {
|
||||
b.power_isa_ld(
|
||||
start_reg + i,
|
||||
0,
|
||||
(Self::CONSTANTS_ADDR + (Self::CONSTANTS_STEP * i) as u64) as i16,
|
||||
);
|
||||
}
|
||||
for i in 1..Self::CONSTANTS_COUNT {
|
||||
b.power_isa_add(4, 4, start_reg + i);
|
||||
}
|
||||
|
||||
b.power_isa_addi(3, 3, -1);
|
||||
b.power_isa_b(loop_header);
|
||||
|
||||
b.define_label(loop_done);
|
||||
b.power_isa_mr(3, 4);
|
||||
for _ in 0..Self::LOG2_RESULT_FACTOR {
|
||||
b.power_isa_add(3, 3, 3);
|
||||
}
|
||||
b.power_isa_blr(); // return
|
||||
|
||||
b.build()
|
||||
}
|
||||
fn make_load_store_execution_state() -> MockMemory {
|
||||
let expected = 0x0123_4567_89AB_CDEF_u64;
|
||||
let constants: [[u8; Self::CONSTANTS_STEP]; Self::CONSTANTS_COUNT] =
|
||||
std::array::from_fn(|i| {
|
||||
let start_bit_index = i * 64 / Self::CONSTANTS_COUNT;
|
||||
let end_bit_index = (i + 1) * 64 / Self::CONSTANTS_COUNT;
|
||||
let start_bit = 1u64.unbounded_shl(start_bit_index as u32);
|
||||
let end_bit = 1u64.unbounded_shl(end_bit_index as u32);
|
||||
let mask = end_bit.wrapping_sub(start_bit);
|
||||
(expected & mask).to_le_bytes()
|
||||
});
|
||||
let loop_count = 4;
|
||||
MockMemory::new(
|
||||
loop_count,
|
||||
expected * loop_count * 2u64.pow(Self::LOG2_RESULT_FACTOR),
|
||||
[(Self::CONSTANTS_ADDR, constants.as_flattened())],
|
||||
)
|
||||
}
|
||||
}
|
||||
|
||||
#[hdl]
|
||||
#[test]
|
||||
fn test_rename_execute_retire_slow_loop() {
|
||||
let _n = SourceLocation::normalize_files_for_tests();
|
||||
let mut config = CpuConfig::new(
|
||||
vec![
|
||||
UnitConfig::new(UnitKind::AluBranch),
|
||||
UnitConfig::new(UnitKind::AluBranch),
|
||||
UnitConfig::new(UnitKind::AluBranch),
|
||||
UnitConfig::new(UnitKind::AluBranch),
|
||||
UnitConfig::new(UnitKind::LoadStore),
|
||||
UnitConfig::new(UnitKind::TransformedMove),
|
||||
],
|
||||
NonZeroUsize::new(20).unwrap(),
|
||||
);
|
||||
config.fetch_width = NonZeroUsize::new(4).unwrap();
|
||||
let m = rename_execute_retire_test_harness::<SlowLoopInsns>(PhantomConst::new_sized(config));
|
||||
let mut sim = Simulation::new(m);
|
||||
let writer = RcWriter::default();
|
||||
sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
|
||||
struct DumpVcdOnDrop {
|
||||
writer: Option<RcWriter>,
|
||||
}
|
||||
impl Drop for DumpVcdOnDrop {
|
||||
fn drop(&mut self) {
|
||||
if let Some(mut writer) = self.writer.take() {
|
||||
let vcd = String::from_utf8(writer.take()).unwrap();
|
||||
println!("####### VCD:\n{vcd}\n#######");
|
||||
}
|
||||
}
|
||||
}
|
||||
let mut writer = DumpVcdOnDrop {
|
||||
writer: Some(writer),
|
||||
};
|
||||
sim.write_clock(sim.io().cd.clk, false);
|
||||
sim.write_reset(sim.io().cd.rst, true);
|
||||
for cycle in 0..200 {
|
||||
sim.advance_time(SimDuration::from_nanos(500));
|
||||
println!("clock tick: {cycle}");
|
||||
sim.write_clock(sim.io().cd.clk, true);
|
||||
sim.advance_time(SimDuration::from_nanos(500));
|
||||
sim.write_clock(sim.io().cd.clk, false);
|
||||
sim.write_reset(sim.io().cd.rst, false);
|
||||
}
|
||||
assert!(sim.read_bool(sim.io().all_outputs_written));
|
||||
// FIXME: vcd is just whatever rename_execute_retire does now, which isn't known to be correct
|
||||
let vcd = String::from_utf8(writer.writer.take().unwrap().take()).unwrap();
|
||||
println!("####### VCD:\n{vcd}\n#######");
|
||||
if vcd != include_str!("expected/rename_execute_retire_slow_loop.vcd") {
|
||||
panic!();
|
||||
}
|
||||
}
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -15,7 +15,7 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
|
|||
None,
|
||||
BranchMOp::branch_i(
|
||||
MOpDestReg::new_sim(&[], &[]),
|
||||
MOpRegNum::const_zero().value,
|
||||
[MOpRegNum::const_zero(); 2],
|
||||
0x345678.cast_to_static::<SInt<_>>(),
|
||||
true,
|
||||
false,
|
||||
|
|
@ -28,7 +28,7 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
|
|||
None,
|
||||
BranchMOp::branch_i(
|
||||
MOpDestReg::new_sim(&[], &[]),
|
||||
MOpRegNum::const_zero().value,
|
||||
[MOpRegNum::const_zero(); 2],
|
||||
0x345678.cast_to_static::<SInt<_>>(),
|
||||
false,
|
||||
false,
|
||||
|
|
@ -41,7 +41,7 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
|
|||
None,
|
||||
BranchMOp::branch_i(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_LR_REG_NUM], &[]),
|
||||
MOpRegNum::const_zero().value,
|
||||
[MOpRegNum::const_zero(); 2],
|
||||
0x345678.cast_to_static::<SInt<_>>(),
|
||||
true,
|
||||
true,
|
||||
|
|
@ -54,7 +54,7 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
|
|||
None,
|
||||
BranchMOp::branch_i(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_LR_REG_NUM], &[]),
|
||||
MOpRegNum::const_zero().value,
|
||||
[MOpRegNum::const_zero(); 2],
|
||||
0x345678.cast_to_static::<SInt<_>>(),
|
||||
false,
|
||||
true,
|
||||
|
|
@ -74,10 +74,7 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
|
|||
[
|
||||
AddSubMOp::add_sub_i::<MOp>(
|
||||
MOpDestReg::new([MOpRegNum::power_isa_ctr_reg()], []),
|
||||
[
|
||||
MOpRegNum::power_isa_ctr_reg().value,
|
||||
MOpRegNum::const_zero().value,
|
||||
],
|
||||
[MOpRegNum::power_isa_ctr_reg(), MOpRegNum::const_zero()],
|
||||
(-1).cast_to_static::<SInt<_>>(),
|
||||
OutputIntegerMode.Full64(),
|
||||
false,
|
||||
|
|
@ -143,9 +140,9 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
|
|||
BranchMOp::branch_cond_ctr(
|
||||
$dest,
|
||||
[
|
||||
MOpRegNum::power_isa_cr_reg_imm(0).value,
|
||||
MOpRegNum::power_isa_cr_reg_imm(0),
|
||||
$src1,
|
||||
MOpRegNum::power_isa_ctr_reg().value,
|
||||
MOpRegNum::power_isa_ctr_reg(),
|
||||
],
|
||||
$imm.cast_to_static::<SInt<_>>(),
|
||||
true,
|
||||
|
|
@ -163,9 +160,9 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
|
|||
BranchMOp::branch_cond_ctr(
|
||||
$dest,
|
||||
[
|
||||
MOpRegNum::power_isa_cr_reg_imm(0).value,
|
||||
MOpRegNum::power_isa_cr_reg_imm(0),
|
||||
$src1,
|
||||
MOpRegNum::power_isa_ctr_reg().value,
|
||||
MOpRegNum::power_isa_ctr_reg(),
|
||||
],
|
||||
$imm.cast_to_static::<SInt<_>>(),
|
||||
true,
|
||||
|
|
@ -183,9 +180,9 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
|
|||
BranchMOp::branch_cond_ctr(
|
||||
$dest,
|
||||
[
|
||||
MOpRegNum::power_isa_cr_reg_imm(0).value,
|
||||
MOpRegNum::power_isa_cr_reg_imm(0),
|
||||
$src1,
|
||||
MOpRegNum::power_isa_ctr_reg().value,
|
||||
MOpRegNum::power_isa_ctr_reg(),
|
||||
],
|
||||
$imm.cast_to_static::<SInt<_>>(),
|
||||
true,
|
||||
|
|
@ -203,9 +200,9 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
|
|||
BranchMOp::branch_cond_ctr(
|
||||
$dest,
|
||||
[
|
||||
MOpRegNum::power_isa_cr_reg_imm(0).value,
|
||||
MOpRegNum::power_isa_cr_reg_imm(0),
|
||||
$src1,
|
||||
MOpRegNum::power_isa_ctr_reg().value,
|
||||
MOpRegNum::power_isa_ctr_reg(),
|
||||
],
|
||||
$imm.cast_to_static::<SInt<_>>(),
|
||||
true,
|
||||
|
|
@ -223,9 +220,9 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
|
|||
BranchMOp::branch_cond_ctr(
|
||||
$dest,
|
||||
[
|
||||
MOpRegNum::power_isa_cr_reg_imm(2).value,
|
||||
MOpRegNum::power_isa_cr_reg_imm(2),
|
||||
$src1,
|
||||
MOpRegNum::power_isa_ctr_reg().value,
|
||||
MOpRegNum::power_isa_ctr_reg(),
|
||||
],
|
||||
$imm.cast_to_static::<SInt<_>>(),
|
||||
true,
|
||||
|
|
@ -243,9 +240,9 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
|
|||
BranchMOp::branch_cond_ctr(
|
||||
$dest,
|
||||
[
|
||||
MOpRegNum::power_isa_cr_reg_imm(0).value,
|
||||
MOpRegNum::power_isa_cr_reg_imm(0),
|
||||
$src1,
|
||||
MOpRegNum::power_isa_ctr_reg().value,
|
||||
MOpRegNum::power_isa_ctr_reg(),
|
||||
],
|
||||
$imm.cast_to_static::<SInt<_>>(),
|
||||
true,
|
||||
|
|
@ -264,9 +261,9 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
|
|||
BranchMOp::branch_cond_ctr(
|
||||
$dest,
|
||||
[
|
||||
MOpRegNum::power_isa_cr_reg_imm(0).value,
|
||||
MOpRegNum::power_isa_cr_reg_imm(0),
|
||||
$src1,
|
||||
MOpRegNum::const_zero().value,
|
||||
MOpRegNum::const_zero(),
|
||||
],
|
||||
$imm.cast_to_static::<SInt<_>>(),
|
||||
true,
|
||||
|
|
@ -285,9 +282,9 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
|
|||
BranchMOp::branch_cond_ctr(
|
||||
$dest,
|
||||
[
|
||||
MOpRegNum::power_isa_cr_reg_imm(0).value,
|
||||
MOpRegNum::power_isa_cr_reg_imm(0),
|
||||
$src1,
|
||||
MOpRegNum::power_isa_ctr_reg().value,
|
||||
MOpRegNum::power_isa_ctr_reg(),
|
||||
],
|
||||
$imm.cast_to_static::<SInt<_>>(),
|
||||
false,
|
||||
|
|
@ -305,9 +302,9 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
|
|||
BranchMOp::branch_cond_ctr(
|
||||
$dest,
|
||||
[
|
||||
MOpRegNum::power_isa_cr_reg_imm(0).value,
|
||||
MOpRegNum::power_isa_cr_reg_imm(0),
|
||||
$src1,
|
||||
MOpRegNum::power_isa_ctr_reg().value,
|
||||
MOpRegNum::power_isa_ctr_reg(),
|
||||
],
|
||||
$imm.cast_to_static::<SInt<_>>(),
|
||||
false,
|
||||
|
|
@ -326,9 +323,9 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
|
|||
BranchMOp::branch_cond_ctr(
|
||||
$dest,
|
||||
[
|
||||
MOpRegNum::power_isa_cr_reg_imm(0).value,
|
||||
MOpRegNum::power_isa_cr_reg_imm(0),
|
||||
$src1,
|
||||
MOpRegNum::const_zero().value,
|
||||
MOpRegNum::const_zero(),
|
||||
],
|
||||
$imm.cast_to_static::<SInt<_>>(),
|
||||
false,
|
||||
|
|
@ -346,8 +343,11 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
|
|||
None,
|
||||
BranchMOp::branch_ctr(
|
||||
$dest,
|
||||
$src1,
|
||||
MOpRegNum::power_isa_ctr_reg().value,
|
||||
[
|
||||
MOpRegNum::const_zero(),
|
||||
$src1,
|
||||
MOpRegNum::power_isa_ctr_reg(),
|
||||
],
|
||||
$imm.cast_to_static::<SInt<_>>(),
|
||||
true,
|
||||
$pc_relative,
|
||||
|
|
@ -361,8 +361,11 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
|
|||
None,
|
||||
BranchMOp::branch_ctr(
|
||||
$dest,
|
||||
$src1,
|
||||
MOpRegNum::power_isa_ctr_reg().value,
|
||||
[
|
||||
MOpRegNum::const_zero(),
|
||||
$src1,
|
||||
MOpRegNum::power_isa_ctr_reg(),
|
||||
],
|
||||
$imm.cast_to_static::<SInt<_>>(),
|
||||
false,
|
||||
$pc_relative,
|
||||
|
|
@ -377,7 +380,7 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
|
|||
None,
|
||||
BranchMOp::branch_i(
|
||||
$dest,
|
||||
$src1,
|
||||
[MOpRegNum::const_zero(), $src1],
|
||||
$imm.cast_to_static::<SInt<_>>(),
|
||||
$pc_relative,
|
||||
$lk,
|
||||
|
|
@ -392,7 +395,7 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
|
|||
asm_last_arg = "0x1234";
|
||||
imm = 0x1234;
|
||||
encoding = 0x40001234;
|
||||
src1 = MOpRegNum::const_zero().value;
|
||||
src1 = MOpRegNum::const_zero();
|
||||
pc_relative = true;
|
||||
is_ret = false;
|
||||
}
|
||||
|
|
@ -402,7 +405,7 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
|
|||
asm_last_arg = "0x1234";
|
||||
imm = 0x1234;
|
||||
encoding = 0x40001236;
|
||||
src1 = MOpRegNum::const_zero().value;
|
||||
src1 = MOpRegNum::const_zero();
|
||||
pc_relative = false;
|
||||
is_ret = false;
|
||||
}
|
||||
|
|
@ -412,7 +415,7 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
|
|||
asm_last_arg = "0";
|
||||
imm = 0;
|
||||
encoding = 0x4c000020;
|
||||
src1 = MOpRegNum::power_isa_lr_reg().value;
|
||||
src1 = MOpRegNum::power_isa_lr_reg();
|
||||
pc_relative = false;
|
||||
is_ret = true;
|
||||
}
|
||||
|
|
@ -422,7 +425,7 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
|
|||
asm_last_arg = "0";
|
||||
imm = 0;
|
||||
encoding = 0x4c000420;
|
||||
src1 = MOpRegNum::power_isa_ctr_reg().value;
|
||||
src1 = MOpRegNum::power_isa_ctr_reg();
|
||||
pc_relative = false;
|
||||
is_ret = false;
|
||||
}
|
||||
|
|
@ -434,8 +437,11 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
|
|||
None,
|
||||
BranchMOp::branch_ctr(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_LR_REG_NUM], &[]),
|
||||
MOpRegNum::power_isa_tar_reg().value,
|
||||
MOpRegNum::power_isa_ctr_reg().value,
|
||||
[
|
||||
MOpRegNum::const_zero(),
|
||||
MOpRegNum::power_isa_tar_reg(),
|
||||
MOpRegNum::power_isa_ctr_reg(),
|
||||
],
|
||||
0.cast_to_static::<SInt<_>>(),
|
||||
false,
|
||||
false,
|
||||
|
|
|
|||
|
|
@ -23,9 +23,9 @@ pub fn test_cases_book_i_2_5_condition_register(retval: &mut Vec<TestCase>) {
|
|||
LogicalFlagsMOp::logical_flags(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
|
||||
[
|
||||
MOpRegNum::power_isa_cr_reg_imm(1).value,
|
||||
MOpRegNum::power_isa_cr_reg_imm(5).value,
|
||||
MOpRegNum::power_isa_cr_reg_imm(3).value,
|
||||
MOpRegNum::power_isa_cr_reg_imm(1),
|
||||
MOpRegNum::power_isa_cr_reg_imm(5),
|
||||
MOpRegNum::power_isa_cr_reg_imm(3),
|
||||
],
|
||||
LogicalFlagsMOpImm::from_swizzle_fn::<PRegFlagsPowerISA>(|src0, src1, src2| {
|
||||
let mut dest = src2.map(|v| Some(v.into()));
|
||||
|
|
@ -42,9 +42,9 @@ pub fn test_cases_book_i_2_5_condition_register(retval: &mut Vec<TestCase>) {
|
|||
LogicalFlagsMOp::logical_flags(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(0)], &[]),
|
||||
[
|
||||
MOpRegNum::power_isa_cr_reg_imm(0).value,
|
||||
MOpRegNum::power_isa_cr_reg_imm(0).value,
|
||||
MOpRegNum::power_isa_cr_reg_imm(0).value,
|
||||
MOpRegNum::power_isa_cr_reg_imm(0),
|
||||
MOpRegNum::power_isa_cr_reg_imm(0),
|
||||
MOpRegNum::power_isa_cr_reg_imm(0),
|
||||
],
|
||||
LogicalFlagsMOpImm::from_swizzle_fn::<PRegFlagsPowerISA>(|src0, src1, src2| {
|
||||
let mut dest = src2.map(|v| Some(v.into()));
|
||||
|
|
@ -61,9 +61,9 @@ pub fn test_cases_book_i_2_5_condition_register(retval: &mut Vec<TestCase>) {
|
|||
LogicalFlagsMOp::logical_flags(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(0)], &[]),
|
||||
[
|
||||
MOpRegNum::power_isa_cr_reg_imm(0).value,
|
||||
MOpRegNum::power_isa_cr_reg_imm(0).value,
|
||||
MOpRegNum::power_isa_cr_reg_imm(0).value,
|
||||
MOpRegNum::power_isa_cr_reg_imm(0),
|
||||
MOpRegNum::power_isa_cr_reg_imm(0),
|
||||
MOpRegNum::power_isa_cr_reg_imm(0),
|
||||
],
|
||||
LogicalFlagsMOpImm::from_swizzle_fn::<PRegFlagsPowerISA>(|src0, src1, src2| {
|
||||
let mut dest = src2.map(|v| Some(v.into()));
|
||||
|
|
@ -91,7 +91,7 @@ pub fn test_cases_book_i_2_5_condition_register(retval: &mut Vec<TestCase>) {
|
|||
None,
|
||||
MoveRegMOp::move_reg(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num($dest)], &[]),
|
||||
[MOpRegNum::power_isa_cr_reg_imm($src).value],
|
||||
[MOpRegNum::power_isa_cr_reg_imm($src)],
|
||||
0i8.cast_to_static::<SInt<_>>(),
|
||||
),
|
||||
));
|
||||
|
|
|
|||
|
|
@ -13,10 +13,7 @@ pub fn test_cases_book_i_3_3_9_fixed_point_arithmetic(retval: &mut Vec<TestCase>
|
|||
None,
|
||||
AddSubMOp::add_sub_i(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
|
||||
[
|
||||
MOpRegNum::power_isa_gpr_reg_imm(4).value,
|
||||
MOpRegNum::const_zero().value,
|
||||
],
|
||||
[MOpRegNum::power_isa_gpr_reg_imm(4), MOpRegNum::const_zero()],
|
||||
0x1234.cast_to_static::<SInt<_>>(),
|
||||
OutputIntegerMode.Full64(),
|
||||
false,
|
||||
|
|
@ -31,10 +28,7 @@ pub fn test_cases_book_i_3_3_9_fixed_point_arithmetic(retval: &mut Vec<TestCase>
|
|||
Some(0x38646789),
|
||||
AddSubMOp::add_sub_i(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
|
||||
[
|
||||
MOpRegNum::power_isa_gpr_reg_imm(4).value,
|
||||
MOpRegNum::const_zero().value,
|
||||
],
|
||||
[MOpRegNum::power_isa_gpr_reg_imm(4), MOpRegNum::const_zero()],
|
||||
0x123456789i64.cast_to_static::<SInt<_>>(),
|
||||
OutputIntegerMode.Full64(),
|
||||
false,
|
||||
|
|
@ -49,7 +43,7 @@ pub fn test_cases_book_i_3_3_9_fixed_point_arithmetic(retval: &mut Vec<TestCase>
|
|||
Some(0x38606789),
|
||||
AddSubMOp::add_sub_i(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
|
||||
[MOpRegNum::const_zero().value, MOpRegNum::const_zero().value],
|
||||
[MOpRegNum::const_zero(), MOpRegNum::const_zero()],
|
||||
0x123456789i64.cast_to_static::<SInt<_>>(),
|
||||
OutputIntegerMode.Full64(),
|
||||
false,
|
||||
|
|
@ -64,10 +58,7 @@ pub fn test_cases_book_i_3_3_9_fixed_point_arithmetic(retval: &mut Vec<TestCase>
|
|||
None,
|
||||
AddSubMOp::add_sub_i(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
|
||||
[
|
||||
MOpRegNum::power_isa_gpr_reg_imm(4).value,
|
||||
MOpRegNum::const_zero().value,
|
||||
],
|
||||
[MOpRegNum::power_isa_gpr_reg_imm(4), MOpRegNum::const_zero()],
|
||||
0x12340000.cast_to_static::<SInt<_>>(),
|
||||
OutputIntegerMode.Full64(),
|
||||
false,
|
||||
|
|
@ -82,7 +73,7 @@ pub fn test_cases_book_i_3_3_9_fixed_point_arithmetic(retval: &mut Vec<TestCase>
|
|||
None,
|
||||
AddSubMOp::add_sub_i(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
|
||||
[MOpRegNum::const_zero().value; _],
|
||||
[MOpRegNum::const_zero(); _],
|
||||
0x12340004.cast_to_static::<SInt<_>>(),
|
||||
OutputIntegerMode.Full64(),
|
||||
false,
|
||||
|
|
@ -101,9 +92,9 @@ pub fn test_cases_book_i_3_3_9_fixed_point_arithmetic(retval: &mut Vec<TestCase>
|
|||
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
|
||||
),
|
||||
[
|
||||
MOpRegNum::power_isa_gpr_reg_imm(4).value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm(5).value,
|
||||
MOpRegNum::const_zero().value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm(4),
|
||||
MOpRegNum::power_isa_gpr_reg_imm(5),
|
||||
MOpRegNum::const_zero(),
|
||||
],
|
||||
0.cast_to_static::<SInt<_>>(),
|
||||
OutputIntegerMode.Full64(),
|
||||
|
|
@ -125,10 +116,7 @@ pub fn test_cases_book_i_3_3_9_fixed_point_arithmetic(retval: &mut Vec<TestCase>
|
|||
],
|
||||
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
|
||||
),
|
||||
[
|
||||
MOpRegNum::power_isa_gpr_reg_imm(4).value,
|
||||
MOpRegNum::const_zero().value,
|
||||
],
|
||||
[MOpRegNum::power_isa_gpr_reg_imm(4), MOpRegNum::const_zero()],
|
||||
0x1234.cast_to_static::<SInt<_>>(),
|
||||
OutputIntegerMode.Full64(),
|
||||
false,
|
||||
|
|
@ -147,9 +135,9 @@ pub fn test_cases_book_i_3_3_9_fixed_point_arithmetic(retval: &mut Vec<TestCase>
|
|||
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
|
||||
),
|
||||
[
|
||||
MOpRegNum::power_isa_gpr_reg_imm(4).value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm(5).value,
|
||||
MOpRegNum::const_zero().value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm(4),
|
||||
MOpRegNum::power_isa_gpr_reg_imm(5),
|
||||
MOpRegNum::const_zero(),
|
||||
],
|
||||
0.cast_to_static::<SInt<_>>(),
|
||||
OutputIntegerMode.Full64(),
|
||||
|
|
@ -171,10 +159,7 @@ pub fn test_cases_book_i_3_3_9_fixed_point_arithmetic(retval: &mut Vec<TestCase>
|
|||
],
|
||||
&[],
|
||||
),
|
||||
[
|
||||
MOpRegNum::power_isa_gpr_reg_imm(4).value,
|
||||
MOpRegNum::const_zero().value,
|
||||
],
|
||||
[MOpRegNum::power_isa_gpr_reg_imm(4), MOpRegNum::const_zero()],
|
||||
0x1234.cast_to_static::<SInt<_>>(),
|
||||
OutputIntegerMode.Full64(),
|
||||
true,
|
||||
|
|
@ -196,9 +181,9 @@ pub fn test_cases_book_i_3_3_9_fixed_point_arithmetic(retval: &mut Vec<TestCase>
|
|||
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
|
||||
),
|
||||
[
|
||||
MOpRegNum::power_isa_gpr_reg_imm(4).value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm(5).value,
|
||||
MOpRegNum::const_zero().value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm(4),
|
||||
MOpRegNum::power_isa_gpr_reg_imm(5),
|
||||
MOpRegNum::const_zero(),
|
||||
],
|
||||
0.cast_to_static::<SInt<_>>(),
|
||||
OutputIntegerMode.Full64(),
|
||||
|
|
@ -221,9 +206,9 @@ pub fn test_cases_book_i_3_3_9_fixed_point_arithmetic(retval: &mut Vec<TestCase>
|
|||
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
|
||||
),
|
||||
[
|
||||
MOpRegNum::power_isa_gpr_reg_imm(4).value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm(5).value,
|
||||
MOpRegNum::const_zero().value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm(4),
|
||||
MOpRegNum::power_isa_gpr_reg_imm(5),
|
||||
MOpRegNum::const_zero(),
|
||||
],
|
||||
0.cast_to_static::<SInt<_>>(),
|
||||
OutputIntegerMode.Full64(),
|
||||
|
|
@ -246,9 +231,9 @@ pub fn test_cases_book_i_3_3_9_fixed_point_arithmetic(retval: &mut Vec<TestCase>
|
|||
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
|
||||
),
|
||||
[
|
||||
MOpRegNum::power_isa_gpr_reg_imm(4).value,
|
||||
MOpRegNum::power_isa_xer_ca_ca32_reg().value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm(5).value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm(4),
|
||||
MOpRegNum::power_isa_xer_ca_ca32_reg(),
|
||||
MOpRegNum::power_isa_gpr_reg_imm(5),
|
||||
],
|
||||
0.cast_to_static::<SInt<_>>(),
|
||||
OutputIntegerMode.Full64(),
|
||||
|
|
@ -271,9 +256,9 @@ pub fn test_cases_book_i_3_3_9_fixed_point_arithmetic(retval: &mut Vec<TestCase>
|
|||
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
|
||||
),
|
||||
[
|
||||
MOpRegNum::power_isa_gpr_reg_imm(4).value,
|
||||
MOpRegNum::power_isa_xer_ca_ca32_reg().value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm(5).value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm(4),
|
||||
MOpRegNum::power_isa_xer_ca_ca32_reg(),
|
||||
MOpRegNum::power_isa_gpr_reg_imm(5),
|
||||
],
|
||||
0.cast_to_static::<SInt<_>>(),
|
||||
OutputIntegerMode.Full64(),
|
||||
|
|
@ -296,9 +281,9 @@ pub fn test_cases_book_i_3_3_9_fixed_point_arithmetic(retval: &mut Vec<TestCase>
|
|||
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
|
||||
),
|
||||
[
|
||||
MOpRegNum::power_isa_gpr_reg_imm(4).value,
|
||||
MOpRegNum::power_isa_xer_ca_ca32_reg().value,
|
||||
MOpRegNum::const_zero().value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm(4),
|
||||
MOpRegNum::power_isa_xer_ca_ca32_reg(),
|
||||
MOpRegNum::const_zero(),
|
||||
],
|
||||
(-1i8).cast_to_static::<SInt<_>>(),
|
||||
OutputIntegerMode.Full64(),
|
||||
|
|
@ -321,9 +306,9 @@ pub fn test_cases_book_i_3_3_9_fixed_point_arithmetic(retval: &mut Vec<TestCase>
|
|||
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
|
||||
),
|
||||
[
|
||||
MOpRegNum::power_isa_gpr_reg_imm(4).value,
|
||||
MOpRegNum::power_isa_xer_ca_ca32_reg().value,
|
||||
MOpRegNum::const_zero().value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm(4),
|
||||
MOpRegNum::power_isa_xer_ca_ca32_reg(),
|
||||
MOpRegNum::const_zero(),
|
||||
],
|
||||
(-1i8).cast_to_static::<SInt<_>>(),
|
||||
OutputIntegerMode.Full64(),
|
||||
|
|
@ -346,9 +331,9 @@ pub fn test_cases_book_i_3_3_9_fixed_point_arithmetic(retval: &mut Vec<TestCase>
|
|||
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
|
||||
),
|
||||
[
|
||||
MOpRegNum::power_isa_gpr_reg_imm(4).value,
|
||||
MOpRegNum::power_isa_xer_ca_ca32_reg().value,
|
||||
MOpRegNum::const_zero().value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm(4),
|
||||
MOpRegNum::power_isa_xer_ca_ca32_reg(),
|
||||
MOpRegNum::const_zero(),
|
||||
],
|
||||
0.cast_to_static::<SInt<_>>(),
|
||||
OutputIntegerMode.Full64(),
|
||||
|
|
@ -371,9 +356,9 @@ pub fn test_cases_book_i_3_3_9_fixed_point_arithmetic(retval: &mut Vec<TestCase>
|
|||
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
|
||||
),
|
||||
[
|
||||
MOpRegNum::power_isa_gpr_reg_imm(4).value,
|
||||
MOpRegNum::power_isa_xer_ca_ca32_reg().value,
|
||||
MOpRegNum::const_zero().value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm(4),
|
||||
MOpRegNum::power_isa_xer_ca_ca32_reg(),
|
||||
MOpRegNum::const_zero(),
|
||||
],
|
||||
0.cast_to_static::<SInt<_>>(),
|
||||
OutputIntegerMode.Full64(),
|
||||
|
|
@ -393,9 +378,9 @@ pub fn test_cases_book_i_3_3_9_fixed_point_arithmetic(retval: &mut Vec<TestCase>
|
|||
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
|
||||
),
|
||||
[
|
||||
MOpRegNum::power_isa_gpr_reg_imm(4).value,
|
||||
MOpRegNum::const_zero().value,
|
||||
MOpRegNum::const_zero().value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm(4),
|
||||
MOpRegNum::const_zero(),
|
||||
MOpRegNum::const_zero(),
|
||||
],
|
||||
0.cast_to_static::<SInt<_>>(),
|
||||
OutputIntegerMode.Full64(),
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@ pub fn test_cases_book_i_3_3_10_fixed_point_compare(retval: &mut Vec<TestCase>)
|
|||
None,
|
||||
CompareMOp::compare_i(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
|
||||
[MOpRegNum::power_isa_gpr_reg_imm(4).value],
|
||||
[MOpRegNum::power_isa_gpr_reg_imm(4)],
|
||||
0x1234.cast_to_static::<SInt<_>>(),
|
||||
CompareMode.S32(),
|
||||
),
|
||||
|
|
@ -24,7 +24,7 @@ pub fn test_cases_book_i_3_3_10_fixed_point_compare(retval: &mut Vec<TestCase>)
|
|||
None,
|
||||
CompareMOp::compare_i(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
|
||||
[MOpRegNum::power_isa_gpr_reg_imm(4).value],
|
||||
[MOpRegNum::power_isa_gpr_reg_imm(4)],
|
||||
(0x89abu16 as i16).cast_to_static::<SInt<_>>(),
|
||||
CompareMode.S64(),
|
||||
),
|
||||
|
|
@ -36,8 +36,8 @@ pub fn test_cases_book_i_3_3_10_fixed_point_compare(retval: &mut Vec<TestCase>)
|
|||
CompareMOp::compare(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
|
||||
[
|
||||
MOpRegNum::power_isa_gpr_reg_imm(4).value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm(5).value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm(4),
|
||||
MOpRegNum::power_isa_gpr_reg_imm(5),
|
||||
],
|
||||
CompareMode.S32(),
|
||||
),
|
||||
|
|
@ -49,8 +49,8 @@ pub fn test_cases_book_i_3_3_10_fixed_point_compare(retval: &mut Vec<TestCase>)
|
|||
CompareMOp::compare(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
|
||||
[
|
||||
MOpRegNum::power_isa_gpr_reg_imm(4).value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm(5).value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm(4),
|
||||
MOpRegNum::power_isa_gpr_reg_imm(5),
|
||||
],
|
||||
CompareMode.S64(),
|
||||
),
|
||||
|
|
@ -61,7 +61,7 @@ pub fn test_cases_book_i_3_3_10_fixed_point_compare(retval: &mut Vec<TestCase>)
|
|||
None,
|
||||
CompareMOp::compare_i(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
|
||||
[MOpRegNum::power_isa_gpr_reg_imm(4).value],
|
||||
[MOpRegNum::power_isa_gpr_reg_imm(4)],
|
||||
0x1234.cast_to_static::<SInt<_>>(),
|
||||
CompareMode.U32(),
|
||||
),
|
||||
|
|
@ -72,7 +72,7 @@ pub fn test_cases_book_i_3_3_10_fixed_point_compare(retval: &mut Vec<TestCase>)
|
|||
None,
|
||||
CompareMOp::compare_i(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
|
||||
[MOpRegNum::power_isa_gpr_reg_imm(4).value],
|
||||
[MOpRegNum::power_isa_gpr_reg_imm(4)],
|
||||
0x89ab.cast_to_static::<SInt<_>>(),
|
||||
CompareMode.U64(),
|
||||
),
|
||||
|
|
@ -84,8 +84,8 @@ pub fn test_cases_book_i_3_3_10_fixed_point_compare(retval: &mut Vec<TestCase>)
|
|||
CompareMOp::compare(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
|
||||
[
|
||||
MOpRegNum::power_isa_gpr_reg_imm(4).value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm(5).value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm(4),
|
||||
MOpRegNum::power_isa_gpr_reg_imm(5),
|
||||
],
|
||||
CompareMode.U32(),
|
||||
),
|
||||
|
|
@ -97,8 +97,8 @@ pub fn test_cases_book_i_3_3_10_fixed_point_compare(retval: &mut Vec<TestCase>)
|
|||
CompareMOp::compare(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
|
||||
[
|
||||
MOpRegNum::power_isa_gpr_reg_imm(4).value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm(5).value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm(4),
|
||||
MOpRegNum::power_isa_gpr_reg_imm(5),
|
||||
],
|
||||
CompareMode.U64(),
|
||||
),
|
||||
|
|
@ -110,8 +110,8 @@ pub fn test_cases_book_i_3_3_10_fixed_point_compare(retval: &mut Vec<TestCase>)
|
|||
CompareMOp::compare(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
|
||||
[
|
||||
MOpRegNum::power_isa_gpr_reg_imm(4).value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm(5).value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm(4),
|
||||
MOpRegNum::power_isa_gpr_reg_imm(5),
|
||||
],
|
||||
CompareMode.CmpRBOne(),
|
||||
),
|
||||
|
|
@ -123,8 +123,8 @@ pub fn test_cases_book_i_3_3_10_fixed_point_compare(retval: &mut Vec<TestCase>)
|
|||
CompareMOp::compare(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
|
||||
[
|
||||
MOpRegNum::power_isa_gpr_reg_imm(4).value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm(5).value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm(4),
|
||||
MOpRegNum::power_isa_gpr_reg_imm(5),
|
||||
],
|
||||
CompareMode.CmpRBTwo(),
|
||||
),
|
||||
|
|
@ -136,8 +136,8 @@ pub fn test_cases_book_i_3_3_10_fixed_point_compare(retval: &mut Vec<TestCase>)
|
|||
CompareMOp::compare(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
|
||||
[
|
||||
MOpRegNum::power_isa_gpr_reg_imm(4).value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm(5).value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm(4),
|
||||
MOpRegNum::power_isa_gpr_reg_imm(5),
|
||||
],
|
||||
CompareMode.CmpEqB(),
|
||||
),
|
||||
|
|
|
|||
|
|
@ -26,11 +26,11 @@ pub fn test_cases_book_i_3_3_2_fixed_point_load(retval: &mut Vec<TestCase>) {
|
|||
MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]),
|
||||
[
|
||||
if $r != 0 || $ra == 0 {
|
||||
MOpRegNum::const_zero().value
|
||||
MOpRegNum::const_zero()
|
||||
} else {
|
||||
MOpRegNum::power_isa_gpr_reg_imm($ra).value
|
||||
MOpRegNum::power_isa_gpr_reg_imm($ra)
|
||||
},
|
||||
MOpRegNum::const_zero().value,
|
||||
MOpRegNum::const_zero(),
|
||||
],
|
||||
($disp as i64).cast_to_static::<SInt<_>>(),
|
||||
OutputIntegerMode.Full64(),
|
||||
|
|
@ -41,7 +41,7 @@ pub fn test_cases_book_i_3_3_2_fixed_point_load(retval: &mut Vec<TestCase>) {
|
|||
),
|
||||
LoadMOp::load(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[]),
|
||||
[MOpRegNum::power_isa_temp_reg().value],
|
||||
[MOpRegNum::power_isa_temp_reg()],
|
||||
LoadStoreWidth.$width(),
|
||||
LoadStoreConversion.$conversion(),
|
||||
),
|
||||
|
|
@ -65,11 +65,11 @@ pub fn test_cases_book_i_3_3_2_fixed_point_load(retval: &mut Vec<TestCase>) {
|
|||
MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]),
|
||||
[
|
||||
if $ra == 0 {
|
||||
MOpRegNum::const_zero().value
|
||||
MOpRegNum::const_zero()
|
||||
} else {
|
||||
MOpRegNum::power_isa_gpr_reg_imm($ra).value
|
||||
MOpRegNum::power_isa_gpr_reg_imm($ra)
|
||||
},
|
||||
MOpRegNum::const_zero().value,
|
||||
MOpRegNum::const_zero(),
|
||||
],
|
||||
($disp as i64).cast_to_static::<SInt<_>>(),
|
||||
OutputIntegerMode.Full64(),
|
||||
|
|
@ -80,7 +80,7 @@ pub fn test_cases_book_i_3_3_2_fixed_point_load(retval: &mut Vec<TestCase>) {
|
|||
),
|
||||
LoadMOp::load(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[]),
|
||||
[MOpRegNum::power_isa_temp_reg().value],
|
||||
[MOpRegNum::power_isa_temp_reg()],
|
||||
LoadStoreWidth.$width(),
|
||||
LoadStoreConversion.$conversion(),
|
||||
),
|
||||
|
|
@ -103,8 +103,8 @@ pub fn test_cases_book_i_3_3_2_fixed_point_load(retval: &mut Vec<TestCase>) {
|
|||
AddSubMOp::add_sub_i(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($ra)], &[]),
|
||||
[
|
||||
MOpRegNum::power_isa_gpr_reg_imm($ra).value,
|
||||
MOpRegNum::const_zero().value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm($ra),
|
||||
MOpRegNum::const_zero(),
|
||||
],
|
||||
($disp as i64).cast_to_static::<SInt<_>>(),
|
||||
OutputIntegerMode.Full64(),
|
||||
|
|
@ -115,7 +115,7 @@ pub fn test_cases_book_i_3_3_2_fixed_point_load(retval: &mut Vec<TestCase>) {
|
|||
),
|
||||
LoadMOp::load(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[]),
|
||||
[MOpRegNum::power_isa_gpr_reg_imm($ra).value],
|
||||
[MOpRegNum::power_isa_gpr_reg_imm($ra)],
|
||||
LoadStoreWidth.$width(),
|
||||
LoadStoreConversion.$conversion(),
|
||||
),
|
||||
|
|
@ -139,11 +139,11 @@ pub fn test_cases_book_i_3_3_2_fixed_point_load(retval: &mut Vec<TestCase>) {
|
|||
MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]),
|
||||
[
|
||||
if $ra == 0 {
|
||||
MOpRegNum::const_zero().value
|
||||
MOpRegNum::const_zero()
|
||||
} else {
|
||||
MOpRegNum::power_isa_gpr_reg_imm($ra).value
|
||||
MOpRegNum::power_isa_gpr_reg_imm($ra)
|
||||
},
|
||||
MOpRegNum::power_isa_gpr_reg_imm($rb).value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm($rb),
|
||||
],
|
||||
0.cast_to_static::<SInt<_>>(),
|
||||
OutputIntegerMode.Full64(),
|
||||
|
|
@ -154,7 +154,7 @@ pub fn test_cases_book_i_3_3_2_fixed_point_load(retval: &mut Vec<TestCase>) {
|
|||
),
|
||||
LoadMOp::load(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[]),
|
||||
[MOpRegNum::power_isa_temp_reg().value],
|
||||
[MOpRegNum::power_isa_temp_reg()],
|
||||
LoadStoreWidth.$width(),
|
||||
LoadStoreConversion.$conversion(),
|
||||
),
|
||||
|
|
@ -177,8 +177,8 @@ pub fn test_cases_book_i_3_3_2_fixed_point_load(retval: &mut Vec<TestCase>) {
|
|||
AddSubMOp::add_sub_i(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($ra)], &[]),
|
||||
[
|
||||
MOpRegNum::power_isa_gpr_reg_imm($ra).value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm($rb).value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm($ra),
|
||||
MOpRegNum::power_isa_gpr_reg_imm($rb),
|
||||
],
|
||||
0.cast_to_static::<SInt<_>>(),
|
||||
OutputIntegerMode.Full64(),
|
||||
|
|
@ -189,7 +189,7 @@ pub fn test_cases_book_i_3_3_2_fixed_point_load(retval: &mut Vec<TestCase>) {
|
|||
),
|
||||
LoadMOp::load(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[]),
|
||||
[MOpRegNum::power_isa_gpr_reg_imm($ra).value],
|
||||
[MOpRegNum::power_isa_gpr_reg_imm($ra)],
|
||||
LoadStoreWidth.$width(),
|
||||
LoadStoreConversion.$conversion(),
|
||||
),
|
||||
|
|
|
|||
|
|
@ -34,7 +34,7 @@ pub fn test_cases_book_i_3_3_13_fixed_point_logical(retval: &mut Vec<TestCase>)
|
|||
&[]
|
||||
},
|
||||
),
|
||||
[MOpRegNum::power_isa_gpr_reg_imm($src).value],
|
||||
[MOpRegNum::power_isa_gpr_reg_imm($src)],
|
||||
(($imm as u32) << if $mnemonic.contains('s') { 16 } else { 0 })
|
||||
.cast_to_static::<SInt<_>>(),
|
||||
OutputIntegerMode.Full64(),
|
||||
|
|
@ -108,8 +108,8 @@ pub fn test_cases_book_i_3_3_13_fixed_point_logical(retval: &mut Vec<TestCase>)
|
|||
},
|
||||
),
|
||||
[
|
||||
MOpRegNum::power_isa_gpr_reg_imm($src0).value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm($src1).value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm($src0),
|
||||
MOpRegNum::power_isa_gpr_reg_imm($src1),
|
||||
],
|
||||
0.cast_to_static::<SInt<_>>(),
|
||||
OutputIntegerMode.Full64(),
|
||||
|
|
@ -159,7 +159,7 @@ pub fn test_cases_book_i_3_3_13_fixed_point_logical(retval: &mut Vec<TestCase>)
|
|||
None,
|
||||
MoveRegMOp::move_reg(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
|
||||
[MOpRegNum::power_isa_gpr_reg_imm(4).value],
|
||||
[MOpRegNum::power_isa_gpr_reg_imm(4)],
|
||||
0.cast_to_static::<SInt<_>>(),
|
||||
),
|
||||
));
|
||||
|
|
@ -232,7 +232,7 @@ pub fn test_cases_book_i_3_3_13_fixed_point_logical(retval: &mut Vec<TestCase>)
|
|||
&[]
|
||||
},
|
||||
),
|
||||
[MOpRegNum::power_isa_gpr_reg_imm($src).value],
|
||||
[MOpRegNum::power_isa_gpr_reg_imm($src)],
|
||||
0.cast_to_static::<SInt<_>>(),
|
||||
OutputIntegerMode.$OutputIntegerMode(),
|
||||
Lut4::from_fn(|a, b| a | b),
|
||||
|
|
|
|||
|
|
@ -95,9 +95,9 @@ pub fn test_cases_book_i_3_3_14_fixed_point_rotate_and_shift(retval: &mut Vec<Te
|
|||
ShiftRotateMOp::shift_rotate(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[]),
|
||||
[
|
||||
MOpRegNum::power_isa_gpr_reg_imm($src).value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm($src).value,
|
||||
src2.value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm($src),
|
||||
MOpRegNum::power_isa_gpr_reg_imm($src),
|
||||
src2,
|
||||
],
|
||||
&imm,
|
||||
OutputIntegerMode.Full64(),
|
||||
|
|
@ -121,9 +121,9 @@ pub fn test_cases_book_i_3_3_14_fixed_point_rotate_and_shift(retval: &mut Vec<Te
|
|||
ShiftRotateMOp::shift_rotate(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],),
|
||||
[
|
||||
MOpRegNum::power_isa_gpr_reg_imm($src).value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm($src).value,
|
||||
src2.value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm($src),
|
||||
MOpRegNum::power_isa_gpr_reg_imm($src),
|
||||
src2,
|
||||
],
|
||||
imm,
|
||||
OutputIntegerMode.Full64(),
|
||||
|
|
@ -156,9 +156,9 @@ pub fn test_cases_book_i_3_3_14_fixed_point_rotate_and_shift(retval: &mut Vec<Te
|
|||
ShiftRotateMOp::shift_rotate(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[]),
|
||||
[
|
||||
MOpRegNum::power_isa_gpr_reg_imm($src).value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm($src).value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm($amount).value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm($src),
|
||||
MOpRegNum::power_isa_gpr_reg_imm($src),
|
||||
MOpRegNum::power_isa_gpr_reg_imm($amount),
|
||||
],
|
||||
rotate_imm(None, $rotated_output_start_and_len, false),
|
||||
OutputIntegerMode.Full64(),
|
||||
|
|
@ -182,9 +182,9 @@ pub fn test_cases_book_i_3_3_14_fixed_point_rotate_and_shift(retval: &mut Vec<Te
|
|||
ShiftRotateMOp::shift_rotate(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],),
|
||||
[
|
||||
MOpRegNum::power_isa_gpr_reg_imm($src).value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm($src).value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm($amount).value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm($src),
|
||||
MOpRegNum::power_isa_gpr_reg_imm($src),
|
||||
MOpRegNum::power_isa_gpr_reg_imm($amount),
|
||||
],
|
||||
rotate_imm(None, $rotated_output_start_and_len, false),
|
||||
OutputIntegerMode.Full64(),
|
||||
|
|
@ -739,9 +739,9 @@ pub fn test_cases_book_i_3_3_14_fixed_point_rotate_and_shift(retval: &mut Vec<Te
|
|||
ShiftRotateMOp::shift_rotate(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[]),
|
||||
[
|
||||
MOpRegNum::power_isa_gpr_reg_imm($src).value,
|
||||
MOpRegNum::const_zero().value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm($amount).value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm($src),
|
||||
MOpRegNum::const_zero(),
|
||||
MOpRegNum::power_isa_gpr_reg_imm($amount),
|
||||
],
|
||||
shift_imm(None, false),
|
||||
OutputIntegerMode.Full64(),
|
||||
|
|
@ -766,9 +766,9 @@ pub fn test_cases_book_i_3_3_14_fixed_point_rotate_and_shift(retval: &mut Vec<Te
|
|||
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
|
||||
),
|
||||
[
|
||||
MOpRegNum::power_isa_gpr_reg_imm($src).value,
|
||||
MOpRegNum::const_zero().value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm($amount).value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm($src),
|
||||
MOpRegNum::const_zero(),
|
||||
MOpRegNum::power_isa_gpr_reg_imm($amount),
|
||||
],
|
||||
shift_imm(None, false),
|
||||
OutputIntegerMode.Full64(),
|
||||
|
|
@ -798,9 +798,9 @@ pub fn test_cases_book_i_3_3_14_fixed_point_rotate_and_shift(retval: &mut Vec<Te
|
|||
ShiftRotateMOp::shift_rotate(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[]),
|
||||
[
|
||||
MOpRegNum::const_zero().value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm($src).value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm($amount).value,
|
||||
MOpRegNum::const_zero(),
|
||||
MOpRegNum::power_isa_gpr_reg_imm($src),
|
||||
MOpRegNum::power_isa_gpr_reg_imm($amount),
|
||||
],
|
||||
shift_imm(None, true),
|
||||
OutputIntegerMode.Full64(),
|
||||
|
|
@ -825,9 +825,9 @@ pub fn test_cases_book_i_3_3_14_fixed_point_rotate_and_shift(retval: &mut Vec<Te
|
|||
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
|
||||
),
|
||||
[
|
||||
MOpRegNum::const_zero().value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm($src).value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm($amount).value,
|
||||
MOpRegNum::const_zero(),
|
||||
MOpRegNum::power_isa_gpr_reg_imm($src),
|
||||
MOpRegNum::power_isa_gpr_reg_imm($amount),
|
||||
],
|
||||
shift_imm(None, true),
|
||||
OutputIntegerMode.Full64(),
|
||||
|
|
@ -863,9 +863,9 @@ pub fn test_cases_book_i_3_3_14_fixed_point_rotate_and_shift(retval: &mut Vec<Te
|
|||
&[],
|
||||
),
|
||||
[
|
||||
MOpRegNum::power_isa_gpr_reg_imm($src).value,
|
||||
MOpRegNum::const_zero().value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm($amount).value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm($src),
|
||||
MOpRegNum::const_zero(),
|
||||
MOpRegNum::power_isa_gpr_reg_imm($amount),
|
||||
],
|
||||
shift_imm(None, true),
|
||||
OutputIntegerMode.Full64(),
|
||||
|
|
@ -893,9 +893,9 @@ pub fn test_cases_book_i_3_3_14_fixed_point_rotate_and_shift(retval: &mut Vec<Te
|
|||
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
|
||||
),
|
||||
[
|
||||
MOpRegNum::power_isa_gpr_reg_imm($src).value,
|
||||
MOpRegNum::const_zero().value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm($amount).value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm($src),
|
||||
MOpRegNum::const_zero(),
|
||||
MOpRegNum::power_isa_gpr_reg_imm($amount),
|
||||
],
|
||||
shift_imm(None, true),
|
||||
OutputIntegerMode.Full64(),
|
||||
|
|
@ -931,9 +931,9 @@ pub fn test_cases_book_i_3_3_14_fixed_point_rotate_and_shift(retval: &mut Vec<Te
|
|||
&[],
|
||||
),
|
||||
[
|
||||
MOpRegNum::power_isa_gpr_reg_imm($src).value,
|
||||
MOpRegNum::const_zero().value,
|
||||
MOpRegNum::const_zero().value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm($src),
|
||||
MOpRegNum::const_zero(),
|
||||
MOpRegNum::const_zero(),
|
||||
],
|
||||
shift_imm(Some($amount), true),
|
||||
OutputIntegerMode.Full64(),
|
||||
|
|
@ -961,9 +961,9 @@ pub fn test_cases_book_i_3_3_14_fixed_point_rotate_and_shift(retval: &mut Vec<Te
|
|||
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
|
||||
),
|
||||
[
|
||||
MOpRegNum::power_isa_gpr_reg_imm($src).value,
|
||||
MOpRegNum::const_zero().value,
|
||||
MOpRegNum::const_zero().value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm($src),
|
||||
MOpRegNum::const_zero(),
|
||||
MOpRegNum::const_zero(),
|
||||
],
|
||||
shift_imm(Some($amount), true),
|
||||
OutputIntegerMode.Full64(),
|
||||
|
|
@ -1072,9 +1072,9 @@ pub fn test_cases_book_i_3_3_14_fixed_point_rotate_and_shift(retval: &mut Vec<Te
|
|||
ShiftRotateMOp::shift_rotate(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[]),
|
||||
[
|
||||
MOpRegNum::power_isa_gpr_reg_imm($src).value,
|
||||
MOpRegNum::const_zero().value,
|
||||
MOpRegNum::const_zero().value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm($src),
|
||||
MOpRegNum::const_zero(),
|
||||
MOpRegNum::const_zero(),
|
||||
],
|
||||
shift_imm(Some($amount), false),
|
||||
OutputIntegerMode.Full64(),
|
||||
|
|
@ -1099,9 +1099,9 @@ pub fn test_cases_book_i_3_3_14_fixed_point_rotate_and_shift(retval: &mut Vec<Te
|
|||
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
|
||||
),
|
||||
[
|
||||
MOpRegNum::power_isa_gpr_reg_imm($src).value,
|
||||
MOpRegNum::const_zero().value,
|
||||
MOpRegNum::const_zero().value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm($src),
|
||||
MOpRegNum::const_zero(),
|
||||
MOpRegNum::const_zero(),
|
||||
],
|
||||
shift_imm(Some($amount), false),
|
||||
OutputIntegerMode.Full64(),
|
||||
|
|
|
|||
|
|
@ -25,11 +25,11 @@ pub fn test_cases_book_i_3_3_3_fixed_point_store(retval: &mut Vec<TestCase>) {
|
|||
MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]),
|
||||
[
|
||||
if $r != 0 || $ra == 0 {
|
||||
MOpRegNum::const_zero().value
|
||||
MOpRegNum::const_zero()
|
||||
} else {
|
||||
MOpRegNum::power_isa_gpr_reg_imm($ra).value
|
||||
MOpRegNum::power_isa_gpr_reg_imm($ra)
|
||||
},
|
||||
MOpRegNum::const_zero().value,
|
||||
MOpRegNum::const_zero(),
|
||||
],
|
||||
($disp as i64).cast_to_static::<SInt<_>>(),
|
||||
OutputIntegerMode.Full64(),
|
||||
|
|
@ -41,8 +41,8 @@ pub fn test_cases_book_i_3_3_3_fixed_point_store(retval: &mut Vec<TestCase>) {
|
|||
StoreMOp::store(
|
||||
MOpDestReg::new_sim(&[], &[]),
|
||||
[
|
||||
MOpRegNum::power_isa_temp_reg().value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm($rs).value,
|
||||
MOpRegNum::power_isa_temp_reg(),
|
||||
MOpRegNum::power_isa_gpr_reg_imm($rs),
|
||||
],
|
||||
LoadStoreWidth.$width(),
|
||||
LoadStoreConversion.ZeroExt(),
|
||||
|
|
@ -66,11 +66,11 @@ pub fn test_cases_book_i_3_3_3_fixed_point_store(retval: &mut Vec<TestCase>) {
|
|||
MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]),
|
||||
[
|
||||
if $ra == 0 {
|
||||
MOpRegNum::const_zero().value
|
||||
MOpRegNum::const_zero()
|
||||
} else {
|
||||
MOpRegNum::power_isa_gpr_reg_imm($ra).value
|
||||
MOpRegNum::power_isa_gpr_reg_imm($ra)
|
||||
},
|
||||
MOpRegNum::const_zero().value,
|
||||
MOpRegNum::const_zero(),
|
||||
],
|
||||
($disp as i64).cast_to_static::<SInt<_>>(),
|
||||
OutputIntegerMode.Full64(),
|
||||
|
|
@ -82,8 +82,8 @@ pub fn test_cases_book_i_3_3_3_fixed_point_store(retval: &mut Vec<TestCase>) {
|
|||
StoreMOp::store(
|
||||
MOpDestReg::new_sim(&[], &[]),
|
||||
[
|
||||
MOpRegNum::power_isa_temp_reg().value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm($rs).value,
|
||||
MOpRegNum::power_isa_temp_reg(),
|
||||
MOpRegNum::power_isa_gpr_reg_imm($rs),
|
||||
],
|
||||
LoadStoreWidth.$width(),
|
||||
LoadStoreConversion.ZeroExt(),
|
||||
|
|
@ -107,8 +107,8 @@ pub fn test_cases_book_i_3_3_3_fixed_point_store(retval: &mut Vec<TestCase>) {
|
|||
AddSubMOp::add_sub_i(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]),
|
||||
[
|
||||
MOpRegNum::power_isa_gpr_reg_imm($ra).value,
|
||||
MOpRegNum::const_zero().value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm($ra),
|
||||
MOpRegNum::const_zero(),
|
||||
],
|
||||
($disp as i64).cast_to_static::<SInt<_>>(),
|
||||
OutputIntegerMode.Full64(),
|
||||
|
|
@ -120,15 +120,15 @@ pub fn test_cases_book_i_3_3_3_fixed_point_store(retval: &mut Vec<TestCase>) {
|
|||
StoreMOp::store(
|
||||
MOpDestReg::new_sim(&[], &[]),
|
||||
[
|
||||
MOpRegNum::power_isa_temp_reg().value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm($rs).value,
|
||||
MOpRegNum::power_isa_temp_reg(),
|
||||
MOpRegNum::power_isa_gpr_reg_imm($rs),
|
||||
],
|
||||
LoadStoreWidth.$width(),
|
||||
LoadStoreConversion.ZeroExt(),
|
||||
),
|
||||
MoveRegMOp::move_reg(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($ra)], &[]),
|
||||
[MOpRegNum::power_isa_temp_reg().value],
|
||||
[MOpRegNum::power_isa_temp_reg()],
|
||||
0.cast_to_static::<SInt<_>>(),
|
||||
),
|
||||
],
|
||||
|
|
@ -142,8 +142,8 @@ pub fn test_cases_book_i_3_3_3_fixed_point_store(retval: &mut Vec<TestCase>) {
|
|||
AddSubMOp::add_sub_i(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($ra)], &[]),
|
||||
[
|
||||
MOpRegNum::power_isa_gpr_reg_imm($ra).value,
|
||||
MOpRegNum::const_zero().value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm($ra),
|
||||
MOpRegNum::const_zero(),
|
||||
],
|
||||
($disp as i64).cast_to_static::<SInt<_>>(),
|
||||
OutputIntegerMode.Full64(),
|
||||
|
|
@ -155,8 +155,8 @@ pub fn test_cases_book_i_3_3_3_fixed_point_store(retval: &mut Vec<TestCase>) {
|
|||
StoreMOp::store(
|
||||
MOpDestReg::new_sim(&[], &[]),
|
||||
[
|
||||
MOpRegNum::power_isa_gpr_reg_imm($ra).value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm($rs).value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm($ra),
|
||||
MOpRegNum::power_isa_gpr_reg_imm($rs),
|
||||
],
|
||||
LoadStoreWidth.$width(),
|
||||
LoadStoreConversion.ZeroExt(),
|
||||
|
|
@ -181,11 +181,11 @@ pub fn test_cases_book_i_3_3_3_fixed_point_store(retval: &mut Vec<TestCase>) {
|
|||
MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]),
|
||||
[
|
||||
if $ra == 0 {
|
||||
MOpRegNum::const_zero().value
|
||||
MOpRegNum::const_zero()
|
||||
} else {
|
||||
MOpRegNum::power_isa_gpr_reg_imm($ra).value
|
||||
MOpRegNum::power_isa_gpr_reg_imm($ra)
|
||||
},
|
||||
MOpRegNum::power_isa_gpr_reg_imm($rb).value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm($rb),
|
||||
],
|
||||
0.cast_to_static::<SInt<_>>(),
|
||||
OutputIntegerMode.Full64(),
|
||||
|
|
@ -197,8 +197,8 @@ pub fn test_cases_book_i_3_3_3_fixed_point_store(retval: &mut Vec<TestCase>) {
|
|||
StoreMOp::store(
|
||||
MOpDestReg::new_sim(&[], &[]),
|
||||
[
|
||||
MOpRegNum::power_isa_temp_reg().value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm($rs).value,
|
||||
MOpRegNum::power_isa_temp_reg(),
|
||||
MOpRegNum::power_isa_gpr_reg_imm($rs),
|
||||
],
|
||||
LoadStoreWidth.$width(),
|
||||
LoadStoreConversion.ZeroExt(),
|
||||
|
|
@ -222,8 +222,8 @@ pub fn test_cases_book_i_3_3_3_fixed_point_store(retval: &mut Vec<TestCase>) {
|
|||
AddSubMOp::add_sub_i(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]),
|
||||
[
|
||||
MOpRegNum::power_isa_gpr_reg_imm($ra).value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm($rb).value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm($ra),
|
||||
MOpRegNum::power_isa_gpr_reg_imm($rb),
|
||||
],
|
||||
0.cast_to_static::<SInt<_>>(),
|
||||
OutputIntegerMode.Full64(),
|
||||
|
|
@ -235,15 +235,15 @@ pub fn test_cases_book_i_3_3_3_fixed_point_store(retval: &mut Vec<TestCase>) {
|
|||
StoreMOp::store(
|
||||
MOpDestReg::new_sim(&[], &[]),
|
||||
[
|
||||
MOpRegNum::power_isa_temp_reg().value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm($rs).value,
|
||||
MOpRegNum::power_isa_temp_reg(),
|
||||
MOpRegNum::power_isa_gpr_reg_imm($rs),
|
||||
],
|
||||
LoadStoreWidth.$width(),
|
||||
LoadStoreConversion.ZeroExt(),
|
||||
),
|
||||
MoveRegMOp::move_reg(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($ra)], &[]),
|
||||
[MOpRegNum::power_isa_temp_reg().value],
|
||||
[MOpRegNum::power_isa_temp_reg()],
|
||||
0.cast_to_static::<SInt<_>>(),
|
||||
),
|
||||
],
|
||||
|
|
@ -258,11 +258,11 @@ pub fn test_cases_book_i_3_3_3_fixed_point_store(retval: &mut Vec<TestCase>) {
|
|||
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($ra)], &[]),
|
||||
[
|
||||
if $ra == 0 {
|
||||
MOpRegNum::const_zero().value
|
||||
MOpRegNum::const_zero()
|
||||
} else {
|
||||
MOpRegNum::power_isa_gpr_reg_imm($ra).value
|
||||
MOpRegNum::power_isa_gpr_reg_imm($ra)
|
||||
},
|
||||
MOpRegNum::power_isa_gpr_reg_imm($rb).value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm($rb),
|
||||
],
|
||||
0.cast_to_static::<SInt<_>>(),
|
||||
OutputIntegerMode.Full64(),
|
||||
|
|
@ -274,8 +274,8 @@ pub fn test_cases_book_i_3_3_3_fixed_point_store(retval: &mut Vec<TestCase>) {
|
|||
StoreMOp::store(
|
||||
MOpDestReg::new_sim(&[], &[]),
|
||||
[
|
||||
MOpRegNum::power_isa_gpr_reg_imm($ra).value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm($rs).value,
|
||||
MOpRegNum::power_isa_gpr_reg_imm($ra),
|
||||
MOpRegNum::power_isa_gpr_reg_imm($rs),
|
||||
],
|
||||
LoadStoreWidth.$width(),
|
||||
LoadStoreConversion.ZeroExt(),
|
||||
|
|
|
|||
|
|
@ -30,9 +30,9 @@ pub fn test_cases_book_i_3_3_19_move_to_from_system_register(retval: &mut Vec<Te
|
|||
LogicalFlagsMOp::logical_flags(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
|
||||
[
|
||||
MOpRegNum::power_isa_xer_ca_ca32_reg().value,
|
||||
MOpRegNum::const_zero().value,
|
||||
MOpRegNum::power_isa_xer_so_ov_ov32_reg().value,
|
||||
MOpRegNum::power_isa_xer_ca_ca32_reg(),
|
||||
MOpRegNum::const_zero(),
|
||||
MOpRegNum::power_isa_xer_so_ov_ov32_reg(),
|
||||
],
|
||||
mcrxrx_imm(),
|
||||
Lut4::from_fn(|a, b| a | b),
|
||||
|
|
@ -48,7 +48,7 @@ pub fn test_cases_book_iii_5_4_4_move_to_from_system_register(retval: &mut Vec<T
|
|||
None,
|
||||
MoveRegMOp::move_reg(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
|
||||
[MOpRegNum::power_isa_lr_reg().value],
|
||||
[MOpRegNum::power_isa_lr_reg()],
|
||||
0.cast_to_static::<SInt<_>>(),
|
||||
),
|
||||
));
|
||||
|
|
@ -58,7 +58,7 @@ pub fn test_cases_book_iii_5_4_4_move_to_from_system_register(retval: &mut Vec<T
|
|||
None,
|
||||
MoveRegMOp::move_reg(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_LR_REG_NUM], &[]),
|
||||
[MOpRegNum::power_isa_gpr_reg_imm(3).value],
|
||||
[MOpRegNum::power_isa_gpr_reg_imm(3)],
|
||||
0.cast_to_static::<SInt<_>>(),
|
||||
),
|
||||
));
|
||||
|
|
@ -68,7 +68,7 @@ pub fn test_cases_book_iii_5_4_4_move_to_from_system_register(retval: &mut Vec<T
|
|||
None,
|
||||
MoveRegMOp::move_reg(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
|
||||
[MOpRegNum::power_isa_ctr_reg().value],
|
||||
[MOpRegNum::power_isa_ctr_reg()],
|
||||
0.cast_to_static::<SInt<_>>(),
|
||||
),
|
||||
));
|
||||
|
|
@ -78,7 +78,7 @@ pub fn test_cases_book_iii_5_4_4_move_to_from_system_register(retval: &mut Vec<T
|
|||
None,
|
||||
MoveRegMOp::move_reg(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_CTR_REG_NUM], &[]),
|
||||
[MOpRegNum::power_isa_gpr_reg_imm(3).value],
|
||||
[MOpRegNum::power_isa_gpr_reg_imm(3)],
|
||||
0.cast_to_static::<SInt<_>>(),
|
||||
),
|
||||
));
|
||||
|
|
@ -88,7 +88,7 @@ pub fn test_cases_book_iii_5_4_4_move_to_from_system_register(retval: &mut Vec<T
|
|||
None,
|
||||
MoveRegMOp::move_reg(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
|
||||
[MOpRegNum::power_isa_tar_reg().value],
|
||||
[MOpRegNum::power_isa_tar_reg()],
|
||||
0.cast_to_static::<SInt<_>>(),
|
||||
),
|
||||
));
|
||||
|
|
@ -98,7 +98,7 @@ pub fn test_cases_book_iii_5_4_4_move_to_from_system_register(retval: &mut Vec<T
|
|||
None,
|
||||
MoveRegMOp::move_reg(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TAR_REG_NUM], &[]),
|
||||
[MOpRegNum::power_isa_gpr_reg_imm(3).value],
|
||||
[MOpRegNum::power_isa_gpr_reg_imm(3)],
|
||||
0.cast_to_static::<SInt<_>>(),
|
||||
),
|
||||
));
|
||||
|
|
@ -109,7 +109,7 @@ pub fn test_cases_book_iii_5_4_4_move_to_from_system_register(retval: &mut Vec<T
|
|||
None,
|
||||
ReadSpecialMOp::read_special(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
|
||||
[MOpRegNum::const_zero().value; 0],
|
||||
[MOpRegNum::const_zero(); 0],
|
||||
ReadSpecialMOpImm.PowerIsaTimeBase(),
|
||||
),
|
||||
));
|
||||
|
|
@ -120,7 +120,7 @@ pub fn test_cases_book_iii_5_4_4_move_to_from_system_register(retval: &mut Vec<T
|
|||
None,
|
||||
ReadSpecialMOp::read_special(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
|
||||
[MOpRegNum::const_zero().value; 0],
|
||||
[MOpRegNum::const_zero(); 0],
|
||||
ReadSpecialMOpImm.PowerIsaTimeBaseU(),
|
||||
),
|
||||
));
|
||||
|
|
@ -131,7 +131,7 @@ pub fn test_cases_book_iii_5_4_4_move_to_from_system_register(retval: &mut Vec<T
|
|||
None,
|
||||
ReadSpecialMOp::read_special(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
|
||||
[MOpRegNum::const_zero().value; 0],
|
||||
[MOpRegNum::const_zero(); 0],
|
||||
ReadSpecialMOpImm.PowerIsaTimeBase(),
|
||||
),
|
||||
));
|
||||
|
|
@ -142,7 +142,7 @@ pub fn test_cases_book_iii_5_4_4_move_to_from_system_register(retval: &mut Vec<T
|
|||
None,
|
||||
ReadSpecialMOp::read_special(
|
||||
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
|
||||
[MOpRegNum::const_zero().value; 0],
|
||||
[MOpRegNum::const_zero(); 0],
|
||||
ReadSpecialMOpImm.PowerIsaTimeBaseU(),
|
||||
),
|
||||
));
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue