format code

.forgejo/workflows/test.yml

@@ -4,6 +4,7 @@ on: [push, pull_request]
 
 jobs:
   deps:
+    runs-on: debian-12
     uses: ./.forgejo/workflows/deps.yml
   test:
     runs-on: debian-12
@@ -38,7 +39,7 @@ jobs:
             z3 \
             zlib1g-dev
       - run: |
-          curl --proto '=https' --tlsv1.2 -sSf https://sh.rustup.rs | sh -s -- -y --default-toolchain 1.82.0
+          curl --proto '=https' --tlsv1.2 -sSf https://sh.rustup.rs | sh -s -- -y --default-toolchain 1.89.0
           source "$HOME/.cargo/env"
           echo "$PATH" >> "$GITHUB_PATH"
       - uses: https://git.libre-chip.org/mirrors/cache/restore@v3

Cargo.toml

@@ -7,11 +7,11 @@ members = ["crates/*"]
 [workspace.package]
 version = "0.1.0"
 license = "LGPL-3.0-or-later"
-edition = "2021"
+edition = "2024"
 repository = ""
 keywords = []
 categories = []
-rust-version = "1.82.0"
+rust-version = "1.89.0"
 
 [workspace.dependencies]
 fayalite = { git = "https://git.libre-chip.org/libre-chip/fayalite.git", version = "0.3.0", branch = "master" }

crates/cpu/src/config.rs

@@ -1,10 +1,10 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information
 use crate::{
-    instruction::{MOpTrait, PRegNum, RenamedMOp, UnitNum, UnitOutRegNum, CONST_ZERO_UNIT_NUM},
+    instruction::{CONST_ZERO_UNIT_NUM, MOpTrait, PRegNum, RenamedMOp, UnitNum, UnitOutRegNum},
     unit::{
-        unit_base::{UnitForwardingInfo, UnitToRegAlloc},
         UnitCancelInput, UnitKind, UnitOutputWrite,
+        unit_base::{UnitForwardingInfo, UnitToRegAlloc},
     },
 };
 use fayalite::prelude::*;

crates/cpu/src/instruction.rs

@@ -25,10 +25,7 @@ impl<T: MOpTrait> MOpInto<T> for T {
 }
 
 pub trait MOpTrait: Type {
-    type Mapped<NewDestReg: Type, NewSrcRegWidth: Size>: MOpTrait<
-        DestReg = NewDestReg,
-        SrcRegWidth = NewSrcRegWidth,
-    >;
+    type Mapped<NewDestReg: Type, NewSrcRegWidth: Size>: MOpTrait<DestReg = NewDestReg, SrcRegWidth = NewSrcRegWidth>;
     type DestReg: Type;
     type SrcRegWidth: Size;
     fn dest_reg_ty(self) -> Self::DestReg;
@@ -73,11 +70,11 @@ pub trait CommonMOpTrait: MOpTrait {
     type PrefixPad: KnownSize;
     type SrcCount: KnownSize;
     type CommonMOpTraitMapped<NewDestReg: Type, NewSrcRegWidth: Size>: CommonMOpTrait<
-        DestReg = NewDestReg,
-        SrcRegWidth = NewSrcRegWidth,
-        PrefixPad = Self::PrefixPad,
-        SrcCount = Self::SrcCount,
-    >;
+            DestReg = NewDestReg,
+            SrcRegWidth = NewSrcRegWidth,
+            PrefixPad = Self::PrefixPad,
+            SrcCount = Self::SrcCount,
+        >;
     type CommonMOpTraitDestReg: Type;
     type CommonMOpTraitSrcRegWidth: Size;
     fn common_mop_ty(

crates/cpu/src/reg_alloc.rs

@@ -3,18 +3,18 @@
 use crate::{
     config::CpuConfig,
     instruction::{
-        MOp, MOpDestReg, MOpRegNum, MOpTrait, MoveRegMOp, PRegNum, RenameTableName, UnitOutRegNum,
-        COMMON_MOP_SRC_LEN,
+        COMMON_MOP_SRC_LEN, MOp, MOpDestReg, MOpRegNum, MOpTrait, MoveRegMOp, PRegNum,
+        RenameTableName, UnitOutRegNum,
     },
     unit::{
-        unit_base::{UnitForwardingInfo, UnitInput},
         GlobalState, TrapData, UnitMOp, UnitOutput, UnitOutputWrite, UnitResult,
         UnitResultCompleted, UnitTrait,
+        unit_base::{UnitForwardingInfo, UnitInput},
     },
     util::tree_reduce::tree_reduce_with_state,
 };
 use fayalite::{
-    memory::{splat_mask, WriteStruct},
+    memory::{WriteStruct, splat_mask},
     module::{instance_with_loc, memory_with_loc, wire_with_loc},
     prelude::*,
     util::ready_valid::ReadyValid,

crates/cpu/src/unit.rs

@@ -4,8 +4,8 @@
 use crate::{
     config::CpuConfig,
     instruction::{
-        mop_enum, AluBranchMOp, LoadStoreMOp, MOp, MOpDestReg, MOpInto, MOpRegNum, MOpTrait,
-        RenamedMOp, UnitOutRegNum,
+        AluBranchMOp, LoadStoreMOp, MOp, MOpDestReg, MOpInto, MOpRegNum, MOpTrait, RenamedMOp,
+        UnitOutRegNum, mop_enum,
     },
     register::{FlagsMode, PRegValue},
     unit::unit_base::UnitToRegAlloc,

crates/cpu/src/unit/alu_branch.rs

@@ -4,14 +4,14 @@
 use crate::{
     config::CpuConfig,
     instruction::{
-        AddSubMOp, AluBranchMOp, AluCommonMOp, CommonMOp, LogicalMOp, MOpTrait, OutputIntegerMode,
-        RenamedMOp, UnitOutRegNum, COMMON_MOP_SRC_LEN,
+        AddSubMOp, AluBranchMOp, AluCommonMOp, COMMON_MOP_SRC_LEN, CommonMOp, LogicalMOp, MOpTrait,
+        OutputIntegerMode, RenamedMOp, UnitOutRegNum,
     },
     register::{FlagsMode, PRegFlagsPowerISA, PRegFlagsX86, PRegValue},
     unit::{
-        unit_base::{unit_base, ExecuteEnd, ExecuteStart, UnitToRegAlloc},
         DynUnit, DynUnitWrapper, GlobalState, UnitKind, UnitMOp, UnitOutput, UnitResult,
         UnitResultCompleted, UnitTrait,
+        unit_base::{ExecuteEnd, ExecuteStart, UnitToRegAlloc, unit_base},
     },
 };
 use fayalite::{

crates/cpu/src/unit/unit_base.rs

@@ -3,7 +3,7 @@
 
 use crate::{
     config::CpuConfig,
-    instruction::{MOpTrait, PRegNum, UnitNum, UnitOutRegNum, COMMON_MOP_SRC_LEN},
+    instruction::{COMMON_MOP_SRC_LEN, MOpTrait, PRegNum, UnitNum, UnitOutRegNum},
     register::PRegValue,
     unit::{UnitCancelInput, UnitOutput, UnitOutputWrite},
     util::tree_reduce::tree_reduce,

crates/cpu/tests/reg_alloc.rs

@@ -4,7 +4,7 @@
 use cpu::{
     config::{CpuConfig, UnitConfig},
     instruction::{AddSubMOp, LogicalMOp, MOp, MOpDestReg, MOpRegNum, OutputIntegerMode},
-    reg_alloc::{reg_alloc, FetchedDecodedMOp},
+    reg_alloc::{FetchedDecodedMOp, reg_alloc},
     register::{FlagsMode, PRegFlagsPowerISA},
     unit::{GlobalState, UnitKind},
 };
@@ -12,7 +12,7 @@ use fayalite::{
     assert_export_firrtl,
     firrtl::ExportOptions,
     prelude::*,
-    sim::{time::SimDuration, vcd::VcdWriterDecls, Simulation},
+    sim::{Simulation, time::SimDuration, vcd::VcdWriterDecls},
     util::RcWriter,
 };
 use std::num::NonZeroUsize;