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tests/units_formal: implement tests for rest of AddSub[I] instructions
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This commit is contained in:
Jacob Lifshay 2026-06-18 20:08:11 -07:00
parent b6bbc97990
commit fb0b07fbb2
Signed by: programmerjake
SSH key fingerprint: SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
9 changed files with 413919 additions and 267782 deletions
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384
crates/cpu/tests/expected/units_formal_power_isa_add_sim.vcd generated
View file

@ -1629,6 +1629,206 @@ $var string 1 k^+pu; \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_0_25 $end
$var string 1 #a]5!9 \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_1_28 $end
$var string 1 k^+pu< \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_0_26 $end
$var string 1 #a]5!: \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_1_29 $end
$var string 1 k^+pu= \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_0_27 $end
$var string 1 #a]5!; \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_1_30 $end
$var string 1 k^+pu> \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_0_28 $end
$var string 1 #a]5!< \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_1_31 $end
$var string 1 k^+pu? \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_0_29 $end
$var string 1 #a]5!= \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_1_32 $end
$var string 1 k^+pu@ \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_0_30 $end
$var string 1 #a]5!> \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_1_33 $end
$var string 1 k^+puA \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_0_31 $end
$var string 1 #a]5!? \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_1_34 $end
$var string 1 k^+puB \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_0_32 $end
$var string 1 #a]5!@ \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_1_35 $end
$var string 1 k^+puC \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_0_33 $end
$var string 1 #a]5!A \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_1_36 $end
$var string 1 k^+puD \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_0_34 $end
$var string 1 #a]5!B \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_1_37 $end
$var string 1 k^+puE \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_0_35 $end
$var string 1 #a]5!C \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_1_38 $end
$var string 1 k^+puF \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_0_36 $end
$var string 1 #a]5!D \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_1_39 $end
$var string 1 k^+puG \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_0_37 $end
$var string 1 #a]5!E \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_1_40 $end
$var string 1 k^+puH \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_0_38 $end
$var string 1 #a]5!F \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_1_41 $end
$var string 1 k^+puI \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_0_39 $end
$var string 1 #a]5!G \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_1_42 $end
$var string 1 k^+puJ \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_0_40 $end
$var string 1 #a]5!H \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_1_43 $end
$var string 1 k^+puK \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_0_41 $end
$var string 1 #a]5!I \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_1_44 $end
$var string 1 k^+puL \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_0_42 $end
$var string 1 #a]5!J \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_1_45 $end
$var string 1 k^+puM \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_0_43 $end
$var string 1 #a]5!K \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_1_46 $end
$var string 1 k^+puN \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_0_44 $end
$var string 1 #a]5!L \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_1_47 $end
$var string 1 k^+puO \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$upscope $end
$scope struct decoder_input $end
$var wire 32 x,~Jt \0 $end
@ -15426,6 +15626,26 @@ $var wire 1 K+"Lg \matched_case_subfeo. $end
$var wire 1 ;UoIk matched_case_addic $end
$var wire 1 g:;Z_ \matched_case_addic. $end
$var wire 1 pAfEx matched_case_subfic $end
$var wire 1 }{=[F matched_case_addme $end
$var wire 1 f~Et` matched_case_addmeo $end
$var wire 1 3ih6h \matched_case_addme. $end
$var wire 1 q&%T7 \matched_case_addmeo. $end
$var wire 1 $tMNT matched_case_addze $end
$var wire 1 F_46[ matched_case_addzeo $end
$var wire 1 ^ws"U \matched_case_addze. $end
$var wire 1 <$"E* \matched_case_addzeo. $end
$var wire 1 Pc.#E matched_case_subfme $end
$var wire 1 X2TW' matched_case_subfmeo $end
$var wire 1 0MXa1 \matched_case_subfme. $end
$var wire 1 bmkf> \matched_case_subfmeo. $end
$var wire 1 *Z14L matched_case_subfze $end
$var wire 1 )Ac#^ matched_case_subfzeo $end
$var wire 1 gnp$u \matched_case_subfze. $end
$var wire 1 %z.T? \matched_case_subfzeo. $end
$var wire 1 L0oiF matched_case_neg $end
$var wire 1 B`j2Z matched_case_nego $end
$var wire 1 l;NVP \matched_case_neg. $end
$var wire 1 6k7t) \matched_case_nego. $end
$var wire 64 <$d:7 input_r3 $end
$var wire 64 h<mmR input_r4 $end
$var wire 1 %^<Il input_ca $end
@ -15827,6 +16047,58 @@ $var string 1 4CV)U" addic_subfic_expected_out_2 $end
$var wire 16 .-Zk(# addic_subfic_imm_3 $end
$var wire 64 $a0'K# addic_subfic_in_3 $end
$var string 1 4CV)U# addic_subfic_expected_out_3 $end
$var wire 64 R7O^b addmze_subfmze_add_in0 $end
$var wire 64 s;K}r addmze_subfmze_add_in1 $end
$var string 1 j+akj addmze_subfmze_expected_out $end
$var wire 64 R7O^b" addmze_subfmze_add_in0_2 $end
$var wire 64 s;K}r" addmze_subfmze_add_in1_2 $end
$var string 1 j+akj" addmze_subfmze_expected_out_2 $end
$var wire 64 R7O^b# addmze_subfmze_add_in0_3 $end
$var wire 64 s;K}r# addmze_subfmze_add_in1_3 $end
$var string 1 j+akj# addmze_subfmze_expected_out_3 $end
$var wire 64 R7O^b$ addmze_subfmze_add_in0_4 $end
$var wire 64 s;K}r$ addmze_subfmze_add_in1_4 $end
$var string 1 j+akj$ addmze_subfmze_expected_out_4 $end
$var wire 64 R7O^b% addmze_subfmze_add_in0_5 $end
$var wire 64 s;K}r% addmze_subfmze_add_in1_5 $end
$var string 1 j+akj% addmze_subfmze_expected_out_5 $end
$var wire 64 R7O^b& addmze_subfmze_add_in0_6 $end
$var wire 64 s;K}r& addmze_subfmze_add_in1_6 $end
$var string 1 j+akj& addmze_subfmze_expected_out_6 $end
$var wire 64 R7O^b' addmze_subfmze_add_in0_7 $end
$var wire 64 s;K}r' addmze_subfmze_add_in1_7 $end
$var string 1 j+akj' addmze_subfmze_expected_out_7 $end
$var wire 64 R7O^b( addmze_subfmze_add_in0_8 $end
$var wire 64 s;K}r( addmze_subfmze_add_in1_8 $end
$var string 1 j+akj( addmze_subfmze_expected_out_8 $end
$var wire 64 R7O^b) addmze_subfmze_add_in0_9 $end
$var wire 64 s;K}r) addmze_subfmze_add_in1_9 $end
$var string 1 j+akj) addmze_subfmze_expected_out_9 $end
$var wire 64 R7O^b* addmze_subfmze_add_in0_10 $end
$var wire 64 s;K}r* addmze_subfmze_add_in1_10 $end
$var string 1 j+akj* addmze_subfmze_expected_out_10 $end
$var wire 64 R7O^b+ addmze_subfmze_add_in0_11 $end
$var wire 64 s;K}r+ addmze_subfmze_add_in1_11 $end
$var string 1 j+akj+ addmze_subfmze_expected_out_11 $end
$var wire 64 R7O^b, addmze_subfmze_add_in0_12 $end
$var wire 64 s;K}r, addmze_subfmze_add_in1_12 $end
$var string 1 j+akj, addmze_subfmze_expected_out_12 $end
$var wire 64 R7O^b- addmze_subfmze_add_in0_13 $end
$var wire 64 s;K}r- addmze_subfmze_add_in1_13 $end
$var string 1 j+akj- addmze_subfmze_expected_out_13 $end
$var wire 64 R7O^b. addmze_subfmze_add_in0_14 $end
$var wire 64 s;K}r. addmze_subfmze_add_in1_14 $end
$var string 1 j+akj. addmze_subfmze_expected_out_14 $end
$var wire 64 R7O^b/ addmze_subfmze_add_in0_15 $end
$var wire 64 s;K}r/ addmze_subfmze_add_in1_15 $end
$var string 1 j+akj/ addmze_subfmze_expected_out_15 $end
$var wire 64 R7O^b0 addmze_subfmze_add_in0_16 $end
$var wire 64 s;K}r0 addmze_subfmze_add_in1_16 $end
$var string 1 j+akj0 addmze_subfmze_expected_out_16 $end
$var string 1 8o:\@ neg_expected_out $end
$var string 1 8o:\@" neg_expected_out_2 $end
$var string 1 8o:\@# neg_expected_out_3 $end
$var string 1 8o:\@$ neg_expected_out_4 $end
$upscope $end
$enddefinitions $end
$dumpvars
@ -17062,6 +17334,46 @@ sHdlSome\x20(1) #a]5!7
sHdlNone\x20(0) k^+pu:
sHdlSome\x20(1) #a]5!8
sHdlSome\x20(1) k^+pu;
sHdlNone\x20(0) #a]5!9
sHdlNone\x20(0) k^+pu<
sHdlNone\x20(0) #a]5!:
sHdlSome\x20(1) k^+pu=
sHdlSome\x20(1) #a]5!;
sHdlNone\x20(0) k^+pu>
sHdlSome\x20(1) #a]5!<
sHdlSome\x20(1) k^+pu?
sHdlNone\x20(0) #a]5!=
sHdlNone\x20(0) k^+pu@
sHdlNone\x20(0) #a]5!>
sHdlSome\x20(1) k^+puA
sHdlSome\x20(1) #a]5!?
sHdlNone\x20(0) k^+puB
sHdlSome\x20(1) #a]5!@
sHdlSome\x20(1) k^+puC
sHdlNone\x20(0) #a]5!A
sHdlNone\x20(0) k^+puD
sHdlNone\x20(0) #a]5!B
sHdlSome\x20(1) k^+puE
sHdlSome\x20(1) #a]5!C
sHdlNone\x20(0) k^+puF
sHdlSome\x20(1) #a]5!D
sHdlSome\x20(1) k^+puG
sHdlNone\x20(0) #a]5!E
sHdlNone\x20(0) k^+puH
sHdlNone\x20(0) #a]5!F
sHdlSome\x20(1) k^+puI
sHdlSome\x20(1) #a]5!G
sHdlNone\x20(0) k^+puJ
sHdlSome\x20(1) #a]5!H
sHdlSome\x20(1) k^+puK
sHdlNone\x20(0) #a]5!I
sHdlNone\x20(0) k^+puL
sHdlNone\x20(0) #a]5!J
sHdlSome\x20(1) k^+puM
sHdlSome\x20(1) #a]5!K
sHdlNone\x20(0) k^+puN
sHdlSome\x20(1) #a]5!L
sHdlSome\x20(1) k^+puO
b0 x,~Jt
sHdlNone\x20(0) \L:8?
b0 sD<$[
@ -23489,6 +23801,26 @@ b1000000000100 @$@j=%
0;UoIk
0g:;Z_
0pAfEx
0}{=[F
0f~Et`
03ih6h
0q&%T7
0$tMNT
0F_46[
0^ws"U
0<$"E*
0Pc.#E
0X2TW'
00MXa1
0bmkf>
0*Z14L
0)Ac#^
0gnp$u
0%z.T?
0L0oiF
0B`j2Z
0l;NVP
06k7t)
b1001000110100 <$d:7
b1001000110100 @$@j=&
b1001000110100 h<mmR
@ -23861,6 +24193,58 @@ sPRegValue\x20{\x20int_fp:\x200x3448_u64,\x20flags:\x20Pwr\x20{\x20cr_gt:\x20tru
b10001000010100 .-Zk(#
b1001000110100 $a0'K#
sPRegValue\x20{\x20int_fp:\x200x3448_u64,\x20flags:\x20Pwr\x20{\x20cr_gt:\x20true,\x20..\x20}\x20} 4CV)U#
b1001000110100 R7O^b
b0 s;K}r
sPRegValue\x20{\x20int_fp:\x200x1234_u64,\x20flags:\x20Pwr\x20{\x20cr_gt:\x20true,\x20..\x20}\x20} j+akj
b1001000110100 R7O^b"
b0 s;K}r"
sPRegValue\x20{\x20int_fp:\x200x1234_u64,\x20flags:\x20Pwr\x20{\x20cr_gt:\x20true,\x20..\x20}\x20} j+akj"
b1001000110100 R7O^b#
b0 s;K}r#
sPRegValue\x20{\x20int_fp:\x200x1234_u64,\x20flags:\x20Pwr\x20{\x20cr_gt:\x20true,\x20..\x20}\x20} j+akj#
b1001000110100 R7O^b$
b0 s;K}r$
sPRegValue\x20{\x20int_fp:\x200x1234_u64,\x20flags:\x20Pwr\x20{\x20cr_gt:\x20true,\x20..\x20}\x20} j+akj$
b1001000110100 R7O^b%
b0 s;K}r%
sPRegValue\x20{\x20int_fp:\x200x1234_u64,\x20flags:\x20Pwr\x20{\x20cr_gt:\x20true,\x20..\x20}\x20} j+akj%
b1001000110100 R7O^b&
b0 s;K}r&
sPRegValue\x20{\x20int_fp:\x200x1234_u64,\x20flags:\x20Pwr\x20{\x20cr_gt:\x20true,\x20..\x20}\x20} j+akj&
b1001000110100 R7O^b'
b0 s;K}r'
sPRegValue\x20{\x20int_fp:\x200x1234_u64,\x20flags:\x20Pwr\x20{\x20cr_gt:\x20true,\x20..\x20}\x20} j+akj'
b1001000110100 R7O^b(
b0 s;K}r(
sPRegValue\x20{\x20int_fp:\x200x1234_u64,\x20flags:\x20Pwr\x20{\x20cr_gt:\x20true,\x20..\x20}\x20} j+akj(
b1001000110100 R7O^b)
b0 s;K}r)
sPRegValue\x20{\x20int_fp:\x200x1234_u64,\x20flags:\x20Pwr\x20{\x20cr_gt:\x20true,\x20..\x20}\x20} j+akj)
b1001000110100 R7O^b*
b0 s;K}r*
sPRegValue\x20{\x20int_fp:\x200x1234_u64,\x20flags:\x20Pwr\x20{\x20cr_gt:\x20true,\x20..\x20}\x20} j+akj*
b1001000110100 R7O^b+
b0 s;K}r+
sPRegValue\x20{\x20int_fp:\x200x1234_u64,\x20flags:\x20Pwr\x20{\x20cr_gt:\x20true,\x20..\x20}\x20} j+akj+
b1001000110100 R7O^b,
b0 s;K}r,
sPRegValue\x20{\x20int_fp:\x200x1234_u64,\x20flags:\x20Pwr\x20{\x20cr_gt:\x20true,\x20..\x20}\x20} j+akj,
b1001000110100 R7O^b-
b0 s;K}r-
sPRegValue\x20{\x20int_fp:\x200x1234_u64,\x20flags:\x20Pwr\x20{\x20cr_gt:\x20true,\x20..\x20}\x20} j+akj-
b1001000110100 R7O^b.
b0 s;K}r.
sPRegValue\x20{\x20int_fp:\x200x1234_u64,\x20flags:\x20Pwr\x20{\x20cr_gt:\x20true,\x20..\x20}\x20} j+akj.
b1001000110100 R7O^b/
b0 s;K}r/
sPRegValue\x20{\x20int_fp:\x200x1234_u64,\x20flags:\x20Pwr\x20{\x20cr_gt:\x20true,\x20..\x20}\x20} j+akj/
b1001000110100 R7O^b0
b0 s;K}r0
sPRegValue\x20{\x20int_fp:\x200x1234_u64,\x20flags:\x20Pwr\x20{\x20cr_gt:\x20true,\x20..\x20}\x20} j+akj0
sPRegValue\x20{\x20int_fp:\x200xFFFFFFFFFFFFEDCC_u64,\x20flags:\x20Pwr\x20{\x20cr_lt:\x20true,\x20..\x20}\x20} 8o:\@
sPRegValue\x20{\x20int_fp:\x200xFFFFFFFFFFFFEDCC_u64,\x20flags:\x20Pwr\x20{\x20cr_lt:\x20true,\x20..\x20}\x20} 8o:\@"
sPRegValue\x20{\x20int_fp:\x200xFFFFFFFFFFFFEDCC_u64,\x20flags:\x20Pwr\x20{\x20cr_lt:\x20true,\x20..\x20}\x20} 8o:\@#
sPRegValue\x20{\x20int_fp:\x200xFFFFFFFFFFFFEDCC_u64,\x20flags:\x20Pwr\x20{\x20cr_lt:\x20true,\x20..\x20}\x20} 8o:\@$
$end
#500000
1mAPf1

32237
crates/cpu/tests/expected/units_formal_power_isa_add_sub_sim_0.vcd generated
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crates/cpu/tests/expected/units_formal_power_isa_add_sub_sim_1.vcd generated
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crates/cpu/tests/expected/units_formal_power_isa_add_sub_sim_2.vcd generated
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crates/cpu/tests/expected/units_formal_power_isa_add_sub_sim_3.vcd generated
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crates/cpu/tests/expected/units_formal_power_isa_add_sub_sim_4.vcd generated
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crates/cpu/tests/expected/units_formal_power_isa_add_sub_sim_5.vcd generated
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crates/cpu/tests/expected/units_formal_power_isa_paddi_sim.vcd generated
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@ -1629,6 +1629,206 @@ $var string 1 k^+pu; \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_0_25 $end
$var string 1 #a]5!9 \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_1_28 $end
$var string 1 k^+pu< \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_0_26 $end
$var string 1 #a]5!: \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_1_29 $end
$var string 1 k^+pu= \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_0_27 $end
$var string 1 #a]5!; \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_1_30 $end
$var string 1 k^+pu> \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_0_28 $end
$var string 1 #a]5!< \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_1_31 $end
$var string 1 k^+pu? \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_0_29 $end
$var string 1 #a]5!= \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_1_32 $end
$var string 1 k^+pu@ \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_0_30 $end
$var string 1 #a]5!> \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_1_33 $end
$var string 1 k^+puA \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_0_31 $end
$var string 1 #a]5!? \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_1_34 $end
$var string 1 k^+puB \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_0_32 $end
$var string 1 #a]5!@ \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_1_35 $end
$var string 1 k^+puC \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_0_33 $end
$var string 1 #a]5!A \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_1_36 $end
$var string 1 k^+puD \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_0_34 $end
$var string 1 #a]5!B \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_1_37 $end
$var string 1 k^+puE \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_0_35 $end
$var string 1 #a]5!C \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_1_38 $end
$var string 1 k^+puF \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_0_36 $end
$var string 1 #a]5!D \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_1_39 $end
$var string 1 k^+puG \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_0_37 $end
$var string 1 #a]5!E \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_1_40 $end
$var string 1 k^+puH \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_0_38 $end
$var string 1 #a]5!F \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_1_41 $end
$var string 1 k^+puI \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_0_39 $end
$var string 1 #a]5!G \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_1_42 $end
$var string 1 k^+puJ \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_0_40 $end
$var string 1 #a]5!H \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_1_43 $end
$var string 1 k^+puK \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_0_41 $end
$var string 1 #a]5!I \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_1_44 $end
$var string 1 k^+puL \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_0_42 $end
$var string 1 #a]5!J \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_1_45 $end
$var string 1 k^+puM \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_0_43 $end
$var string 1 #a]5!K \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_1_46 $end
$var string 1 k^+puN \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_0_44 $end
$var string 1 #a]5!L \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct flag_reg_1_47 $end
$var string 1 k^+puO \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$upscope $end
$scope struct decoder_input $end
$var wire 32 x,~Jt \0 $end
@ -15426,6 +15626,26 @@ $var wire 1 K+"Lg \matched_case_subfeo. $end
$var wire 1 ;UoIk matched_case_addic $end
$var wire 1 g:;Z_ \matched_case_addic. $end
$var wire 1 pAfEx matched_case_subfic $end
$var wire 1 }{=[F matched_case_addme $end
$var wire 1 f~Et` matched_case_addmeo $end
$var wire 1 3ih6h \matched_case_addme. $end
$var wire 1 q&%T7 \matched_case_addmeo. $end
$var wire 1 $tMNT matched_case_addze $end
$var wire 1 F_46[ matched_case_addzeo $end
$var wire 1 ^ws"U \matched_case_addze. $end
$var wire 1 <$"E* \matched_case_addzeo. $end
$var wire 1 Pc.#E matched_case_subfme $end
$var wire 1 X2TW' matched_case_subfmeo $end
$var wire 1 0MXa1 \matched_case_subfme. $end
$var wire 1 bmkf> \matched_case_subfmeo. $end
$var wire 1 *Z14L matched_case_subfze $end
$var wire 1 )Ac#^ matched_case_subfzeo $end
$var wire 1 gnp$u \matched_case_subfze. $end
$var wire 1 %z.T? \matched_case_subfzeo. $end
$var wire 1 L0oiF matched_case_neg $end
$var wire 1 B`j2Z matched_case_nego $end
$var wire 1 l;NVP \matched_case_neg. $end
$var wire 1 6k7t) \matched_case_nego. $end
$var wire 64 <$d:7 input_r3 $end
$var wire 64 h<mmR input_r4 $end
$var wire 1 %^<Il input_ca $end
@ -15827,6 +16047,58 @@ $var string 1 4CV)U" addic_subfic_expected_out_2 $end
$var wire 16 .-Zk(# addic_subfic_imm_3 $end
$var wire 64 $a0'K# addic_subfic_in_3 $end
$var string 1 4CV)U# addic_subfic_expected_out_3 $end
$var wire 64 R7O^b addmze_subfmze_add_in0 $end
$var wire 64 s;K}r addmze_subfmze_add_in1 $end
$var string 1 j+akj addmze_subfmze_expected_out $end
$var wire 64 R7O^b" addmze_subfmze_add_in0_2 $end
$var wire 64 s;K}r" addmze_subfmze_add_in1_2 $end
$var string 1 j+akj" addmze_subfmze_expected_out_2 $end
$var wire 64 R7O^b# addmze_subfmze_add_in0_3 $end
$var wire 64 s;K}r# addmze_subfmze_add_in1_3 $end
$var string 1 j+akj# addmze_subfmze_expected_out_3 $end
$var wire 64 R7O^b$ addmze_subfmze_add_in0_4 $end
$var wire 64 s;K}r$ addmze_subfmze_add_in1_4 $end
$var string 1 j+akj$ addmze_subfmze_expected_out_4 $end
$var wire 64 R7O^b% addmze_subfmze_add_in0_5 $end
$var wire 64 s;K}r% addmze_subfmze_add_in1_5 $end
$var string 1 j+akj% addmze_subfmze_expected_out_5 $end
$var wire 64 R7O^b& addmze_subfmze_add_in0_6 $end
$var wire 64 s;K}r& addmze_subfmze_add_in1_6 $end
$var string 1 j+akj& addmze_subfmze_expected_out_6 $end
$var wire 64 R7O^b' addmze_subfmze_add_in0_7 $end
$var wire 64 s;K}r' addmze_subfmze_add_in1_7 $end
$var string 1 j+akj' addmze_subfmze_expected_out_7 $end
$var wire 64 R7O^b( addmze_subfmze_add_in0_8 $end
$var wire 64 s;K}r( addmze_subfmze_add_in1_8 $end
$var string 1 j+akj( addmze_subfmze_expected_out_8 $end
$var wire 64 R7O^b) addmze_subfmze_add_in0_9 $end
$var wire 64 s;K}r) addmze_subfmze_add_in1_9 $end
$var string 1 j+akj) addmze_subfmze_expected_out_9 $end
$var wire 64 R7O^b* addmze_subfmze_add_in0_10 $end
$var wire 64 s;K}r* addmze_subfmze_add_in1_10 $end
$var string 1 j+akj* addmze_subfmze_expected_out_10 $end
$var wire 64 R7O^b+ addmze_subfmze_add_in0_11 $end
$var wire 64 s;K}r+ addmze_subfmze_add_in1_11 $end
$var string 1 j+akj+ addmze_subfmze_expected_out_11 $end
$var wire 64 R7O^b, addmze_subfmze_add_in0_12 $end
$var wire 64 s;K}r, addmze_subfmze_add_in1_12 $end
$var string 1 j+akj, addmze_subfmze_expected_out_12 $end
$var wire 64 R7O^b- addmze_subfmze_add_in0_13 $end
$var wire 64 s;K}r- addmze_subfmze_add_in1_13 $end
$var string 1 j+akj- addmze_subfmze_expected_out_13 $end
$var wire 64 R7O^b. addmze_subfmze_add_in0_14 $end
$var wire 64 s;K}r. addmze_subfmze_add_in1_14 $end
$var string 1 j+akj. addmze_subfmze_expected_out_14 $end
$var wire 64 R7O^b/ addmze_subfmze_add_in0_15 $end
$var wire 64 s;K}r/ addmze_subfmze_add_in1_15 $end
$var string 1 j+akj/ addmze_subfmze_expected_out_15 $end
$var wire 64 R7O^b0 addmze_subfmze_add_in0_16 $end
$var wire 64 s;K}r0 addmze_subfmze_add_in1_16 $end
$var string 1 j+akj0 addmze_subfmze_expected_out_16 $end
$var string 1 8o:\@ neg_expected_out $end
$var string 1 8o:\@" neg_expected_out_2 $end
$var string 1 8o:\@# neg_expected_out_3 $end
$var string 1 8o:\@$ neg_expected_out_4 $end
$upscope $end
$enddefinitions $end
$dumpvars
@ -17062,6 +17334,46 @@ sHdlSome\x20(1) #a]5!7
sHdlNone\x20(0) k^+pu:
sHdlSome\x20(1) #a]5!8
sHdlSome\x20(1) k^+pu;
sHdlNone\x20(0) #a]5!9
sHdlNone\x20(0) k^+pu<
sHdlNone\x20(0) #a]5!:
sHdlSome\x20(1) k^+pu=
sHdlSome\x20(1) #a]5!;
sHdlNone\x20(0) k^+pu>
sHdlSome\x20(1) #a]5!<
sHdlSome\x20(1) k^+pu?
sHdlNone\x20(0) #a]5!=
sHdlNone\x20(0) k^+pu@
sHdlNone\x20(0) #a]5!>
sHdlSome\x20(1) k^+puA
sHdlSome\x20(1) #a]5!?
sHdlNone\x20(0) k^+puB
sHdlSome\x20(1) #a]5!@
sHdlSome\x20(1) k^+puC
sHdlNone\x20(0) #a]5!A
sHdlNone\x20(0) k^+puD
sHdlNone\x20(0) #a]5!B
sHdlSome\x20(1) k^+puE
sHdlSome\x20(1) #a]5!C
sHdlNone\x20(0) k^+puF
sHdlSome\x20(1) #a]5!D
sHdlSome\x20(1) k^+puG
sHdlNone\x20(0) #a]5!E
sHdlNone\x20(0) k^+puH
sHdlNone\x20(0) #a]5!F
sHdlSome\x20(1) k^+puI
sHdlSome\x20(1) #a]5!G
sHdlNone\x20(0) k^+puJ
sHdlSome\x20(1) #a]5!H
sHdlSome\x20(1) k^+puK
sHdlNone\x20(0) #a]5!I
sHdlNone\x20(0) k^+puL
sHdlNone\x20(0) #a]5!J
sHdlSome\x20(1) k^+puM
sHdlSome\x20(1) #a]5!K
sHdlNone\x20(0) k^+puN
sHdlSome\x20(1) #a]5!L
sHdlSome\x20(1) k^+puO
b0 x,~Jt
sHdlNone\x20(0) \L:8?
b0 sD<$[
@ -23489,6 +23801,26 @@ b1000000001000 @$@j=%
0;UoIk
0g:;Z_
0pAfEx
0}{=[F
0f~Et`
03ih6h
0q&%T7
0$tMNT
0F_46[
0^ws"U
0<$"E*
0Pc.#E
0X2TW'
00MXa1
0bmkf>
0*Z14L
0)Ac#^
0gnp$u
0%z.T?
0L0oiF
0B`j2Z
0l;NVP
06k7t)
b1001100100000111010011110010011000000000000000000000000000000010 <$d:7
b1001100100000111010011110010011000000000000000000000000000000010 @$@j=&
b110000000000000000001000010010000010111110111111111111011111101 h<mmR
@ -23861,6 +24193,58 @@ sPRegValue\x20{\x20int_fp:\x200x9FFFFBDBE8200103_u64,\x20flags:\x20Pwr\x20{\x20c
b0 .-Zk(#
b1001111111111111111110111101101111101000001000000000000100000010 $a0'K#
sPRegValue\x20{\x20int_fp:\x200x9FFFFBDBE8200103_u64,\x20flags:\x20Pwr\x20{\x20cr_lt:\x20true,\x20..\x20}\x20} 4CV)U#
b1001111111111111111110111101101111101000001000000000000100000010 R7O^b
b0 s;K}r
sPRegValue\x20{\x20int_fp:\x200x9FFFFBDBE8200102_u64,\x20flags:\x20Pwr\x20{\x20cr_lt:\x20true,\x20..\x20}\x20} j+akj
b1001111111111111111110111101101111101000001000000000000100000010 R7O^b"
b0 s;K}r"
sPRegValue\x20{\x20int_fp:\x200x9FFFFBDBE8200102_u64,\x20flags:\x20Pwr\x20{\x20cr_lt:\x20true,\x20..\x20}\x20} j+akj"
b1001111111111111111110111101101111101000001000000000000100000010 R7O^b#
b0 s;K}r#
sPRegValue\x20{\x20int_fp:\x200x9FFFFBDBE8200102_u64,\x20flags:\x20Pwr\x20{\x20cr_lt:\x20true,\x20..\x20}\x20} j+akj#
b1001111111111111111110111101101111101000001000000000000100000010 R7O^b$
b0 s;K}r$
sPRegValue\x20{\x20int_fp:\x200x9FFFFBDBE8200102_u64,\x20flags:\x20Pwr\x20{\x20cr_lt:\x20true,\x20..\x20}\x20} j+akj$
b1001111111111111111110111101101111101000001000000000000100000010 R7O^b%
b0 s;K}r%
sPRegValue\x20{\x20int_fp:\x200x9FFFFBDBE8200102_u64,\x20flags:\x20Pwr\x20{\x20cr_lt:\x20true,\x20..\x20}\x20} j+akj%
b1001111111111111111110111101101111101000001000000000000100000010 R7O^b&
b0 s;K}r&
sPRegValue\x20{\x20int_fp:\x200x9FFFFBDBE8200102_u64,\x20flags:\x20Pwr\x20{\x20cr_lt:\x20true,\x20..\x20}\x20} j+akj&
b1001111111111111111110111101101111101000001000000000000100000010 R7O^b'
b0 s;K}r'
sPRegValue\x20{\x20int_fp:\x200x9FFFFBDBE8200102_u64,\x20flags:\x20Pwr\x20{\x20cr_lt:\x20true,\x20..\x20}\x20} j+akj'
b1001111111111111111110111101101111101000001000000000000100000010 R7O^b(
b0 s;K}r(
sPRegValue\x20{\x20int_fp:\x200x9FFFFBDBE8200102_u64,\x20flags:\x20Pwr\x20{\x20cr_lt:\x20true,\x20..\x20}\x20} j+akj(
b1001111111111111111110111101101111101000001000000000000100000010 R7O^b)
b0 s;K}r)
sPRegValue\x20{\x20int_fp:\x200x9FFFFBDBE8200102_u64,\x20flags:\x20Pwr\x20{\x20cr_lt:\x20true,\x20..\x20}\x20} j+akj)
b1001111111111111111110111101101111101000001000000000000100000010 R7O^b*
b0 s;K}r*
sPRegValue\x20{\x20int_fp:\x200x9FFFFBDBE8200102_u64,\x20flags:\x20Pwr\x20{\x20cr_lt:\x20true,\x20..\x20}\x20} j+akj*
b1001111111111111111110111101101111101000001000000000000100000010 R7O^b+
b0 s;K}r+
sPRegValue\x20{\x20int_fp:\x200x9FFFFBDBE8200102_u64,\x20flags:\x20Pwr\x20{\x20cr_lt:\x20true,\x20..\x20}\x20} j+akj+
b1001111111111111111110111101101111101000001000000000000100000010 R7O^b,
b0 s;K}r,
sPRegValue\x20{\x20int_fp:\x200x9FFFFBDBE8200102_u64,\x20flags:\x20Pwr\x20{\x20cr_lt:\x20true,\x20..\x20}\x20} j+akj,
b1001111111111111111110111101101111101000001000000000000100000010 R7O^b-
b0 s;K}r-
sPRegValue\x20{\x20int_fp:\x200x9FFFFBDBE8200102_u64,\x20flags:\x20Pwr\x20{\x20cr_lt:\x20true,\x20..\x20}\x20} j+akj-
b1001111111111111111110111101101111101000001000000000000100000010 R7O^b.
b0 s;K}r.
sPRegValue\x20{\x20int_fp:\x200x9FFFFBDBE8200102_u64,\x20flags:\x20Pwr\x20{\x20cr_lt:\x20true,\x20..\x20}\x20} j+akj.
b1001111111111111111110111101101111101000001000000000000100000010 R7O^b/
b0 s;K}r/
sPRegValue\x20{\x20int_fp:\x200x9FFFFBDBE8200102_u64,\x20flags:\x20Pwr\x20{\x20cr_lt:\x20true,\x20..\x20}\x20} j+akj/
b1001111111111111111110111101101111101000001000000000000100000010 R7O^b0
b0 s;K}r0
sPRegValue\x20{\x20int_fp:\x200x9FFFFBDBE8200102_u64,\x20flags:\x20Pwr\x20{\x20cr_lt:\x20true,\x20..\x20}\x20} j+akj0
sPRegValue\x20{\x20int_fp:\x200x9FFFFBDBE8200103_u64,\x20flags:\x20Pwr\x20{\x20cr_lt:\x20true,\x20..\x20}\x20} 8o:\@
sPRegValue\x20{\x20int_fp:\x200x9FFFFBDBE8200103_u64,\x20flags:\x20Pwr\x20{\x20cr_lt:\x20true,\x20..\x20}\x20} 8o:\@"
sPRegValue\x20{\x20int_fp:\x200x9FFFFBDBE8200103_u64,\x20flags:\x20Pwr\x20{\x20cr_lt:\x20true,\x20..\x20}\x20} 8o:\@#
sPRegValue\x20{\x20int_fp:\x200x9FFFFBDBE8200103_u64,\x20flags:\x20Pwr\x20{\x20cr_lt:\x20true,\x20..\x20}\x20} 8o:\@$
$end
#500000
1mAPf1

204
crates/cpu/tests/units_formal.rs
View file

@ -570,6 +570,8 @@ fn case_check_add_addc_adde_subf_subfc_subfe(cases: &mut Cases) {
connect(cr_eq, sum_as_s64.cmp_eq(0i64));
connect(so, xer_ov); // TODO: also propagate from input SO
hdl_assert(clk, add_sub_expected_out.cmp_eq(r3_out), "");
#[hdl]
if has_ca_out {
hdl_assert(clk, add_sub_expected_out.cmp_eq(ca_out), "");
@ -593,6 +595,115 @@ fn case_check_add_addc_adde_subf_subfc_subfe(cases: &mut Cases) {
}
}
#[hdl]
fn case_check_addme_addze_subfme_subfze(cases: &mut Cases) {
let r4 = MOpRegNum::power_isa_gpr_reg_num(4);
let ca = MOpRegNum::POWER_ISA_XER_CA_CA32_REG_NUM;
cases.add("addme 3, 4", 0x7C64_01D4, 0, [r4, ca], check);
cases.add("addmeo 3, 4", 0x7C64_05D4, 0, [r4, ca], check);
cases.add("addme. 3, 4", 0x7C64_01D5, 0, [r4, ca], check);
cases.add("addmeo. 3, 4", 0x7C64_05D5, 0, [r4, ca], check);
cases.add("addze 3, 4", 0x7C64_0194, 0, [r4, ca], check);
cases.add("addzeo 3, 4", 0x7C64_0594, 0, [r4, ca], check);
cases.add("addze. 3, 4", 0x7C64_0195, 0, [r4, ca], check);
cases.add("addzeo. 3, 4", 0x7C64_0595, 0, [r4, ca], check);
cases.add("subfme 3, 4", 0x7C64_01D0, 0, [r4, ca], check);
cases.add("subfmeo 3, 4", 0x7C64_05D0, 0, [r4, ca], check);
cases.add("subfme. 3, 4", 0x7C64_01D1, 0, [r4, ca], check);
cases.add("subfmeo. 3, 4", 0x7C64_05D1, 0, [r4, ca], check);
cases.add("subfze 3, 4", 0x7C64_0190, 0, [r4, ca], check);
cases.add("subfzeo 3, 4", 0x7C64_0590, 0, [r4, ca], check);
cases.add("subfze. 3, 4", 0x7C64_0191, 0, [r4, ca], check);
cases.add("subfzeo. 3, 4", 0x7C64_0591, 0, [r4, ca], check);
#[hdl]
fn check(clk: Expr<Clock>, io: &mut CaseIO) {
let rhs_is_ones = (io.suffix & 0x40u32).cmp_ne(0u32);
let oe = (io.suffix & 0x400u32).cmp_ne(0u32);
let is_sub = (io.suffix & 0x4u32).cmp_eq(0u32);
let rc = (io.suffix & 1u32).cmp_ne(0u32);
let r4_in = io.in_reg(MOpRegNum::power_isa_gpr_reg_num(4)).int_fp;
let ca_in = io.in_reg(MOpRegNum::POWER_ISA_XER_CA_CA32_REG_NUM);
let ov_in = io.in_reg(MOpRegNum::POWER_ISA_XER_SO_OV_OV32_REG_NUM);
let cr0_in = io.in_reg(MOpRegNum::POWER_ISA_CR_0_REG_NUM);
let r3_out = io.out_reg(MOpRegNum::power_isa_gpr_reg_num(3));
let ca_out = io.out_reg(MOpRegNum::POWER_ISA_XER_CA_CA32_REG_NUM);
let ov_out = io.out_reg(MOpRegNum::POWER_ISA_XER_SO_OV_OV32_REG_NUM);
let cr0_out = io.out_reg(MOpRegNum::POWER_ISA_CR_0_REG_NUM);
#[hdl]
let addmze_subfmze_add_in0 = wire();
let in0 = addmze_subfmze_add_in0;
connect(in0, r4_in);
#[hdl]
if is_sub {
connect(in0, !r4_in);
}
#[hdl]
let addmze_subfmze_add_in1 = wire();
let in1 = addmze_subfmze_add_in1;
connect(
in1,
rhs_is_ones.cast_to(SInt[1]).cast_to_static::<UInt<64>>(),
);
let add_sub_ca_in = PRegFlags::view::<PRegFlagsPowerISA>(ca_in.flags)
.xer_ca
.cast_to_static::<UInt<1>>();
#[hdl]
let addmze_subfmze_expected_out = wire(r3_out.ty());
let PRegFlagsPowerISAView {
unused: _,
xer_ca,
xer_ca32,
xer_ov,
xer_ov32,
cr_lt,
cr_gt,
cr_eq,
so,
..
} = PRegFlags::view::<PRegFlagsPowerISA>(addmze_subfmze_expected_out.flags);
let in0_s = in0.cast_to_static::<SInt<64>>();
let in1_s = in1.cast_to_static::<SInt<64>>();
let u64_sum = in0 + in1 + add_sub_ca_in;
let s64_sum = in0_s + in1_s + add_sub_ca_in.cast_to(SInt[2]);
let u32_sum = in0.cast_to(UInt[32]) + in1.cast_to(UInt[32]) + add_sub_ca_in;
let s32_sum =
in0.cast_to(SInt[32]) + in1.cast_to(SInt[32]) + add_sub_ca_in.cast_to(SInt[2]);
let sum_as_s64 = u64_sum.cast_to(SInt[64]);
connect(
addmze_subfmze_expected_out.int_fp,
u64_sum.cast_to_static::<UInt<64>>(),
);
connect(xer_ca, u64_sum[64]);
connect(xer_ca32, u32_sum[32]);
connect(xer_ov, s64_sum.cmp_lt(i64::MIN) | s64_sum.cmp_gt(i64::MAX));
connect(
xer_ov32,
s32_sum.cmp_lt(i32::MIN) | s32_sum.cmp_gt(i32::MAX),
);
connect(cr_gt, sum_as_s64.cmp_gt(0i64));
connect(cr_lt, sum_as_s64.cmp_lt(0i64));
connect(cr_eq, sum_as_s64.cmp_eq(0i64));
connect(so, xer_ov); // TODO: also propagate from input SO
hdl_assert(clk, addmze_subfmze_expected_out.cmp_eq(r3_out), "");
hdl_assert(clk, addmze_subfmze_expected_out.cmp_eq(ca_out), "");
#[hdl]
if oe {
hdl_assert(clk, addmze_subfmze_expected_out.cmp_eq(ov_out), "");
} else {
hdl_assert(clk, ov_in.cmp_eq(ov_out), "");
}
#[hdl]
if rc {
hdl_assert(clk, addmze_subfmze_expected_out.cmp_eq(cr0_out), "");
} else {
hdl_assert(clk, cr0_in.cmp_eq(cr0_out), "");
}
}
}
#[hdl]
fn case_check_addic_subfic(cases: &mut Cases) {
let r4 = MOpRegNum::power_isa_gpr_reg_num(4);
@ -660,6 +771,7 @@ fn case_check_addic_subfic(cases: &mut Cases) {
connect(cr_eq, sum_as_s64.cmp_eq(0i64));
connect(so, xer_ov); // TODO: also propagate from input SO
hdl_assert(clk, addic_subfic_expected_out.cmp_eq(r3_out), "");
hdl_assert(clk, addic_subfic_expected_out.cmp_eq(ca_out), "");
#[hdl]
@ -671,6 +783,74 @@ fn case_check_addic_subfic(cases: &mut Cases) {
}
}
#[hdl]
fn case_check_neg(cases: &mut Cases) {
let r4 = MOpRegNum::power_isa_gpr_reg_num(4);
cases.add("neg 3, 4", 0x7C64_00D0, 0, [r4], check);
cases.add("nego 3, 4", 0x7C64_04D0, 0, [r4], check);
cases.add("neg. 3, 4", 0x7C64_00D1, 0, [r4], check);
cases.add("nego. 3, 4", 0x7C64_04D1, 0, [r4], check);
#[hdl]
fn check(clk: Expr<Clock>, io: &mut CaseIO) {
let oe = (io.suffix & 0x400u32).cmp_ne(0u32);
let rc = (io.suffix & 1u32).cmp_ne(0u32);
let r4_in = io.in_reg(MOpRegNum::power_isa_gpr_reg_num(4)).int_fp;
let ov_in = io.in_reg(MOpRegNum::POWER_ISA_XER_SO_OV_OV32_REG_NUM);
let cr0_in = io.in_reg(MOpRegNum::POWER_ISA_CR_0_REG_NUM);
let r3_out = io.out_reg(MOpRegNum::power_isa_gpr_reg_num(3));
let ov_out = io.out_reg(MOpRegNum::POWER_ISA_XER_SO_OV_OV32_REG_NUM);
let cr0_out = io.out_reg(MOpRegNum::POWER_ISA_CR_0_REG_NUM);
#[hdl]
let neg_expected_out = wire(r3_out.ty());
let PRegFlagsPowerISAView {
unused: _,
xer_ca,
xer_ca32,
xer_ov,
xer_ov32,
cr_lt,
cr_gt,
cr_eq,
so,
..
} = PRegFlags::view::<PRegFlagsPowerISA>(neg_expected_out.flags);
let out_s = neg_expected_out.int_fp.cast_to_static::<SInt<64>>();
connect(
neg_expected_out.int_fp,
(-r4_in.cast_to_static::<SInt<64>>()).cast_to_static::<UInt<64>>(),
);
connect(xer_ca, r4_in.cmp_eq(0u64));
connect(xer_ca32, r4_in.cast_to_static::<UInt<32>>().cmp_eq(0u32));
connect(xer_ov, r4_in.cmp_eq(i64::MIN.cast_unsigned()));
connect(
xer_ov32,
r4_in
.cast_to_static::<UInt<32>>()
.cmp_eq(i32::MIN.cast_unsigned()),
);
connect(cr_gt, out_s.cmp_gt(0i64));
connect(cr_lt, out_s.cmp_lt(0i64));
connect(cr_eq, out_s.cmp_eq(0i64));
connect(so, xer_ov); // TODO: also propagate from input SO
hdl_assert(clk, neg_expected_out.cmp_eq(r3_out), "");
#[hdl]
if oe {
hdl_assert(clk, neg_expected_out.cmp_eq(ov_out), "");
} else {
hdl_assert(clk, ov_in.cmp_eq(ov_out), "");
}
#[hdl]
if rc {
hdl_assert(clk, neg_expected_out.cmp_eq(cr0_out), "");
} else {
hdl_assert(clk, cr0_in.cmp_eq(cr0_out), "");
}
}
}
fn cases_add_sub() -> Cases {
let mut cases = Cases::default();
case_check_addi(&mut cases);
@ -679,27 +859,9 @@ fn cases_add_sub() -> Cases {
case_check_addpcis(&mut cases);
case_check_add_addc_adde_subf_subfc_subfe(&mut cases);
case_check_addic_subfic(&mut cases);
// TODO: "addme"
// TODO: "addme."
// TODO: "addmeo"
// TODO: "addmeo."
// TODO: "addze"
// TODO: "addze."
// TODO: "addzeo"
// TODO: "addzeo."
// TODO: "subfme"
// TODO: "subfme."
// TODO: "subfmeo"
// TODO: "subfmeo."
// TODO: "subfze"
// TODO: "subfze."
// TODO: "subfzeo"
// TODO: "subfzeo."
// TODO: "addex"
// TODO: "neg"
// TODO: "neg."
// TODO: "nego"
// TODO: "nego."
case_check_addme_addze_subfme_subfze(&mut cases);
// TODO: addex -- not implemented in decoder::simple_power_isa
case_check_neg(&mut cases);
cases
}