add main_memory_and_io::simple_uart::{transmitter, uart_clock_gen} and tests

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Jacob Lifshay 2026-02-25 00:08:42 -08:00

parent 4ffaba8840

commit e31375b9ce

Signed by: programmerjake

SSH key fingerprint: SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ

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crates/cpu/tests/expected/transmitter_and_uart_clock_gen.vcd generated Normal file

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