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41
crates/cpu/src/rename_execute_retire/unit.mermaid
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crates/cpu/src/rename_execute_retire/unit.mermaid
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%% SPDX-License-Identifier: LGPL-3.0-or-later
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%% See Notices.txt for copyright information
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stateDiagram-v2
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direction LR
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state "Inputs not ready<br/>Speculative<br/>Can cause cancel" as inr_s_c
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state "Inputs not ready<br/>Speculative" as inr_s
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state "Inputs ready<br/>Speculative<br/>Can cause cancel" as ir_s_c
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state "Inputs ready<br/>Speculative" as ir_s
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state "Inputs ready<br/>Can cause cancel" as ir_c
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state "Inputs ready" as ir
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state "Output ready<br/>Speculative<br/>Can cause cancel" as or_s_c
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state "Output ready<br/>Can cause cancel" as or_c
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state "Output ready<br/>Speculative" as or_s
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state "Output ready" as or
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[*] --> inr_s_c: Enqueue
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inr_s_c --> inr_s: Can't cause cancel
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ir_s_c --> ir_s: Can't cause cancel
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ir_c --> ir: Can't cause cancel
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or_s_c --> or_s: Can't cause cancel
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or_c --> or: Can't cause cancel
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ir_s_c --> ir_c: No longer speculative
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ir_s --> ir: No longer speculative
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or_s_c --> or_c: No longer speculative
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or_s --> or: No longer speculative
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inr_s_c --> ir_s_c: Inputs ready
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inr_s --> ir_s: Inputs ready
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ir_s_c --> or_s_c: Output Ready
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ir_c --> or_c: Output Ready
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ir_s --> or_s: Output Ready
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ir --> or: Output Ready
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or_s_c --> [*]: Finish
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or_c --> [*]: Finish
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or_s --> [*]: Finish
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or --> [*]: Finish
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700420
crates/cpu/tests/expected/rename_execute_retire_fibonacci.vcd
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700420
crates/cpu/tests/expected/rename_execute_retire_fibonacci.vcd
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BIN
profile.json.gz
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BIN
profile.json.gz
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