rename_execute_retire: add a head -n1 test
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/ test (pull_request) Successful in 9m24s
All checks were successful
/ test (pull_request) Successful in 9m24s
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SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
8 changed files with 100223 additions and 3334 deletions
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@ -10,8 +10,9 @@ use cpu::{
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AddSubMOp, AluBranchMOp, AluCommonMOp, BranchMOp, COMMON_MOP_SRC_LEN, CommonMOp,
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CompareMOp, CompareMode, ConditionMode, L2RegNum, L2RegisterFileMOp, LoadMOp,
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LoadStoreCommonMOp, LoadStoreConversion, LoadStoreMOp, LoadStoreWidth, MOp, MOpDestReg,
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MOpRegNum, MOpTrait, MoveRegMOp, OutputIntegerMode, PRegNum, ReadL2RegMOp, StoreMOp,
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UnitNum, WriteL2RegMOp,
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MOpRegNum, MOpTrait, MoveRegMOp, OutputIntegerMode, PRegNum, ReadL2RegMOp,
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ShiftAmountOverflowBehavior, ShiftRotateDestLogicOp, ShiftRotateMOp, ShiftRotateMOpImm,
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ShiftRotateMode, StoreMOp, UnitNum, WriteL2RegMOp,
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},
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next_pc::CallStackOp,
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register::{PRegFlags, PRegFlagsPowerISA, PRegValue},
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@ -331,6 +332,43 @@ impl InsnsBuilder {
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},
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));
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}
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fn power_isa_bdnz(&mut self, target: InsnsBuilderLabel) {
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let pc = self.pc;
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self.add_insn(Insn::new_lazy(
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4,
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format!("bdnz {}", self.labels[target.0].name),
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move |labels| {
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[
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AddSubMOp::add_sub_i::<MOp>(
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MOpDestReg::new([MOpRegNum::power_isa_ctr_reg()], []),
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[MOpRegNum::power_isa_ctr_reg(), MOpRegNum::const_zero()],
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(-1).cast_to_static::<SInt<_>>(),
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OutputIntegerMode.Full64(),
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false,
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false,
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false,
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false,
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),
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BranchMOp::branch_ctr(
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MOpDestReg::new_sim(&[], &[]),
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[
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MOpRegNum::const_zero(),
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MOpRegNum::const_zero(),
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MOpRegNum::power_isa_ctr_reg(),
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],
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labels[target.0]
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.pc()
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.wrapping_sub(pc)
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.cast_to_static::<SInt<_>>(),
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true,
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true,
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false,
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false,
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),
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]
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},
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));
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}
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fn power_isa_bl(&mut self, target: InsnsBuilderLabel) {
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let pc = self.pc;
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self.add_insn(Insn::new_lazy(
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@ -402,6 +440,45 @@ impl InsnsBuilder {
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)],
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));
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}
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fn power_isa_cmplwi(&mut self, dest: usize, src: usize, imm: u16) {
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self.add_insn(Insn::new(
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4,
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format!("cmplwi {dest}, {src}, {imm:#x}"),
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[CompareMOp::compare_i(
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MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(dest)], &[]),
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[MOpRegNum::power_isa_gpr_reg_imm(src)],
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imm.cast_to_static::<SInt<_>>(),
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CompareMode.U32(),
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)],
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));
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}
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fn power_isa_lbzu(&mut self, dest: usize, src: usize, disp: i16) {
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self.add_insn(Insn::new(
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4,
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format!("lbzu {dest}, {}({src})", signed_hex(disp)),
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[
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AddSubMOp::add_sub_i(
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MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(src)], &[]),
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[
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MOpRegNum::power_isa_gpr_reg_imm(src),
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MOpRegNum::const_zero(),
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],
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disp.cast_to_static::<SInt<_>>(),
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OutputIntegerMode.Full64(),
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false,
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false,
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false,
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false,
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),
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LoadMOp::load(
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MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(dest)], &[]),
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[MOpRegNum::power_isa_gpr_reg_imm(src)],
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LoadStoreWidth.Width8Bit(),
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LoadStoreConversion.ZeroExt(),
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),
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],
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));
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}
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fn power_isa_ld(&mut self, dest: usize, src: usize, disp: i16) {
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self.add_insn(Insn::new(
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4,
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@ -429,6 +506,36 @@ impl InsnsBuilder {
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],
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));
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}
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fn power_isa_stb(&mut self, value_src: usize, addr_src: usize, disp: i16) {
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self.add_insn(Insn::new(
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4,
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format!("stb {value_src}, {}({addr_src})", signed_hex(disp)),
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[
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AddSubMOp::add_sub_i(
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MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]),
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[
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MOpRegNum::power_isa_gpr_or_zero_reg_imm(addr_src),
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MOpRegNum::const_zero(),
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],
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disp.cast_to_static::<SInt<_>>(),
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OutputIntegerMode.Full64(),
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false,
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false,
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false,
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false,
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),
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StoreMOp::store(
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MOpDestReg::new_sim(&[], &[]),
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[
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MOpRegNum::power_isa_temp_reg(),
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MOpRegNum::power_isa_gpr_reg_imm(value_src),
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],
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LoadStoreWidth.Width8Bit(),
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LoadStoreConversion.ZeroExt(),
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),
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],
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));
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}
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fn power_isa_std(&mut self, value_src: usize, addr_src: usize, disp: i16) {
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self.add_insn(Insn::new(
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4,
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@ -459,6 +566,72 @@ impl InsnsBuilder {
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],
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));
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}
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fn power_isa_stdu(&mut self, value_src: usize, addr_src: usize, disp: i16) {
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if value_src == addr_src {
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self.add_insn(Insn::new(
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4,
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format!("stdu {value_src}, {}({addr_src})", signed_hex(disp)),
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[
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AddSubMOp::add_sub_i(
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MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]),
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[
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MOpRegNum::power_isa_gpr_reg_imm(addr_src),
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MOpRegNum::const_zero(),
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],
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disp.cast_to_static::<SInt<_>>(),
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OutputIntegerMode.Full64(),
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false,
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false,
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false,
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false,
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),
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StoreMOp::store(
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MOpDestReg::new_sim(&[], &[]),
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[
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MOpRegNum::power_isa_temp_reg(),
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MOpRegNum::power_isa_gpr_reg_imm(value_src),
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],
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LoadStoreWidth.Width64Bit(),
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LoadStoreConversion.ZeroExt(),
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),
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MoveRegMOp::move_reg(
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MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(addr_src)], &[]),
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[MOpRegNum::power_isa_temp_reg()],
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0.cast_to_static::<SInt<_>>(),
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),
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],
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));
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} else {
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self.add_insn(Insn::new(
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4,
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format!("stdu {value_src}, {}({addr_src})", signed_hex(disp)),
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[
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AddSubMOp::add_sub_i(
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MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(addr_src)], &[]),
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[
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MOpRegNum::power_isa_gpr_reg_imm(addr_src),
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MOpRegNum::const_zero(),
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],
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disp.cast_to_static::<SInt<_>>(),
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OutputIntegerMode.Full64(),
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false,
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false,
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false,
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false,
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),
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StoreMOp::store(
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MOpDestReg::new_sim(&[], &[]),
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[
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MOpRegNum::power_isa_gpr_reg_imm(addr_src),
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MOpRegNum::power_isa_gpr_reg_imm(value_src),
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],
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LoadStoreWidth.Width64Bit(),
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LoadStoreConversion.ZeroExt(),
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),
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],
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));
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}
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}
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fn power_isa_mflr(&mut self, dest: usize) {
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self.add_insn(Insn::new(
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4,
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@ -481,6 +654,28 @@ impl InsnsBuilder {
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)],
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));
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}
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fn power_isa_mfctr(&mut self, dest: usize) {
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self.add_insn(Insn::new(
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4,
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format!("mfctr {dest}"),
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[MoveRegMOp::move_reg(
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MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(dest)], &[]),
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[MOpRegNum::power_isa_ctr_reg()],
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0i8.cast_to_static::<SInt<_>>(),
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)],
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));
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}
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fn power_isa_mtctr(&mut self, src: usize) {
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self.add_insn(Insn::new(
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4,
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format!("mtctr {src}"),
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[MoveRegMOp::move_reg(
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MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_CTR_REG_NUM], &[]),
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[MOpRegNum::power_isa_gpr_reg_imm(src)],
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0i8.cast_to_static::<SInt<_>>(),
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)],
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));
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}
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fn power_isa_mr(&mut self, dest: usize, src: usize) {
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self.add_insn(Insn::new(
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4,
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@ -492,6 +687,64 @@ impl InsnsBuilder {
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)],
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));
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}
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#[hdl]
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fn power_isa_rlwinm(
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&mut self,
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dest: usize,
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src: usize,
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shift: u32,
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msb0_mask_begin: u32,
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msb0_mask_end: u32,
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) {
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assert!(shift < 32);
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assert!(msb0_mask_begin < 32);
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assert!(msb0_mask_end < 32);
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let insn = format!("rlwinm {dest}, {src}, {shift}, {msb0_mask_begin}, {msb0_mask_end}");
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let msb0_mask_begin = msb0_mask_begin + 32;
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let msb0_mask_end = msb0_mask_end + 32;
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// gives the correct value modulo 2^6 even when `msb0_mask_begin > msb0_mask_end`
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let rotated_output_len = msb0_mask_end.wrapping_sub(msb0_mask_begin).wrapping_add(1) % 64;
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// account for lsb0 vs. msb0
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let rotated_output_start = !msb0_mask_end % 64;
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self.add_insn(Insn::new(
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4,
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insn,
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[ShiftRotateMOp::shift_rotate(
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MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(dest)], &[]),
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[
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MOpRegNum::power_isa_gpr_reg_imm(src),
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MOpRegNum::power_isa_gpr_reg_imm(src),
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MOpRegNum::const_zero(),
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],
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#[hdl]
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ShiftRotateMOpImm {
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shift_rotate_amount: HdlSome(shift.cast_to_static::<UInt<_>>()),
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shift_rotate_right: false,
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shift_amount_overflow_behavior: ShiftAmountOverflowBehavior.WrapToWidth(),
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dest_logic_op: if rotated_output_len == 0 {
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// rotated_output_len wrapped around to 64
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HdlNone()
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} else {
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HdlSome(
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#[hdl]
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ShiftRotateDestLogicOp {
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rotated_output_start: rotated_output_start
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.cast_to_static::<UInt<_>>(),
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rotated_output_len: rotated_output_len.cast_to_static::<UInt<_>>(),
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fallback_is_src2: false,
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},
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)
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},
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},
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OutputIntegerMode.Full64(),
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ShiftRotateMode.FunnelShift2x32Bit(),
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)],
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));
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}
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fn power_isa_clrlwi(&mut self, dest: usize, src: usize, width: u32) {
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assert!(width < 32);
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self.power_isa_rlwinm(dest, src, 0, width, 31);
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}
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}
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trait MakeInsns {
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@ -499,59 +752,6 @@ trait MakeInsns {
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fn make_load_store_execution_state() -> MockMemory;
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}
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struct FibonacciInsns;
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impl MakeInsns for FibonacciInsns {
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fn make_insns() -> Insns {
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let mut b = InsnsBuilder::new();
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let fib = b.new_label("fib");
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let fib_small = b.new_label("fib_small");
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b.power_isa_ld(3, 0, MockMemory::IO_ADDR as i16); // load input
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b.power_isa_addi(1, 0, 0x4000); // setup stack pointer
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b.power_isa_bl(fib);
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b.power_isa_std(3, 0, MockMemory::IO_ADDR as i16); // store output
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let done = b.new_defined_label("done");
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b.power_isa_b(done);
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b.set_pc(0x1000);
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b.define_label(fib);
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b.power_isa_cmpldi(0, 3, 1);
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b.power_isa_ble(fib_small); // if input <= 1 goto fib_small
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// push stack frame
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b.power_isa_mflr(0);
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b.power_isa_addi(1, 1, -16);
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b.power_isa_std(0, 1, 0);
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b.power_isa_std(30, 1, 8);
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b.power_isa_addi(30, 3, -2);
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b.power_isa_addi(3, 3, -1);
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b.power_isa_bl(fib); // fib(input - 1)
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b.power_isa_mr(2, 3);
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b.power_isa_mr(3, 30);
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b.power_isa_mr(30, 2);
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b.power_isa_bl(fib); // fib(input - 2)
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b.power_isa_add(3, 3, 30); // set output to fib(input - 1) + fib(input - 2)
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// pop stack frame and return
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b.power_isa_ld(0, 1, 0);
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b.power_isa_ld(30, 1, 8);
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b.power_isa_addi(1, 1, 16);
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b.power_isa_mtlr(0);
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b.power_isa_blr();
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b.define_label(fib_small);
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b.power_isa_addi(3, 0, 1); // set output to 1
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b.power_isa_blr(); // return
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b.build()
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}
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fn make_load_store_execution_state() -> MockMemory {
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MockMemory::new(4, 5, [])
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}
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}
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#[hdl]
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struct BrPredDebugState {
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call_stack: ArrayVec<UInt<64>, ConstUsize<{ BrPredState::CALL_STACK_CAPACITY }>>,
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@ -1045,7 +1245,7 @@ type SimOnlyMemoryChunk = SimOnly<MemoryChunk>;
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#[hdl(no_static)]
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struct MockMemoryDebugState<C: PhantomConstGet<()> = PhantomConst<()>> {
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wrote_output: Bool,
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wrote_outputs: Bool,
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memory: ArrayType<SimOnlyMemoryChunk, MockMemoryDebugStateMemorySize<C>>,
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l1_cache:
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Array<TraceAsString<HdlOption<MockCacheLineDebugState>>, { MockMemory::CACHE_LINE_COUNT }>,
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@ -1053,9 +1253,9 @@ struct MockMemoryDebugState<C: PhantomConstGet<()> = PhantomConst<()>> {
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#[derive(Debug, Clone)]
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struct MockMemory {
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input: u64,
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expected_output: u64,
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wrote_output: bool,
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input: std::vec::IntoIter<u64>,
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expected_output: Vec<u64>,
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output: Vec<u64>,
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memory: BTreeMap<u64, SimOnlyValue<MemoryChunk>>,
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l1_cache: [Option<MockCacheLine>; Self::CACHE_LINE_COUNT],
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}
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@ -1106,14 +1306,14 @@ impl MockMemory {
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const LOG2_CACHE_LINE_COUNT: usize = 2;
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const CACHE_LINE_COUNT: usize = 1 << Self::LOG2_CACHE_LINE_COUNT;
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fn new<'a, I: IntoIterator<Item = (u64, &'a [u8])>>(
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input: u64,
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expected_output: u64,
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input: Vec<u64>,
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expected_output: Vec<u64>,
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initial_memory: I,
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) -> Self {
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let mut retval = Self {
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input,
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input: input.into_iter(),
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output: Vec::with_capacity(expected_output.len()),
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expected_output,
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wrote_output: false,
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memory: BTreeMap::new(),
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l1_cache: [const { None }; _],
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};
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|
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@ -1125,6 +1325,11 @@ impl MockMemory {
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retval.cache_flush();
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retval
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}
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fn wrote_outputs(&self) -> bool {
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// function filling `output` checks that it matches `expected_output`,
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// so we just need to check the length here
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self.output.len() == self.expected_output.len()
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}
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fn cache_flush(&mut self) {
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self.l1_cache.fill(None);
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}
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|
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@ -1179,11 +1384,18 @@ impl MockMemory {
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}
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Err(FillCacheError::Uncacheable) => {
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assert!(!is_speculative);
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let mut value = None;
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for (chunk_byte_index, byte) in chunk_range.zip(&mut bytes[load_store_range]) {
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let offset = chunk_addr
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.wrapping_add(chunk_byte_index as u64)
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.wrapping_sub(Self::IO_ADDR);
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let value = self.input.to_le_bytes();
|
||||
let value = value
|
||||
.get_or_insert_with(|| {
|
||||
self.input
|
||||
.next()
|
||||
.unwrap_or_else(|| panic!("read input too many times"))
|
||||
})
|
||||
.to_le_bytes();
|
||||
assert!(offset < value.len() as u64);
|
||||
*byte = value[offset as usize];
|
||||
}
|
||||
|
|
@ -1230,11 +1442,16 @@ impl MockMemory {
|
|||
value[offset as usize] = *byte;
|
||||
}
|
||||
let value = u64::from_le_bytes(value);
|
||||
assert!(
|
||||
self.output.len() < self.expected_output.len(),
|
||||
"too many outputs"
|
||||
);
|
||||
assert_eq!(
|
||||
self.expected_output, value,
|
||||
self.expected_output[self.output.len()],
|
||||
value,
|
||||
"output doesn't match expected output"
|
||||
);
|
||||
self.wrote_output = true;
|
||||
self.output.push(value);
|
||||
}
|
||||
Err(FillCacheError::CacheMiss) => return Err(AddressCantBeSpeculativelyAccessed),
|
||||
}
|
||||
|
|
@ -1267,8 +1484,8 @@ impl MockMemory {
|
|||
fn debug_state(&self) -> SimValue<MockMemoryDebugState> {
|
||||
let Self {
|
||||
input: _,
|
||||
output: _,
|
||||
expected_output: _,
|
||||
wrote_output,
|
||||
memory,
|
||||
l1_cache,
|
||||
} = self;
|
||||
|
|
@ -1276,7 +1493,7 @@ impl MockMemory {
|
|||
let empty_chunk = SimOnlyValue::new(MemoryChunk::default());
|
||||
#[hdl(sim)]
|
||||
MockMemoryDebugState::<_> {
|
||||
wrote_output,
|
||||
wrote_outputs: self.wrote_outputs(),
|
||||
memory: SimValue::from_array_elements(
|
||||
ret_ty.memory,
|
||||
memory
|
||||
|
|
@ -1409,6 +1626,37 @@ impl MockMemory {
|
|||
}
|
||||
}
|
||||
|
||||
trait FunnelShift {
|
||||
fn funnel_shl(high: Self, low: Self, shift: u32) -> Self;
|
||||
fn funnel_shr(high: Self, low: Self, shift: u32) -> Self;
|
||||
}
|
||||
|
||||
macro_rules! impl_funnel_shift {
|
||||
($ty:ident) => {
|
||||
impl FunnelShift for $ty {
|
||||
fn funnel_shl(high: Self, low: Self, shift: u32) -> Self {
|
||||
if shift == 0 {
|
||||
high
|
||||
} else {
|
||||
(high << shift) | (low >> ($ty::BITS - shift))
|
||||
}
|
||||
}
|
||||
fn funnel_shr(high: Self, low: Self, shift: u32) -> Self {
|
||||
if shift == 0 {
|
||||
high
|
||||
} else {
|
||||
(high << ($ty::BITS - shift)) | (low >> shift)
|
||||
}
|
||||
}
|
||||
}
|
||||
};
|
||||
}
|
||||
|
||||
impl_funnel_shift!(u8);
|
||||
impl_funnel_shift!(u16);
|
||||
impl_funnel_shift!(u32);
|
||||
impl_funnel_shift!(u64);
|
||||
|
||||
trait MockExecutionStateTrait: Default {
|
||||
type DebugState: BundleType;
|
||||
fn debug_state_ty() -> Self::DebugState;
|
||||
|
|
@ -1541,6 +1789,188 @@ trait MockExecutionStateTrait: Default {
|
|||
}
|
||||
}
|
||||
#[hdl]
|
||||
fn run_shift_rotate<C: PhantomConstCpuConfig>(
|
||||
&mut self,
|
||||
mop: &SimValue<ShiftRotateMOp<PRegNum<C>, PRegNum<C>>>,
|
||||
src_values: &[SimValue<TraceAsString<PRegValue>>; COMMON_MOP_SRC_LEN],
|
||||
) -> SimValue<TraceAsString<PRegValue>> {
|
||||
#[hdl(sim)]
|
||||
let ShiftRotateMOp::<_, _> { alu_common, mode } = mop;
|
||||
#[hdl(sim)]
|
||||
let AluCommonMOp::<_, _, _, _> {
|
||||
common,
|
||||
output_integer_mode,
|
||||
} = alu_common;
|
||||
#[hdl(sim)]
|
||||
let CommonMOp::<_, _, _, _, _> {
|
||||
prefix_pad: _,
|
||||
dest: _,
|
||||
src: _,
|
||||
imm,
|
||||
} = common;
|
||||
#[hdl(sim)]
|
||||
let ShiftRotateMOpImm {
|
||||
shift_rotate_amount,
|
||||
shift_rotate_right,
|
||||
shift_amount_overflow_behavior,
|
||||
dest_logic_op,
|
||||
} = imm;
|
||||
let shift_rotate_amount = #[hdl(sim)]
|
||||
match shift_rotate_amount {
|
||||
HdlSome(shift_rotate_amount) => {
|
||||
shift_rotate_amount.cast_to_static::<UInt<64>>().as_int()
|
||||
}
|
||||
HdlNone => src_values[2].inner().int_fp.as_int(),
|
||||
};
|
||||
let shifted_rotated = #[hdl(sim)]
|
||||
match mode {
|
||||
ShiftRotateMode::FunnelShift2x8Bit => {
|
||||
if shift_rotate_amount >= 8 {
|
||||
todo!("large shift_rotate_amount={shift_rotate_amount}");
|
||||
}
|
||||
if **shift_rotate_right {
|
||||
FunnelShift::funnel_shr(
|
||||
src_values[0].inner().int_fp.as_int() as u8,
|
||||
src_values[1].inner().int_fp.as_int() as u8,
|
||||
shift_rotate_amount as _,
|
||||
) as u64
|
||||
} else {
|
||||
FunnelShift::funnel_shl(
|
||||
src_values[0].inner().int_fp.as_int() as u8,
|
||||
src_values[1].inner().int_fp.as_int() as u8,
|
||||
shift_rotate_amount as _,
|
||||
) as u64
|
||||
}
|
||||
}
|
||||
ShiftRotateMode::FunnelShift2x16Bit => {
|
||||
if shift_rotate_amount >= 16 {
|
||||
todo!("large shift_rotate_amount={shift_rotate_amount}");
|
||||
}
|
||||
if **shift_rotate_right {
|
||||
FunnelShift::funnel_shr(
|
||||
src_values[0].inner().int_fp.as_int() as u16,
|
||||
src_values[1].inner().int_fp.as_int() as u16,
|
||||
shift_rotate_amount as _,
|
||||
) as u64
|
||||
} else {
|
||||
FunnelShift::funnel_shl(
|
||||
src_values[0].inner().int_fp.as_int() as u16,
|
||||
src_values[1].inner().int_fp.as_int() as u16,
|
||||
shift_rotate_amount as _,
|
||||
) as u64
|
||||
}
|
||||
}
|
||||
ShiftRotateMode::FunnelShift2x32Bit => {
|
||||
if shift_rotate_amount >= 32 {
|
||||
todo!("large shift_rotate_amount={shift_rotate_amount}");
|
||||
}
|
||||
if **shift_rotate_right {
|
||||
FunnelShift::funnel_shr(
|
||||
src_values[0].inner().int_fp.as_int() as u32,
|
||||
src_values[1].inner().int_fp.as_int() as u32,
|
||||
shift_rotate_amount as _,
|
||||
) as u64
|
||||
} else {
|
||||
FunnelShift::funnel_shl(
|
||||
src_values[0].inner().int_fp.as_int() as u32,
|
||||
src_values[1].inner().int_fp.as_int() as u32,
|
||||
shift_rotate_amount as _,
|
||||
) as u64
|
||||
}
|
||||
}
|
||||
ShiftRotateMode::FunnelShift2x64Bit => {
|
||||
if shift_rotate_amount >= 64 {
|
||||
todo!("large shift_rotate_amount={shift_rotate_amount}");
|
||||
}
|
||||
if **shift_rotate_right {
|
||||
FunnelShift::funnel_shr(
|
||||
src_values[0].inner().int_fp.as_int(),
|
||||
src_values[1].inner().int_fp.as_int(),
|
||||
shift_rotate_amount as _,
|
||||
)
|
||||
} else {
|
||||
FunnelShift::funnel_shl(
|
||||
src_values[0].inner().int_fp.as_int(),
|
||||
src_values[1].inner().int_fp.as_int(),
|
||||
shift_rotate_amount as _,
|
||||
)
|
||||
}
|
||||
}
|
||||
ShiftRotateMode::SignExt8To64BitThenShift => {
|
||||
if shift_rotate_amount >= 64 {
|
||||
todo!("large shift_rotate_amount={shift_rotate_amount}");
|
||||
}
|
||||
let input = src_values[0].inner().int_fp.as_int() as i8 as i64;
|
||||
if **shift_rotate_right {
|
||||
(input >> shift_rotate_amount) as u64
|
||||
} else {
|
||||
(input << shift_rotate_amount) as u64
|
||||
}
|
||||
}
|
||||
ShiftRotateMode::SignExt16To64BitThenShift => {
|
||||
if shift_rotate_amount >= 64 {
|
||||
todo!("large shift_rotate_amount={shift_rotate_amount}");
|
||||
}
|
||||
let input = src_values[0].inner().int_fp.as_int() as i16 as i64;
|
||||
if **shift_rotate_right {
|
||||
(input >> shift_rotate_amount) as u64
|
||||
} else {
|
||||
(input << shift_rotate_amount) as u64
|
||||
}
|
||||
}
|
||||
ShiftRotateMode::SignExt32To64BitThenShift => {
|
||||
if shift_rotate_amount >= 64 {
|
||||
todo!("large shift_rotate_amount={shift_rotate_amount}");
|
||||
}
|
||||
let input = src_values[0].inner().int_fp.as_int() as i32 as i64;
|
||||
if **shift_rotate_right {
|
||||
(input >> shift_rotate_amount) as u64
|
||||
} else {
|
||||
(input << shift_rotate_amount) as u64
|
||||
}
|
||||
}
|
||||
ShiftRotateMode::ShiftSigned64 => {
|
||||
if shift_rotate_amount >= 64 {
|
||||
todo!("large shift_rotate_amount={shift_rotate_amount}");
|
||||
}
|
||||
let input = src_values[0].inner().int_fp.as_int() as i64;
|
||||
if **shift_rotate_right {
|
||||
(input >> shift_rotate_amount) as u64
|
||||
} else {
|
||||
(input << shift_rotate_amount) as u64
|
||||
}
|
||||
}
|
||||
};
|
||||
let masked = #[hdl(sim)]
|
||||
if let HdlSome(dest_logic_op) = dest_logic_op {
|
||||
ShiftRotateDestLogicOp::operation_sim(
|
||||
dest_logic_op,
|
||||
shifted_rotated,
|
||||
&src_values[2].inner().int_fp,
|
||||
)
|
||||
.as_int()
|
||||
} else {
|
||||
shifted_rotated
|
||||
};
|
||||
let int_fp = #[hdl(sim)]
|
||||
match output_integer_mode {
|
||||
OutputIntegerMode::Full64 => masked,
|
||||
OutputIntegerMode::DupLow32 => (masked & 0xFFFFFFFF) | (masked << 32),
|
||||
OutputIntegerMode::ZeroExt32 => masked as u32 as u64,
|
||||
OutputIntegerMode::SignExt32 => masked as i32 as u64,
|
||||
OutputIntegerMode::ZeroExt16 => masked as u16 as u64,
|
||||
OutputIntegerMode::SignExt16 => masked as i16 as u64,
|
||||
OutputIntegerMode::ZeroExt8 => masked as u8 as u64,
|
||||
OutputIntegerMode::SignExt8 => masked as i8 as u64,
|
||||
};
|
||||
let retval = #[hdl(sim)]
|
||||
PRegValue {
|
||||
int_fp,
|
||||
flags: PRegFlags::zeroed_sim(), // TODO: compute flags
|
||||
};
|
||||
retval.into_trace_as_string()
|
||||
}
|
||||
#[hdl]
|
||||
fn run_branch<C: PhantomConstCpuConfig, SrcCount: KnownSize>(
|
||||
&mut self,
|
||||
id: &SimValue<MOpId>,
|
||||
|
|
@ -1582,9 +2012,11 @@ trait MockExecutionStateTrait: Default {
|
|||
.get(2)
|
||||
.is_some_and(|src2| *src2 != PRegNum[config].const_zero_sim());
|
||||
let src2_cond = if has_src2 {
|
||||
let _ = invert_src2_eq_zero;
|
||||
let _ = src2;
|
||||
todo!("has_src2");
|
||||
if **invert_src2_eq_zero {
|
||||
src2.inner().int_fp.as_int() != 0
|
||||
} else {
|
||||
src2.inner().int_fp.as_int() == 0
|
||||
}
|
||||
} else {
|
||||
true
|
||||
};
|
||||
|
|
@ -1724,9 +2156,10 @@ trait MockExecutionStateTrait: Default {
|
|||
AluBranchMOp::<_, _>::LogicalI(mop) => {
|
||||
todo!("implement LogicalI")
|
||||
}
|
||||
AluBranchMOp::<_, _>::ShiftRotate(mop) => {
|
||||
todo!("implement ShiftRotate")
|
||||
}
|
||||
AluBranchMOp::<_, _>::ShiftRotate(mop) => (
|
||||
Some((self.run_shift_rotate(mop, src_values), empty_predictor_op())),
|
||||
None,
|
||||
),
|
||||
AluBranchMOp::<_, _>::Compare(mop) => (
|
||||
Some((self.run_compare(mop, src_values), empty_predictor_op())),
|
||||
None,
|
||||
|
|
@ -3367,7 +3800,7 @@ fn mock_load_store_unit<#[hdl(skip)] MI: MakeInsns>(
|
|||
.await;
|
||||
}
|
||||
sim.write(debug_state, state.debug_state()).await;
|
||||
sim.write(all_outputs_written, state.memory.wrote_output)
|
||||
sim.write(all_outputs_written, state.memory.wrote_outputs())
|
||||
.await;
|
||||
sim.wait_for_clock_edge(cd.clk).await;
|
||||
{
|
||||
|
|
@ -3489,6 +3922,59 @@ fn rename_execute_retire_test_harness<#[hdl(skip)] MI: MakeInsns>(config: Phanto
|
|||
}
|
||||
}
|
||||
|
||||
struct FibonacciInsns;
|
||||
|
||||
impl MakeInsns for FibonacciInsns {
|
||||
fn make_insns() -> Insns {
|
||||
let mut b = InsnsBuilder::new();
|
||||
|
||||
let fib = b.new_label("fib");
|
||||
let fib_small = b.new_label("fib_small");
|
||||
b.power_isa_ld(3, 0, MockMemory::IO_ADDR as i16); // load input
|
||||
b.power_isa_addi(1, 0, 0x4000); // setup stack pointer
|
||||
b.power_isa_bl(fib);
|
||||
b.power_isa_std(3, 0, MockMemory::IO_ADDR as i16); // store output
|
||||
let done = b.new_defined_label("done");
|
||||
b.power_isa_b(done);
|
||||
|
||||
b.set_pc(0x1000);
|
||||
b.define_label(fib);
|
||||
b.power_isa_cmpldi(0, 3, 1);
|
||||
b.power_isa_ble(fib_small); // if input <= 1 goto fib_small
|
||||
|
||||
// push stack frame
|
||||
b.power_isa_mflr(0);
|
||||
b.power_isa_addi(1, 1, -16);
|
||||
b.power_isa_std(0, 1, 0);
|
||||
b.power_isa_std(30, 1, 8);
|
||||
|
||||
b.power_isa_addi(30, 3, -2);
|
||||
b.power_isa_addi(3, 3, -1);
|
||||
b.power_isa_bl(fib); // fib(input - 1)
|
||||
b.power_isa_mr(2, 3);
|
||||
b.power_isa_mr(3, 30);
|
||||
b.power_isa_mr(30, 2);
|
||||
b.power_isa_bl(fib); // fib(input - 2)
|
||||
b.power_isa_add(3, 3, 30); // set output to fib(input - 1) + fib(input - 2)
|
||||
|
||||
// pop stack frame and return
|
||||
b.power_isa_ld(0, 1, 0);
|
||||
b.power_isa_ld(30, 1, 8);
|
||||
b.power_isa_addi(1, 1, 16);
|
||||
b.power_isa_mtlr(0);
|
||||
b.power_isa_blr();
|
||||
|
||||
b.define_label(fib_small);
|
||||
b.power_isa_addi(3, 0, 1); // set output to 1
|
||||
b.power_isa_blr(); // return
|
||||
|
||||
b.build()
|
||||
}
|
||||
fn make_load_store_execution_state() -> MockMemory {
|
||||
MockMemory::new(vec![4], vec![5], [])
|
||||
}
|
||||
}
|
||||
|
||||
#[hdl]
|
||||
#[test]
|
||||
fn test_rename_execute_retire_fibonacci() {
|
||||
|
|
@ -3613,8 +4099,8 @@ impl MakeInsns for SlowLoopInsns {
|
|||
});
|
||||
let loop_count = 4;
|
||||
MockMemory::new(
|
||||
loop_count,
|
||||
expected * loop_count * 2u64.pow(Self::LOG2_RESULT_FACTOR),
|
||||
vec![loop_count],
|
||||
vec![expected * loop_count * 2u64.pow(Self::LOG2_RESULT_FACTOR)],
|
||||
[(Self::CONSTANTS_ADDR, constants.as_flattened())],
|
||||
)
|
||||
}
|
||||
|
|
@ -3674,3 +4160,139 @@ fn test_rename_execute_retire_slow_loop() {
|
|||
panic!();
|
||||
}
|
||||
}
|
||||
|
||||
/// equivalent of Unix's `head -n1`
|
||||
struct HeadN1Insns;
|
||||
|
||||
impl HeadN1Insns {
|
||||
const BUFFER_SIZE: u64 = 0x100;
|
||||
const MAIN_STACK_FRAME_SIZE: u64 = (Self::BUFFER_SIZE + 0x20).next_multiple_of(0x10);
|
||||
const BUFFER_OFFSET_FROM_SP: i16 = (Self::MAIN_STACK_FRAME_SIZE - Self::BUFFER_SIZE) as i16;
|
||||
const TEST_INPUT: &str = "Test input.\nLine 2";
|
||||
}
|
||||
|
||||
impl MakeInsns for HeadN1Insns {
|
||||
fn make_insns() -> Insns {
|
||||
let mut b = InsnsBuilder::new();
|
||||
|
||||
let main = b.new_label("main");
|
||||
b.power_isa_addi(1, 0, 0x4000); // setup stack pointer
|
||||
b.power_isa_bl(main);
|
||||
let done = b.new_defined_label("done");
|
||||
b.power_isa_b(done);
|
||||
|
||||
b.set_pc(0xF00);
|
||||
let error = b.new_defined_label("error");
|
||||
b.power_isa_addi(3, 0, -1);
|
||||
b.power_isa_std(3, 0, MockMemory::IO_ADDR as i16);
|
||||
b.power_isa_b(error);
|
||||
|
||||
b.set_pc(0x1000);
|
||||
b.define_label(main);
|
||||
b.power_isa_stdu(1, 1, -(Self::MAIN_STACK_FRAME_SIZE as i16));
|
||||
b.power_isa_ld(4, 0, MockMemory::IO_ADDR as i16);
|
||||
b.power_isa_addi(3, 0, Self::BUFFER_SIZE as i16);
|
||||
b.power_isa_addi(5, 1, Self::BUFFER_OFFSET_FROM_SP - 1);
|
||||
b.power_isa_mtctr(3);
|
||||
b.power_isa_addi(3, 0, 0);
|
||||
|
||||
let read_loop = b.new_defined_label("read_loop");
|
||||
b.power_isa_clrlwi(6, 4, 24);
|
||||
b.power_isa_cmplwi(0, 6, b'\n' as u16);
|
||||
let done_reading = b.new_label("done_reading");
|
||||
b.power_isa_beq(done_reading);
|
||||
|
||||
b.power_isa_stb(4, 5, 1);
|
||||
b.power_isa_addi(5, 5, 1);
|
||||
b.power_isa_addi(3, 3, 1);
|
||||
b.power_isa_ld(4, 0, MockMemory::IO_ADDR as i16);
|
||||
b.power_isa_bdnz(read_loop);
|
||||
|
||||
b.power_isa_bl(error);
|
||||
|
||||
b.define_label(done_reading);
|
||||
b.power_isa_cmpldi(0, 3, 0);
|
||||
let done_writing = b.new_label("done_writing");
|
||||
b.power_isa_beq(done_writing);
|
||||
|
||||
b.power_isa_addi(4, 1, Self::BUFFER_OFFSET_FROM_SP - 1);
|
||||
b.power_isa_mtctr(3);
|
||||
|
||||
let write_loop = b.new_defined_label("write_loop");
|
||||
b.power_isa_lbzu(3, 4, 1);
|
||||
b.power_isa_std(3, 0, MockMemory::IO_ADDR as i16);
|
||||
b.power_isa_bdnz(write_loop);
|
||||
|
||||
b.define_label(done_writing);
|
||||
b.power_isa_addi(3, 0, b'\n' as i16);
|
||||
b.power_isa_std(3, 0, MockMemory::IO_ADDR as i16);
|
||||
b.power_isa_addi(1, 1, Self::MAIN_STACK_FRAME_SIZE as i16);
|
||||
b.power_isa_blr();
|
||||
|
||||
b.build()
|
||||
}
|
||||
fn make_load_store_execution_state() -> MockMemory {
|
||||
MockMemory::new(
|
||||
Self::TEST_INPUT.bytes().map(|b| b as u64).collect(),
|
||||
Self::TEST_INPUT
|
||||
.split_inclusive('\n')
|
||||
.next()
|
||||
.expect("known to contain a newline")
|
||||
.bytes()
|
||||
.map(|b| b as u64)
|
||||
.collect(),
|
||||
[],
|
||||
)
|
||||
}
|
||||
}
|
||||
|
||||
#[hdl]
|
||||
#[test]
|
||||
fn test_rename_execute_retire_head_n1() {
|
||||
let _n = SourceLocation::normalize_files_for_tests();
|
||||
let mut config = CpuConfig::new(
|
||||
vec![
|
||||
UnitConfig::new(UnitKind::AluBranch),
|
||||
UnitConfig::new(UnitKind::AluBranch),
|
||||
UnitConfig::new(UnitKind::LoadStore),
|
||||
UnitConfig::new(UnitKind::TransformedMove),
|
||||
],
|
||||
NonZeroUsize::new(20).unwrap(),
|
||||
);
|
||||
config.fetch_width = NonZeroUsize::new(2).unwrap();
|
||||
let m = rename_execute_retire_test_harness::<HeadN1Insns>(PhantomConst::new_sized(config));
|
||||
let mut sim = Simulation::new(m);
|
||||
let writer = RcWriter::default();
|
||||
sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
|
||||
struct DumpVcdOnDrop {
|
||||
writer: Option<RcWriter>,
|
||||
}
|
||||
impl Drop for DumpVcdOnDrop {
|
||||
fn drop(&mut self) {
|
||||
if let Some(mut writer) = self.writer.take() {
|
||||
let vcd = String::from_utf8(writer.take()).unwrap();
|
||||
println!("####### VCD:\n{vcd}\n#######");
|
||||
}
|
||||
}
|
||||
}
|
||||
let mut writer = DumpVcdOnDrop {
|
||||
writer: Some(writer),
|
||||
};
|
||||
sim.write_clock(sim.io().cd.clk, false);
|
||||
sim.write_reset(sim.io().cd.rst, true);
|
||||
for cycle in 0..200 {
|
||||
sim.advance_time(SimDuration::from_nanos(500));
|
||||
println!("clock tick: {cycle}");
|
||||
sim.write_clock(sim.io().cd.clk, true);
|
||||
sim.advance_time(SimDuration::from_nanos(500));
|
||||
sim.write_clock(sim.io().cd.clk, false);
|
||||
sim.write_reset(sim.io().cd.rst, false);
|
||||
}
|
||||
assert!(sim.read_bool(sim.io().all_outputs_written));
|
||||
// FIXME: vcd is just whatever rename_execute_retire does now, which isn't known to be correct
|
||||
let vcd = String::from_utf8(writer.writer.take().unwrap().take()).unwrap();
|
||||
println!("####### VCD:\n{vcd}\n#######");
|
||||
if vcd != include_str!("expected/rename_execute_retire_head_n1.vcd") {
|
||||
panic!();
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue