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change MOp to use SrcReg: Type instead of UIntType<SrcRegWidth>

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This commit is contained in:
Jacob Lifshay 2026-05-07 19:52:51 -07:00
parent 409ca7bf97
commit 5e6041a97c
Signed by: programmerjake
SSH key fingerprint: SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
17 changed files with 25735 additions and 25103 deletions
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176
crates/cpu/src/decoder/simple_power_isa.rs
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@ -604,7 +604,7 @@ impl DecodeState<'_> {
}], }],
[], [],
), ),
MOpRegNum::const_zero().value, [MOpRegNum::const_zero(); 2],
(li << 2).cast_to_static(), (li << 2).cast_to_static(),
!aa, !aa,
lk, lk,
@ -646,7 +646,7 @@ impl DecodeState<'_> {
#[hdl] #[hdl]
let branch_ctr_reg: MOpRegNum = wire(); let branch_ctr_reg: MOpRegNum = wire();
let dest = MOpDestReg::new([branch_lr_dest_reg], []); let dest = MOpDestReg::new([branch_lr_dest_reg], []);
let src1 = addr_reg.unwrap_or_else(|| MOpRegNum::const_zero()).value; let src1 = addr_reg.unwrap_or_else(|| MOpRegNum::const_zero());
let imm: Expr<SInt<_>> = (bd.unwrap_or(0_hdl_i14) << 2).cast_to_static(); let imm: Expr<SInt<_>> = (bd.unwrap_or(0_hdl_i14) << 2).cast_to_static();
let invert_src2_eq_zero = !use_eq_for_ctr_compare; let invert_src2_eq_zero = !use_eq_for_ctr_compare;
let pc_relative = match aa { let pc_relative = match aa {
@ -659,7 +659,7 @@ impl DecodeState<'_> {
branch_mop, branch_mop,
BranchMOp::branch_i( BranchMOp::branch_i(
dest, dest,
src1, [MOpRegNum::const_zero(), src1],
imm.cast_to_static::<SInt<_>>(), imm.cast_to_static::<SInt<_>>(),
pc_relative, pc_relative,
lk, lk,
@ -671,8 +671,7 @@ impl DecodeState<'_> {
branch_mop, branch_mop,
BranchMOp::branch_ctr( BranchMOp::branch_ctr(
dest, dest,
src1, [MOpRegNum::const_zero(), src1, branch_ctr_reg],
branch_ctr_reg.value,
imm, imm,
invert_src2_eq_zero, invert_src2_eq_zero,
pc_relative, pc_relative,
@ -685,7 +684,7 @@ impl DecodeState<'_> {
branch_mop, branch_mop,
BranchMOp::branch_cond_ctr( BranchMOp::branch_cond_ctr(
dest, dest,
[cr_field.value, src1, branch_ctr_reg.value], [cr_field, src1, branch_ctr_reg],
imm, imm,
!expected_cr_bit_value, !expected_cr_bit_value,
condition_mode, condition_mode,
@ -713,10 +712,7 @@ impl DecodeState<'_> {
this.output[0], this.output[0],
AddSubMOp::add_sub_i( AddSubMOp::add_sub_i(
MOpDestReg::new([MOpRegNum::power_isa_ctr_reg()], []), MOpDestReg::new([MOpRegNum::power_isa_ctr_reg()], []),
[ [MOpRegNum::power_isa_ctr_reg(), MOpRegNum::const_zero()],
MOpRegNum::power_isa_ctr_reg().value,
MOpRegNum::const_zero().value,
],
(-1).cast_to_static::<SInt<_>>(), (-1).cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
false, false,
@ -789,7 +785,7 @@ impl DecodeState<'_> {
this.output[0], this.output[0],
LogicalFlagsMOp::logical_flags( LogicalFlagsMOp::logical_flags(
MOpDestReg::new([bt_reg], []), MOpDestReg::new([bt_reg], []),
[ba_reg.value, bb_reg.value, bt_reg.value], [ba_reg, bb_reg, bt_reg],
#[hdl] #[hdl]
LogicalFlagsMOpImm { LogicalFlagsMOpImm {
src0_start: src0_start.cast_to(LogicalFlagsMOpImm.src0_start), src0_start: src0_start.cast_to(LogicalFlagsMOpImm.src0_start),
@ -815,7 +811,7 @@ impl DecodeState<'_> {
this.output[0], this.output[0],
MoveRegMOp::move_reg( MoveRegMOp::move_reg(
MOpDestReg::new([crf(bf)], []), MOpDestReg::new([crf(bf)], []),
[crf(bfa).value], [crf(bfa)],
0i8.cast_to_static::<SInt<_>>(), 0i8.cast_to_static::<SInt<_>>(),
), ),
); );
@ -892,7 +888,7 @@ impl DecodeState<'_> {
this.output[0], this.output[0],
AddSubMOp::add_sub_i( AddSubMOp::add_sub_i(
MOpDestReg::new([ea_reg], []), MOpDestReg::new([ea_reg], []),
[MOpRegNum::const_zero().value; 2], [MOpRegNum::const_zero(); 2],
d, d,
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
false, false,
@ -906,7 +902,7 @@ impl DecodeState<'_> {
this.output[0], this.output[0],
AddSubMOp::add_sub_i( AddSubMOp::add_sub_i(
MOpDestReg::new([ea_reg], []), MOpDestReg::new([ea_reg], []),
[gpr_or_zero(ra).value, MOpRegNum::const_zero().value], [gpr_or_zero(ra), MOpRegNum::const_zero()],
d, d,
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
false, false,
@ -918,12 +914,7 @@ impl DecodeState<'_> {
} }
connect( connect(
this.output[1], this.output[1],
LoadMOp::load( LoadMOp::load(MOpDestReg::new([gpr(rt)], []), [ea_reg], width, conversion),
MOpDestReg::new([gpr(rt)], []),
[ea_reg.value],
width,
conversion,
),
); );
}, },
); );
@ -939,7 +930,7 @@ impl DecodeState<'_> {
this.output[0], this.output[0],
AddSubMOp::add_sub_i( AddSubMOp::add_sub_i(
MOpDestReg::new([ea_reg], []), MOpDestReg::new([ea_reg], []),
[gpr_or_zero(ra).value, gpr(rb).value], [gpr_or_zero(ra), gpr(rb)],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
false, false,
@ -950,12 +941,7 @@ impl DecodeState<'_> {
); );
connect( connect(
this.output[1], this.output[1],
LoadMOp::load( LoadMOp::load(MOpDestReg::new([gpr(rt)], []), [ea_reg], width, conversion),
MOpDestReg::new([gpr(rt)], []),
[ea_reg.value],
width,
conversion,
),
); );
}); });
} else if self.arguments == Some("RT,disp(RA)") { } else if self.arguments == Some("RT,disp(RA)") {
@ -969,7 +955,7 @@ impl DecodeState<'_> {
this.output[0], this.output[0],
AddSubMOp::add_sub_i( AddSubMOp::add_sub_i(
MOpDestReg::new([ea_reg], []), MOpDestReg::new([ea_reg], []),
[gpr_or_zero(ra).value, MOpRegNum::const_zero().value], [gpr_or_zero(ra), MOpRegNum::const_zero()],
(ds << 2).cast_to_static::<SInt<_>>(), (ds << 2).cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
false, false,
@ -980,12 +966,7 @@ impl DecodeState<'_> {
); );
connect( connect(
this.output[1], this.output[1],
LoadMOp::load( LoadMOp::load(MOpDestReg::new([gpr(rt)], []), [ea_reg], width, conversion),
MOpDestReg::new([gpr(rt)], []),
[ea_reg.value],
width,
conversion,
),
); );
}); });
} else { } else {
@ -1005,7 +986,7 @@ impl DecodeState<'_> {
this.output[0], this.output[0],
AddSubMOp::add_sub_i( AddSubMOp::add_sub_i(
MOpDestReg::new([ea_reg], []), MOpDestReg::new([ea_reg], []),
[gpr_or_zero(ra).value, MOpRegNum::const_zero().value], [gpr_or_zero(ra), MOpRegNum::const_zero()],
d.cast_to_static::<SInt<_>>(), d.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
false, false,
@ -1016,12 +997,7 @@ impl DecodeState<'_> {
); );
connect( connect(
this.output[1], this.output[1],
LoadMOp::load( LoadMOp::load(MOpDestReg::new([gpr(rt)], []), [ea_reg], width, conversion),
MOpDestReg::new([gpr(rt)], []),
[ea_reg.value],
width,
conversion,
),
); );
}); });
} }
@ -1092,7 +1068,7 @@ impl DecodeState<'_> {
this.output[1], this.output[1],
StoreMOp::store( StoreMOp::store(
MOpDestReg::new([], []), MOpDestReg::new([], []),
[ea_reg.value, gpr(rs).value], [ea_reg, gpr(rs)],
width, width,
LoadStoreConversion.ZeroExt(), LoadStoreConversion.ZeroExt(),
), ),
@ -1107,7 +1083,7 @@ impl DecodeState<'_> {
this.output[2], this.output[2],
MoveRegMOp::move_reg( MoveRegMOp::move_reg(
MOpDestReg::new([gpr(ra)], []), MOpDestReg::new([gpr(ra)], []),
[ea_reg.value], [ea_reg],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
), ),
); );
@ -1126,7 +1102,7 @@ impl DecodeState<'_> {
insn, insn,
AddSubMOp::add_sub_i( AddSubMOp::add_sub_i(
MOpDestReg::new([ea_reg], []), MOpDestReg::new([ea_reg], []),
[MOpRegNum::const_zero().value; 2], [MOpRegNum::const_zero(); 2],
d, d,
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
false, false,
@ -1140,7 +1116,7 @@ impl DecodeState<'_> {
insn, insn,
AddSubMOp::add_sub_i( AddSubMOp::add_sub_i(
MOpDestReg::new([ea_reg], []), MOpDestReg::new([ea_reg], []),
[gpr_or_zero(ra).value, MOpRegNum::const_zero().value], [gpr_or_zero(ra), MOpRegNum::const_zero()],
d, d,
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
false, false,
@ -1161,7 +1137,7 @@ impl DecodeState<'_> {
insn, insn,
AddSubMOp::add_sub_i( AddSubMOp::add_sub_i(
MOpDestReg::new([ea_reg], []), MOpDestReg::new([ea_reg], []),
[gpr_or_zero(ra).value, gpr(rb).value], [gpr_or_zero(ra), gpr(rb)],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
false, false,
@ -1179,7 +1155,7 @@ impl DecodeState<'_> {
insn, insn,
AddSubMOp::add_sub_i( AddSubMOp::add_sub_i(
MOpDestReg::new([ea_reg], []), MOpDestReg::new([ea_reg], []),
[gpr_or_zero(ra).value, MOpRegNum::const_zero().value], [gpr_or_zero(ra), MOpRegNum::const_zero()],
(ds << 2).cast_to_static::<SInt<_>>(), (ds << 2).cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
false, false,
@ -1203,7 +1179,7 @@ impl DecodeState<'_> {
insn, insn,
AddSubMOp::add_sub_i( AddSubMOp::add_sub_i(
MOpDestReg::new([ea_reg], []), MOpDestReg::new([ea_reg], []),
[gpr_or_zero(ra).value, MOpRegNum::const_zero().value], [gpr_or_zero(ra), MOpRegNum::const_zero()],
d.cast_to_static::<SInt<_>>(), d.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
false, false,
@ -1230,7 +1206,7 @@ impl DecodeState<'_> {
AddSubMOp::add_sub_i( AddSubMOp::add_sub_i(
MOpDestReg::new([gpr(rt)], []), MOpDestReg::new([gpr(rt)], []),
#[hdl] #[hdl]
[gpr_or_zero(ra).value, MOpRegNum::const_zero().value], [gpr_or_zero(ra), MOpRegNum::const_zero()],
si.cast_to_static(), si.cast_to_static(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
false, false,
@ -1253,7 +1229,7 @@ impl DecodeState<'_> {
AddSubMOp::add_sub_i( AddSubMOp::add_sub_i(
MOpDestReg::new([gpr(rt)], []), MOpDestReg::new([gpr(rt)], []),
#[hdl] #[hdl]
[gpr_or_zero(ra).value, MOpRegNum::const_zero().value], [gpr_or_zero(ra), MOpRegNum::const_zero()],
((si0 << 16) + si1.cast_to(SInt[34])).cast_to_static(), ((si0 << 16) + si1.cast_to(SInt[34])).cast_to_static(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
false, false,
@ -1280,7 +1256,7 @@ impl DecodeState<'_> {
AddSubMOp::add_sub_i( AddSubMOp::add_sub_i(
MOpDestReg::new([gpr(rt)], []), MOpDestReg::new([gpr(rt)], []),
#[hdl] #[hdl]
[gpr_or_zero(ra).value, MOpRegNum::const_zero().value], [gpr_or_zero(ra), MOpRegNum::const_zero()],
(si << 16).cast_to_static(), (si << 16).cast_to_static(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
false, false,
@ -1307,7 +1283,7 @@ impl DecodeState<'_> {
AddSubMOp::add_sub_i( AddSubMOp::add_sub_i(
MOpDestReg::new([gpr(rt)], []), MOpDestReg::new([gpr(rt)], []),
#[hdl] #[hdl]
[MOpRegNum::const_zero().value; 2], [MOpRegNum::const_zero(); 2],
(4i8 + (d << 16)).cast_to_static(), (4i8 + (d << 16)).cast_to_static(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
false, false,
@ -1340,7 +1316,7 @@ impl DecodeState<'_> {
], ],
), ),
#[hdl] #[hdl]
[gpr(ra).value, gpr(rb).value, MOpRegNum::const_zero().value], [gpr(ra), gpr(rb), MOpRegNum::const_zero()],
0i8.cast_to_static::<SInt<_>>(), 0i8.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
false, false,
@ -1371,7 +1347,7 @@ impl DecodeState<'_> {
)], )],
), ),
#[hdl] #[hdl]
[gpr(ra).value, MOpRegNum::const_zero().value], [gpr(ra), MOpRegNum::const_zero()],
si.cast_to_static(), si.cast_to_static(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
false, false,
@ -1410,7 +1386,7 @@ impl DecodeState<'_> {
], ],
), ),
#[hdl] #[hdl]
[gpr(ra).value, gpr(rb).value, MOpRegNum::const_zero().value], [gpr(ra), gpr(rb), MOpRegNum::const_zero()],
0i8.cast_to_static::<SInt<_>>(), 0i8.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
true, true,
@ -1440,7 +1416,7 @@ impl DecodeState<'_> {
)], )],
), ),
#[hdl] #[hdl]
[gpr(ra).value, MOpRegNum::const_zero().value], [gpr(ra), MOpRegNum::const_zero()],
si.cast_to_static(), si.cast_to_static(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
true, true,
@ -1472,7 +1448,7 @@ impl DecodeState<'_> {
], ],
), ),
#[hdl] #[hdl]
[gpr(ra).value, gpr(rb).value, MOpRegNum::const_zero().value], [gpr(ra), gpr(rb), MOpRegNum::const_zero()],
0i8.cast_to_static::<SInt<_>>(), 0i8.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
false, false,
@ -1505,11 +1481,7 @@ impl DecodeState<'_> {
], ],
), ),
#[hdl] #[hdl]
[ [gpr(ra), MOpRegNum::power_isa_xer_ca_ca32_reg(), gpr(rb)],
gpr(ra).value,
MOpRegNum::power_isa_xer_ca_ca32_reg().value,
gpr(rb).value,
],
0i8.cast_to_static::<SInt<_>>(), 0i8.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
false, false,
@ -1542,11 +1514,7 @@ impl DecodeState<'_> {
], ],
), ),
#[hdl] #[hdl]
[ [gpr(ra), MOpRegNum::power_isa_xer_ca_ca32_reg(), gpr(rb)],
gpr(ra).value,
MOpRegNum::power_isa_xer_ca_ca32_reg().value,
gpr(rb).value,
],
0i8.cast_to_static::<SInt<_>>(), 0i8.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
true, true,
@ -1580,9 +1548,9 @@ impl DecodeState<'_> {
), ),
#[hdl] #[hdl]
[ [
gpr(ra).value, gpr(ra),
MOpRegNum::power_isa_xer_ca_ca32_reg().value, MOpRegNum::power_isa_xer_ca_ca32_reg(),
MOpRegNum::const_zero().value, MOpRegNum::const_zero(),
], ],
if this.mnemonic.contains('m') { -1i8 } else { 0 } if this.mnemonic.contains('m') { -1i8 } else { 0 }
.cast_to_static::<SInt<_>>(), .cast_to_static::<SInt<_>>(),
@ -1617,11 +1585,7 @@ impl DecodeState<'_> {
], ],
), ),
#[hdl] #[hdl]
[ [gpr(ra), MOpRegNum::const_zero(), MOpRegNum::const_zero()],
gpr(ra).value,
MOpRegNum::const_zero().value,
MOpRegNum::const_zero().value,
],
0i8.cast_to_static::<SInt<_>>(), 0i8.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
true, true,
@ -1654,7 +1618,7 @@ impl DecodeState<'_> {
this.output[0], this.output[0],
CompareMOp::compare_i( CompareMOp::compare_i(
MOpDestReg::new([crf(bf)], []), MOpDestReg::new([crf(bf)], []),
[gpr(ra).value], [gpr(ra)],
si.cast_to_static::<SInt<_>>(), si.cast_to_static::<SInt<_>>(),
compare_mode, compare_mode,
), ),
@ -1682,7 +1646,7 @@ impl DecodeState<'_> {
this.output[0], this.output[0],
CompareMOp::compare( CompareMOp::compare(
MOpDestReg::new([crf(bf)], []), MOpDestReg::new([crf(bf)], []),
[gpr(ra).value, gpr(rb).value], [gpr(ra), gpr(rb)],
compare_mode, compare_mode,
), ),
); );
@ -1709,7 +1673,7 @@ impl DecodeState<'_> {
this.output[0], this.output[0],
CompareMOp::compare_i( CompareMOp::compare_i(
MOpDestReg::new([crf(bf)], []), MOpDestReg::new([crf(bf)], []),
[gpr(ra).value], [gpr(ra)],
ui.cast_to_static::<SInt<_>>(), ui.cast_to_static::<SInt<_>>(),
compare_mode, compare_mode,
), ),
@ -1737,7 +1701,7 @@ impl DecodeState<'_> {
this.output[0], this.output[0],
CompareMOp::compare( CompareMOp::compare(
MOpDestReg::new([crf(bf)], []), MOpDestReg::new([crf(bf)], []),
[gpr(ra).value, gpr(rb).value], [gpr(ra), gpr(rb)],
compare_mode, compare_mode,
), ),
); );
@ -1764,7 +1728,7 @@ impl DecodeState<'_> {
this.output[0], this.output[0],
CompareMOp::compare( CompareMOp::compare(
MOpDestReg::new([crf(bf)], []), MOpDestReg::new([crf(bf)], []),
[gpr(ra).value, gpr(rb).value], [gpr(ra), gpr(rb)],
compare_mode, compare_mode,
), ),
); );
@ -1783,7 +1747,7 @@ impl DecodeState<'_> {
this.output[0], this.output[0],
CompareMOp::compare( CompareMOp::compare(
MOpDestReg::new([crf(bf)], []), MOpDestReg::new([crf(bf)], []),
[gpr(ra).value, gpr(rb).value], [gpr(ra), gpr(rb)],
CompareMode.CmpEqB(), CompareMode.CmpEqB(),
), ),
); );
@ -1815,7 +1779,7 @@ impl DecodeState<'_> {
this.mnemonic.contains('.').to_expr(), this.mnemonic.contains('.').to_expr(),
)], )],
), ),
[gpr(rs).value], [gpr(rs)],
if this.mnemonic.contains('s') { if this.mnemonic.contains('s') {
(ui << 16).cast_to_static::<SInt<_>>() (ui << 16).cast_to_static::<SInt<_>>()
} else { } else {
@ -1863,7 +1827,7 @@ impl DecodeState<'_> {
this.output[0], this.output[0],
LogicalMOp::logical( LogicalMOp::logical(
MOpDestReg::new([gpr(ra)], [(MOpRegNum::POWER_ISA_CR_0_REG_NUM, rc)]), MOpDestReg::new([gpr(ra)], [(MOpRegNum::POWER_ISA_CR_0_REG_NUM, rc)]),
[gpr(rs).value, gpr(rb).value], [gpr(rs), gpr(rb)],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
lut, lut,
@ -1877,7 +1841,7 @@ impl DecodeState<'_> {
this.output[0], this.output[0],
MoveRegMOp::move_reg( MoveRegMOp::move_reg(
MOpDestReg::new([gpr(ra)], []), MOpDestReg::new([gpr(ra)], []),
[gpr(rs).value], [gpr(rs)],
0i8.cast_to_static::<SInt<_>>(), 0i8.cast_to_static::<SInt<_>>(),
), ),
); );
@ -1906,7 +1870,7 @@ impl DecodeState<'_> {
this.output[0], this.output[0],
LogicalMOp::logical_i( LogicalMOp::logical_i(
MOpDestReg::new([gpr(ra)], [(MOpRegNum::POWER_ISA_CR_0_REG_NUM, rc)]), MOpDestReg::new([gpr(ra)], [(MOpRegNum::POWER_ISA_CR_0_REG_NUM, rc)]),
[gpr(rs).value], [gpr(rs)],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
output_integer_mode, output_integer_mode,
Lut4::from_fn(|a, b| a | b), Lut4::from_fn(|a, b| a | b),
@ -1984,7 +1948,7 @@ impl DecodeState<'_> {
self.output[0], self.output[0],
ShiftRotateMOp::shift_rotate( ShiftRotateMOp::shift_rotate(
MOpDestReg::new([gpr(ra.0)], [(MOpRegNum::POWER_ISA_CR_0_REG_NUM, rc.0)]), MOpDestReg::new([gpr(ra.0)], [(MOpRegNum::POWER_ISA_CR_0_REG_NUM, rc.0)]),
[gpr(rs.0).value, gpr(rs.0).value, gpr(rb.0).value], [gpr(rs.0), gpr(rs.0), gpr(rb.0)],
#[hdl] #[hdl]
ShiftRotateMOpImm { ShiftRotateMOpImm {
shift_rotate_amount: HdlNone(), shift_rotate_amount: HdlNone(),
@ -2021,20 +1985,20 @@ impl DecodeState<'_> {
self.rotate_dest_logic_op(msb0_mask_begin, msb0_mask_end, fallback_is_src2); self.rotate_dest_logic_op(msb0_mask_begin, msb0_mask_end, fallback_is_src2);
#[hdl] #[hdl]
let rotate_imm_src2 = wire(); let rotate_imm_src2 = wire();
connect(rotate_imm_src2, MOpRegNum::const_zero().value); connect(rotate_imm_src2, MOpRegNum::const_zero());
// if dest_logic_op is HdlNone, we don't need to read from src2 // if dest_logic_op is HdlNone, we don't need to read from src2
#[hdl] #[hdl]
if let HdlSome(dest_logic_op) = dest_logic_op { if let HdlSome(dest_logic_op) = dest_logic_op {
#[hdl] #[hdl]
if dest_logic_op.fallback_is_src2 { if dest_logic_op.fallback_is_src2 {
connect(rotate_imm_src2, gpr(ra.0).value); connect(rotate_imm_src2, gpr(ra.0));
} }
} }
connect( connect(
self.output[0], self.output[0],
ShiftRotateMOp::shift_rotate( ShiftRotateMOp::shift_rotate(
MOpDestReg::new([gpr(ra.0)], [(MOpRegNum::POWER_ISA_CR_0_REG_NUM, rc.0)]), MOpDestReg::new([gpr(ra.0)], [(MOpRegNum::POWER_ISA_CR_0_REG_NUM, rc.0)]),
[gpr(rs.0).value, gpr(rs.0).value, rotate_imm_src2], [gpr(rs.0), gpr(rs.0), rotate_imm_src2],
#[hdl] #[hdl]
ShiftRotateMOpImm { ShiftRotateMOpImm {
shift_rotate_amount: HdlSome(rotate_amount), shift_rotate_amount: HdlSome(rotate_amount),
@ -2184,11 +2148,7 @@ impl DecodeState<'_> {
[gpr(ra), MOpRegNum::power_isa_xer_ca_ca32_reg()], [gpr(ra), MOpRegNum::power_isa_xer_ca_ca32_reg()],
[(MOpRegNum::POWER_ISA_CR_0_REG_NUM, rc)], [(MOpRegNum::POWER_ISA_CR_0_REG_NUM, rc)],
), ),
[ [gpr(rs), MOpRegNum::const_zero(), MOpRegNum::const_zero()],
gpr(rs).value,
MOpRegNum::const_zero().value,
MOpRegNum::const_zero().value,
],
#[hdl] #[hdl]
ShiftRotateMOpImm { ShiftRotateMOpImm {
shift_rotate_amount: HdlSome(sh.cast_to_static::<UInt<_>>()), shift_rotate_amount: HdlSome(sh.cast_to_static::<UInt<_>>()),
@ -2216,11 +2176,7 @@ impl DecodeState<'_> {
[gpr(ra), MOpRegNum::power_isa_xer_ca_ca32_reg()], [gpr(ra), MOpRegNum::power_isa_xer_ca_ca32_reg()],
[(MOpRegNum::POWER_ISA_CR_0_REG_NUM, rc)], [(MOpRegNum::POWER_ISA_CR_0_REG_NUM, rc)],
), ),
[ [gpr(rs), MOpRegNum::const_zero(), MOpRegNum::const_zero()],
gpr(rs).value,
MOpRegNum::const_zero().value,
MOpRegNum::const_zero().value,
],
#[hdl] #[hdl]
ShiftRotateMOpImm { ShiftRotateMOpImm {
shift_rotate_amount: HdlSome(sh.rotate_right(1)), shift_rotate_amount: HdlSome(sh.rotate_right(1)),
@ -2258,9 +2214,9 @@ impl DecodeState<'_> {
[(MOpRegNum::POWER_ISA_CR_0_REG_NUM, rc)], [(MOpRegNum::POWER_ISA_CR_0_REG_NUM, rc)],
), ),
if !is_signed && is_right_shift { if !is_signed && is_right_shift {
[MOpRegNum::const_zero().value, gpr(rs).value, gpr(rb).value] [MOpRegNum::const_zero(), gpr(rs), gpr(rb)]
} else { } else {
[gpr(rs).value, MOpRegNum::const_zero().value, gpr(rb).value] [gpr(rs), MOpRegNum::const_zero(), gpr(rb)]
}, },
#[hdl] #[hdl]
ShiftRotateMOpImm { ShiftRotateMOpImm {
@ -2296,11 +2252,7 @@ impl DecodeState<'_> {
this.output[0], this.output[0],
ShiftRotateMOp::shift_rotate( ShiftRotateMOp::shift_rotate(
MOpDestReg::new([gpr(ra)], [(MOpRegNum::POWER_ISA_CR_0_REG_NUM, rc)]), MOpDestReg::new([gpr(ra)], [(MOpRegNum::POWER_ISA_CR_0_REG_NUM, rc)]),
[ [gpr(rs), MOpRegNum::const_zero(), MOpRegNum::const_zero()],
gpr(rs).value,
MOpRegNum::const_zero().value,
MOpRegNum::const_zero().value,
],
#[hdl] #[hdl]
ShiftRotateMOpImm { ShiftRotateMOpImm {
shift_rotate_amount: HdlSome(sh.rotate_right(1)), shift_rotate_amount: HdlSome(sh.rotate_right(1)),
@ -2330,7 +2282,7 @@ impl DecodeState<'_> {
self.output[0], self.output[0],
MoveRegMOp::move_reg( MoveRegMOp::move_reg(
MOpDestReg::new([spr], []), MOpDestReg::new([spr], []),
[gpr(reg).value], [gpr(reg)],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
), ),
); );
@ -2339,7 +2291,7 @@ impl DecodeState<'_> {
self.output[0], self.output[0],
MoveRegMOp::move_reg( MoveRegMOp::move_reg(
MOpDestReg::new([gpr(reg)], []), MOpDestReg::new([gpr(reg)], []),
[spr.value], [spr],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
), ),
); );
@ -2355,7 +2307,7 @@ impl DecodeState<'_> {
self.output[0], self.output[0],
ReadSpecialMOp::read_special( ReadSpecialMOp::read_special(
MOpDestReg::new([gpr(reg)], []), MOpDestReg::new([gpr(reg)], []),
[MOpRegNum::const_zero().value; 0], [MOpRegNum::const_zero(); 0],
imm, imm,
), ),
); );
@ -2431,9 +2383,9 @@ impl DecodeState<'_> {
LogicalFlagsMOp::logical_flags( LogicalFlagsMOp::logical_flags(
MOpDestReg::new([crf(bf)], []), MOpDestReg::new([crf(bf)], []),
[ [
MOpRegNum::power_isa_xer_ca_ca32_reg().value, MOpRegNum::power_isa_xer_ca_ca32_reg(),
MOpRegNum::const_zero().value, MOpRegNum::const_zero(),
MOpRegNum::power_isa_xer_so_ov_ov32_reg().value, MOpRegNum::power_isa_xer_so_ov_ov32_reg(),
], ],
LogicalFlagsMOpImm::from_swizzle_fn::<PRegFlagsPowerISA>(|src0, src1, src2| { LogicalFlagsMOpImm::from_swizzle_fn::<PRegFlagsPowerISA>(|src0, src1, src2| {
let mut dest = PRegFlagsPowerISAView::splat(None); let mut dest = PRegFlagsPowerISAView::splat(None);

660
crates/cpu/src/instruction.rs
View file

File diff suppressed because it is too large Load diff

36
crates/cpu/src/rename_execute_retire.rs
View file

@ -6,8 +6,8 @@
use crate::{ use crate::{
config::{ config::{
CpuConfig, CpuConfig2PowOutRegNumWidth, CpuConfigFetchWidth, CpuConfigPRegNumWidth, CpuConfig, CpuConfig2PowOutRegNumWidth, CpuConfigFetchWidth, CpuConfigRobSize,
CpuConfigRobSize, CpuConfigUnitCount, PhantomConstCpuConfig, TwiceCpuConfigFetchWidth, CpuConfigUnitCount, PhantomConstCpuConfig, TwiceCpuConfigFetchWidth,
}, },
instruction::{ instruction::{
COMMON_MOP_SRC_LEN, L2RegNum, L2RegisterFileMOp, MOp, MOpDestReg, MOpRegNum, MOpTrait, COMMON_MOP_SRC_LEN, L2RegNum, L2RegisterFileMOp, MOp, MOpDestReg, MOpRegNum, MOpTrait,
@ -118,10 +118,7 @@ pub struct RetireToNextPcInterface<C: PhantomConstGet<CpuConfig>> {
#[hdl] #[hdl]
pub type RenamedMOp<C: PhantomConstGet<CpuConfig>> = pub type RenamedMOp<C: PhantomConstGet<CpuConfig>> =
crate::instruction::RenamedMOp<PRegNum<C>, CpuConfigPRegNumWidth<C>>; crate::instruction::RenamedMOp<PRegNum<C>, PRegNum<C>>;
#[hdl]
pub type RenamedSrcRegUInt<C: PhantomConstGet<CpuConfig>> = UIntType<CpuConfigPRegNumWidth<C>>;
/// Enqueues happen in program order, they are not re-ordered by out-of-order execution. /// Enqueues happen in program order, they are not re-ordered by out-of-order execution.
/// the whole `MOpInstance` is sent again in [`UnitInputsReady`] so Units can just ignore all /// the whole `MOpInstance` is sent again in [`UnitInputsReady`] so Units can just ignore all
@ -1170,7 +1167,7 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
let PRegNum::<_> { let PRegNum::<_> {
unit_num, unit_num,
unit_out_reg, unit_out_reg,
} = src_reg.cast_bits_to(PRegNum[self.config]); } = src_reg;
if Some(unit_index) == UnitNum::index_sim(&unit_num) { if Some(unit_index) == UnitNum::index_sim(&unit_num) {
allocated_regs[UnitOutRegNum::value_sim(&unit_out_reg)] = true; allocated_regs[UnitOutRegNum::value_sim(&unit_out_reg)] = true;
} }
@ -1256,13 +1253,14 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
let unit_kind = UnitMOp::kind_sim(&insn.mop); let unit_kind = UnitMOp::kind_sim(&insn.mop);
#[hdl(sim)] #[hdl(sim)]
if let MOp::TransformedMove(move_reg_mop) = &insn.mop { if let MOp::TransformedMove(move_reg_mop) = &insn.mop {
let mut src_regs = [MOpRegNum::CONST_ZERO_REG_NUM; 1]; let mut src_regs = [MOpRegNum::const_zero_sim()];
MOpTrait::for_each_src_reg_sim_ref(move_reg_mop, &mut |src_reg, index| { MOpTrait::for_each_src_reg_sim_ref(move_reg_mop, &mut |src_reg, index| {
src_regs[index] = src_reg.as_int() as u32; src_regs[index] = src_reg.clone();
}); });
let [src_reg] = src_regs; let [src_reg] = src_regs;
let renamed_reg = self.rename_table.entries[src_reg as usize].clone(); let renamed_reg =
println!("moving from {src_reg:#x} renamed: {renamed_reg:?}"); self.rename_table.entries[MOpRegNum::reg_num_sim(&src_reg) as usize].clone();
println!("moving from {src_reg:?} renamed: {renamed_reg:?}");
let unrenamed_dest_regs = let unrenamed_dest_regs =
MOpDestReg::regs_sim(MOpTrait::dest_reg_sim_ref(move_reg_mop)); MOpDestReg::regs_sim(MOpTrait::dest_reg_sim_ref(move_reg_mop));
assert!(self.rob.incomplete_back_entry.is_none()); assert!(self.rob.incomplete_back_entry.is_none());
@ -1358,19 +1356,16 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
let mop = MOpTrait::map_regs_sim( let mop = MOpTrait::map_regs_sim(
mop, mop,
&renamed_dest_reg, &renamed_dest_reg,
CpuConfigPRegNumWidth[self.config], PRegNum[self.config],
&mut |src_reg, index| { &mut |src_reg, index| {
let renamed = &self.rename_table.entries[src_reg.as_int() as usize]; let renamed = &self.rename_table.entries[MOpRegNum::reg_num_sim(&src_reg) as usize];
println!("renaming src[{index}] from {src_reg:?} to {renamed:?}"); println!("renaming src[{index}] from {src_reg:?} to {renamed:?}");
#[hdl(sim)] #[hdl(sim)]
match renamed { match renamed {
RenameTableEntry::<_>::L1(v) => v.cast_to_bits(), RenameTableEntry::<_>::L1(v) => v.clone(),
RenameTableEntry::<_>::L2(v) => { RenameTableEntry::<_>::L2(v) => {
needed_load.get_or_insert_with(|| v.clone()); needed_load.get_or_insert_with(|| v.clone());
PRegNum[self.config] PRegNum[self.config].const_zero_sim()
.const_zero()
.cast_to_bits()
.into_sim_value()
} }
} }
}, },
@ -1405,7 +1400,7 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
is_last_mop_in_insn, is_last_mop_in_insn,
mop: ReadL2RegMOp::read_l2_reg::<RenamedMOp<C>>( mop: ReadL2RegMOp::read_l2_reg::<RenamedMOp<C>>(
dest, dest,
repeat(RenamedSrcRegUInt[self.config].zero(), ConstUsize), repeat(PRegNum[self.config].const_zero_sim(), ConstUsize),
needed_load, needed_load,
), ),
}, },
@ -1494,7 +1489,6 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
let mut src_values: [_; COMMON_MOP_SRC_LEN] = let mut src_values: [_; COMMON_MOP_SRC_LEN] =
std::array::from_fn(|_| Some(zero_value.clone())); std::array::from_fn(|_| Some(zero_value.clone()));
MOpTrait::for_each_src_reg_sim_ref(&rob.mop.mop, &mut |src_reg, index| { MOpTrait::for_each_src_reg_sim_ref(&rob.mop.mop, &mut |src_reg, index| {
let src_reg = src_reg.cast_bits_to(zero_reg.ty());
#[hdl(sim)] #[hdl(sim)]
let PRegNum::<_> { let PRegNum::<_> {
unit_num, unit_num,
@ -1505,7 +1499,7 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
[UnitOutRegNum::value_sim(unit_out_reg)] [UnitOutRegNum::value_sim(unit_out_reg)]
.clone(); .clone();
} else { } else {
assert_eq!(src_reg, zero_reg); assert_eq!(*src_reg, zero_reg);
src_values[index] = Some(zeroed(PRegValue)); src_values[index] = Some(zeroed(PRegValue));
} }
}); });

96
crates/cpu/src/unit.rs
View file

@ -5,8 +5,8 @@ use crate::{
config::{CpuConfig, PhantomConstCpuConfig}, config::{CpuConfig, PhantomConstCpuConfig},
instruction::{ instruction::{
AluBranchMOp, LoadStoreMOp, MOp, MOpDestReg, MOpInto, MOpRegNum, MOpTrait, AluBranchMOp, LoadStoreMOp, MOp, MOpDestReg, MOpInto, MOpRegNum, MOpTrait,
MOpVariantVisitOps, MOpVariantVisitor, MOpVisitVariants, RenamedMOp, UnitOutRegNum, MOpVariantVisitOps, MOpVariantVisitor, MOpVisitVariants, PRegNum, RenamedMOp,
mop_enum, UnitOutRegNum, mop_enum,
}, },
register::{FlagsMode, PRegValue}, register::{FlagsMode, PRegValue},
unit::unit_base::UnitToRegAlloc, unit::unit_base::UnitToRegAlloc,
@ -28,7 +28,7 @@ macro_rules! all_units {
#[unit_kind = $UnitKind:ident] #[unit_kind = $UnitKind:ident]
#[hdl(custom_debug(sim))] #[hdl(custom_debug(sim))]
$(#[$enum_meta:meta])* $(#[$enum_meta:meta])*
$vis:vis enum $UnitMOpEnum:ident<$DestReg:ident: Type, $SrcRegWidth:ident: Size, #[MOp(get_ty = $transformed_move_op_get_ty:expr)] $TransformedMoveOp:ident: Type> { $vis:vis enum $UnitMOpEnum:ident<$DestReg:ident: Type, $SrcReg:ident: Type, #[MOp(get_ty = $transformed_move_op_get_ty:expr)] $TransformedMoveOp:ident: Type> {
$( $(
$(#[transformed_move $($transformed_move:tt)*])? $(#[transformed_move $($transformed_move:tt)*])?
#[create_dyn_unit_fn = $create_dyn_unit_fn:expr] #[create_dyn_unit_fn = $create_dyn_unit_fn:expr]
@ -87,11 +87,11 @@ macro_rules! all_units {
$(#[$enum_meta])* $(#[$enum_meta])*
$vis enum $UnitMOpEnum< $vis enum $UnitMOpEnum<
$DestReg: Type, $DestReg: Type,
$SrcRegWidth: Size, $SrcReg: Type,
#[MOp(get_ty = $transformed_move_op_get_ty)] $TransformedMoveOp: Type, #[MOp(get_ty = $transformed_move_op_get_ty)] $TransformedMoveOp: Type,
#[MOpVisitVariants] [ #[MOpVisitVariants] [
$TransformedMoveOp: MOpVisitVariants<DestReg = $DestReg, SrcRegWidth = $SrcRegWidth>, $TransformedMoveOp: MOpVisitVariants<DestReg = $DestReg, SrcReg = $SrcReg>,
$($Op: MOpVisitVariants<DestReg = $DestReg, SrcRegWidth = $SrcRegWidth>,)* $($Op: MOpVisitVariants<DestReg = $DestReg, SrcReg = $SrcReg>,)*
] ]
> { > {
$( $(
@ -101,7 +101,7 @@ macro_rules! all_units {
} }
} }
impl<$DestReg: Type, $SrcRegWidth: Size, $TransformedMoveOp: Type> $UnitMOpEnum<$DestReg, $SrcRegWidth, $TransformedMoveOp> { impl<$DestReg: Type, $SrcReg: Type, $TransformedMoveOp: Type> $UnitMOpEnum<$DestReg, $SrcReg, $TransformedMoveOp> {
#[hdl] #[hdl]
$vis fn kind(expr: impl ToExpr<Type = Self>) -> Expr<$HdlUnitKind> { $vis fn kind(expr: impl ToExpr<Type = Self>) -> Expr<$HdlUnitKind> {
#[hdl] #[hdl]
@ -164,18 +164,18 @@ macro_rules! all_units {
} }
} }
)* )*
$vis fn with_transformed_move_op_ty<T>(self, new_transformed_move_op_ty: T) -> $UnitMOpEnum<$DestReg, $SrcRegWidth, T> $vis fn with_transformed_move_op_ty<T>(self, new_transformed_move_op_ty: T) -> $UnitMOpEnum<$DestReg, $SrcReg, T>
where where
T: MOpTrait<DestReg = $DestReg, SrcRegWidth = $SrcRegWidth>, T: MOpTrait<DestReg = $DestReg, SrcReg = $SrcReg>,
$TransformedMoveOp: MOpTrait<DestReg = $DestReg, SrcRegWidth = $SrcRegWidth>, $TransformedMoveOp: MOpTrait<DestReg = $DestReg, SrcReg = $SrcReg>,
{ {
$UnitMOpEnum[self.dest_reg_ty()][self.src_reg_width()][new_transformed_move_op_ty] $UnitMOpEnum[self.dest_reg_ty()][self.src_reg_ty()][new_transformed_move_op_ty]
} }
} }
all_units! { all_units! {
@split_by_transformed_move @split_by_transformed_move
$vis enum $UnitMOpEnum<$DestReg: Type, $SrcRegWidth: Size, $TransformedMoveOp: Type> { $vis enum $UnitMOpEnum<$DestReg: Type, $SrcReg: Type, $TransformedMoveOp: Type> {
$( $(
$(#[transformed_move $($transformed_move)*])? $(#[transformed_move $($transformed_move)*])?
$Unit($Op), $Unit($Op),
@ -200,23 +200,23 @@ macro_rules! all_units {
}; };
( (
@split_by_transformed_move @split_by_transformed_move
$vis:vis enum $UnitMOpEnum:ident<$DestReg:ident: Type, $SrcRegWidth:ident: Size, $TransformedMoveOp:ident: Type> { $vis:vis enum $UnitMOpEnum:ident<$DestReg:ident: Type, $SrcReg:ident: Type, $TransformedMoveOp:ident: Type> {
$($BeforeUnit:ident($BeforeOp:ty),)* $($BeforeUnit:ident($BeforeOp:ty),)*
#[transformed_move] #[transformed_move]
$TransformedMove:ident($TransformedMoveOp2:ty), $TransformedMove:ident($TransformedMoveOp2:ty),
$($AfterUnit:ident($AfterOp:ty),)* $($AfterUnit:ident($AfterOp:ty),)*
} }
) => { ) => {
impl<$DestReg: Type, $SrcRegWidth: Size, $TransformedMoveOp: Type> $UnitMOpEnum<$DestReg, $SrcRegWidth, $TransformedMoveOp> { impl<$DestReg: Type, $SrcReg: Type, $TransformedMoveOp: Type> $UnitMOpEnum<$DestReg, $SrcReg, $TransformedMoveOp> {
#[hdl] #[hdl]
$vis fn try_with_transformed_move_op<T>( $vis fn try_with_transformed_move_op<T>(
this: impl ToExpr<Type = Self>, this: impl ToExpr<Type = Self>,
new_transformed_move_op_ty: T, new_transformed_move_op_ty: T,
connect_transformed_move_op: impl FnOnce(Expr<HdlOption<$UnitMOpEnum<$DestReg, $SrcRegWidth, T>>>, Expr<$TransformedMoveOp>), connect_transformed_move_op: impl FnOnce(Expr<HdlOption<$UnitMOpEnum<$DestReg, $SrcReg, T>>>, Expr<$TransformedMoveOp>),
) -> Expr<HdlOption<$UnitMOpEnum<$DestReg, $SrcRegWidth, T>>> ) -> Expr<HdlOption<$UnitMOpEnum<$DestReg, $SrcReg, T>>>
where where
T: MOpTrait<DestReg = $DestReg, SrcRegWidth = $SrcRegWidth>, T: MOpTrait<DestReg = $DestReg, SrcReg = $SrcReg>,
$TransformedMoveOp: MOpTrait<DestReg = $DestReg, SrcRegWidth = $SrcRegWidth>, $TransformedMoveOp: MOpTrait<DestReg = $DestReg, SrcReg = $SrcReg>,
{ {
let this = this.to_expr(); let this = this.to_expr();
let new_ty = this.ty().with_transformed_move_op_ty(new_transformed_move_op_ty); let new_ty = this.ty().with_transformed_move_op_ty(new_transformed_move_op_ty);
@ -237,11 +237,11 @@ macro_rules! all_units {
$vis fn try_with_transformed_move_op_sim<T, E>( $vis fn try_with_transformed_move_op_sim<T, E>(
this: impl ToSimValue<Type = Self>, this: impl ToSimValue<Type = Self>,
new_transformed_move_op_ty: T, new_transformed_move_op_ty: T,
f: impl FnOnce(SimValue<$TransformedMoveOp>) -> Result<SimValue<$UnitMOpEnum<$DestReg, $SrcRegWidth, T>>, E>, f: impl FnOnce(SimValue<$TransformedMoveOp>) -> Result<SimValue<$UnitMOpEnum<$DestReg, $SrcReg, T>>, E>,
) -> Result<SimValue<$UnitMOpEnum<$DestReg, $SrcRegWidth, T>>, E> ) -> Result<SimValue<$UnitMOpEnum<$DestReg, $SrcReg, T>>, E>
where where
T: MOpTrait<DestReg = $DestReg, SrcRegWidth = $SrcRegWidth>, T: MOpTrait<DestReg = $DestReg, SrcReg = $SrcReg>,
$TransformedMoveOp: MOpTrait<DestReg = $DestReg, SrcRegWidth = $SrcRegWidth>, $TransformedMoveOp: MOpTrait<DestReg = $DestReg, SrcReg = $SrcReg>,
{ {
#![allow(unreachable_patterns)] #![allow(unreachable_patterns)]
let this = this.into_sim_value(); let this = this.into_sim_value();
@ -263,11 +263,11 @@ macro_rules! all_units {
$vis fn with_transformed_move_op_sim<T>( $vis fn with_transformed_move_op_sim<T>(
this: impl ToSimValue<Type = Self>, this: impl ToSimValue<Type = Self>,
new_transformed_move_op_ty: T, new_transformed_move_op_ty: T,
f: impl FnOnce(SimValue<$TransformedMoveOp>) -> SimValue<$UnitMOpEnum<$DestReg, $SrcRegWidth, T>>, f: impl FnOnce(SimValue<$TransformedMoveOp>) -> SimValue<$UnitMOpEnum<$DestReg, $SrcReg, T>>,
) -> SimValue<$UnitMOpEnum<$DestReg, $SrcRegWidth, T>> ) -> SimValue<$UnitMOpEnum<$DestReg, $SrcReg, T>>
where where
T: MOpTrait<DestReg = $DestReg, SrcRegWidth = $SrcRegWidth>, T: MOpTrait<DestReg = $DestReg, SrcReg = $SrcReg>,
$TransformedMoveOp: MOpTrait<DestReg = $DestReg, SrcRegWidth = $SrcRegWidth>, $TransformedMoveOp: MOpTrait<DestReg = $DestReg, SrcReg = $SrcReg>,
{ {
let Ok::<_, std::convert::Infallible>(retval) = Self::try_with_transformed_move_op_sim(this, new_transformed_move_op_ty, move |v| Ok(f(v))); let Ok::<_, std::convert::Infallible>(retval) = Self::try_with_transformed_move_op_sim(this, new_transformed_move_op_ty, move |v| Ok(f(v)));
retval retval
@ -277,7 +277,7 @@ macro_rules! all_units {
const _: () = { const _: () = {
#[hdl] #[hdl]
type $DestReg = MOpDestReg; type $DestReg = MOpDestReg;
type $SrcRegWidth = ConstUsize<{ MOpRegNum::WIDTH }>; type $SrcReg = MOpRegNum;
$(impl MOpInto<MOp> for $BeforeOp { $(impl MOpInto<MOp> for $BeforeOp {
fn mop_into_ty(self) -> MOp { fn mop_into_ty(self) -> MOp {
@ -298,21 +298,21 @@ macro_rules! all_units {
})* })*
}; };
$(impl<$DestReg: Type, $SrcRegWidth: Size> MOpInto<RenamedMOp<$DestReg, $SrcRegWidth>> for $BeforeOp { $(impl<$DestReg: Type, $SrcReg: Type> MOpInto<RenamedMOp<$DestReg, $SrcReg>> for $BeforeOp {
fn mop_into_ty(self) -> RenamedMOp<$DestReg, $SrcRegWidth> { fn mop_into_ty(self) -> RenamedMOp<$DestReg, $SrcReg> {
RenamedMOp[MOpTrait::dest_reg_ty(self)][MOpTrait::src_reg_width(self)] RenamedMOp[MOpTrait::dest_reg_ty(self)][MOpTrait::src_reg_ty(self)]
} }
fn mop_into(this: Expr<Self>) -> Expr<RenamedMOp<$DestReg, $SrcRegWidth>> { fn mop_into(this: Expr<Self>) -> Expr<RenamedMOp<$DestReg, $SrcReg>> {
MOpInto::<RenamedMOp<$DestReg, $SrcRegWidth>>::mop_into_ty(this.ty()).$BeforeUnit(this) MOpInto::<RenamedMOp<$DestReg, $SrcReg>>::mop_into_ty(this.ty()).$BeforeUnit(this)
} }
})* })*
$(impl<$DestReg: Type, $SrcRegWidth: Size> MOpInto<RenamedMOp<$DestReg, $SrcRegWidth>> for $AfterOp { $(impl<$DestReg: Type, $SrcReg: Type> MOpInto<RenamedMOp<$DestReg, $SrcReg>> for $AfterOp {
fn mop_into_ty(self) -> RenamedMOp<$DestReg, $SrcRegWidth> { fn mop_into_ty(self) -> RenamedMOp<$DestReg, $SrcReg> {
RenamedMOp[MOpTrait::dest_reg_ty(self)][MOpTrait::src_reg_width(self)] RenamedMOp[MOpTrait::dest_reg_ty(self)][MOpTrait::src_reg_ty(self)]
} }
fn mop_into(this: Expr<Self>) -> Expr<RenamedMOp<$DestReg, $SrcRegWidth>> { fn mop_into(this: Expr<Self>) -> Expr<RenamedMOp<$DestReg, $SrcReg>> {
MOpInto::<RenamedMOp<$DestReg, $SrcRegWidth>>::mop_into_ty(this.ty()).$AfterUnit(this) MOpInto::<RenamedMOp<$DestReg, $SrcReg>>::mop_into_ty(this.ty()).$AfterUnit(this)
} }
})* })*
}; };
@ -324,21 +324,21 @@ all_units! {
#[hdl(custom_debug(sim))] #[hdl(custom_debug(sim))]
pub enum UnitMOp< pub enum UnitMOp<
DestReg: Type, DestReg: Type,
SrcRegWidth: Size, SrcReg: Type,
#[MOp(get_ty = |this: UnitMOp<DestReg, SrcRegWidth, TransformedMoveOp>, new_dest_reg, new_src_reg_width| { #[MOp(get_ty = |this: UnitMOp<DestReg, SrcReg, TransformedMoveOp>, new_dest_reg, new_src_reg| {
this.TransformedMove.mapped_ty(new_dest_reg, new_src_reg_width) this.TransformedMove.mapped_ty(new_dest_reg, new_src_reg)
})] TransformedMoveOp: Type })] TransformedMoveOp: Type
> { > {
#[create_dyn_unit_fn = |config, unit_index| alu_branch::AluBranch::new(config, unit_index).to_dyn()] #[create_dyn_unit_fn = |config, unit_index| alu_branch::AluBranch::new(config, unit_index).to_dyn()]
#[extract(alu_branch_mop, alu_branch_mop_sim, alu_branch_mop_sim_ref, alu_branch_mop_sim_mut)] #[extract(alu_branch_mop, alu_branch_mop_sim, alu_branch_mop_sim_ref, alu_branch_mop_sim_mut)]
AluBranch(AluBranchMOp<DestReg, SrcRegWidth>), AluBranch(AluBranchMOp<DestReg, SrcReg>),
#[transformed_move] #[transformed_move]
#[create_dyn_unit_fn = |config, unit_index| todo!()] #[create_dyn_unit_fn = |config, unit_index| todo!()]
#[extract(transformed_move_mop, transformed_move_mop_sim, transformed_move_mop_sim_ref, transformed_move_mop_sim_mut)] #[extract(transformed_move_mop, transformed_move_mop_sim, transformed_move_mop_sim_ref, transformed_move_mop_sim_mut)]
TransformedMove(TransformedMoveOp), TransformedMove(TransformedMoveOp),
#[create_dyn_unit_fn = |config, unit_index| todo!()] #[create_dyn_unit_fn = |config, unit_index| todo!()]
#[extract(load_store_mop, load_store_mop_sim, load_store_mop_sim_ref, load_store_mop_sim_mut)] #[extract(load_store_mop, load_store_mop_sim, load_store_mop_sim_ref, load_store_mop_sim_mut)]
LoadStore(LoadStoreMOp<DestReg, SrcRegWidth>), LoadStore(LoadStoreMOp<DestReg, SrcReg>),
} }
} }
@ -408,7 +408,9 @@ pub trait UnitTrait:
fn extract_mop( fn extract_mop(
&self, &self,
mop: Expr<RenamedMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, DynSize>>, mop: Expr<
RenamedMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, PRegNum<PhantomConst<CpuConfig>>>,
>,
) -> Expr<HdlOption<Self::MOp>>; ) -> Expr<HdlOption<Self::MOp>>;
fn module(&self) -> Interned<Module<Self::Type>>; fn module(&self) -> Interned<Module<Self::Type>>;
@ -466,7 +468,9 @@ impl UnitTrait for DynUnit {
fn extract_mop( fn extract_mop(
&self, &self,
mop: Expr<RenamedMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, DynSize>>, mop: Expr<
RenamedMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, PRegNum<PhantomConst<CpuConfig>>>,
>,
) -> Expr<HdlOption<Self::MOp>> { ) -> Expr<HdlOption<Self::MOp>> {
self.unit.extract_mop(mop) self.unit.extract_mop(mop)
} }
@ -521,7 +525,9 @@ impl<T: UnitTrait + Clone + std::hash::Hash + Eq> UnitTrait for DynUnitWrapper<T
fn extract_mop( fn extract_mop(
&self, &self,
mop: Expr<RenamedMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, DynSize>>, mop: Expr<
RenamedMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, PRegNum<PhantomConst<CpuConfig>>>,
>,
) -> Expr<HdlOption<Self::MOp>> { ) -> Expr<HdlOption<Self::MOp>> {
Expr::from_enum(Expr::as_enum(self.0.extract_mop(mop))) Expr::from_enum(Expr::as_enum(self.0.extract_mop(mop)))
} }

70
crates/cpu/src/unit/alu_branch.rs
View file

@ -5,8 +5,8 @@ use crate::{
config::CpuConfig, config::CpuConfig,
instruction::{ instruction::{
AddSubMOp, AluBranchMOp, AluCommonMOp, BranchMOp, COMMON_MOP_SRC_LEN, CommonMOpDefaultImm, AddSubMOp, AluBranchMOp, AluCommonMOp, BranchMOp, COMMON_MOP_SRC_LEN, CommonMOpDefaultImm,
CompareMOp, LogicalFlagsMOp, LogicalMOp, MOpTrait, OutputIntegerMode, ReadSpecialMOp, CompareMOp, LogicalFlagsMOp, LogicalMOp, MOpTrait, OutputIntegerMode, PRegNum,
RenamedMOp, ShiftRotateMOp, UnitOutRegNum, ReadSpecialMOp, RenamedMOp, ShiftRotateMOp, UnitOutRegNum,
}, },
register::{ register::{
FlagsMode, PRegFlagsPowerISA, PRegFlagsPowerISAView, PRegFlagsViewTrait, PRegFlagsX86, FlagsMode, PRegFlagsPowerISA, PRegFlagsPowerISAView, PRegFlagsViewTrait, PRegFlagsX86,
@ -25,7 +25,13 @@ use std::{collections::HashMap, ops::RangeTo};
#[hdl] #[hdl]
fn add_sub<SrcCount: KnownSize>( fn add_sub<SrcCount: KnownSize>(
mop: Expr<AddSubMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, DynSize, SrcCount>>, mop: Expr<
AddSubMOp<
UnitOutRegNum<PhantomConst<CpuConfig>>,
PRegNum<PhantomConst<CpuConfig>>,
SrcCount,
>,
>,
pc: Expr<UInt<64>>, pc: Expr<UInt<64>>,
flags_mode: Expr<FlagsMode>, flags_mode: Expr<FlagsMode>,
src_values: Expr<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>, src_values: Expr<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>,
@ -242,7 +248,9 @@ fn add_sub<SrcCount: KnownSize>(
#[hdl] #[hdl]
fn logical_flags( fn logical_flags(
mop: Expr<LogicalFlagsMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, DynSize>>, mop: Expr<
LogicalFlagsMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, PRegNum<PhantomConst<CpuConfig>>>,
>,
flags_mode: Expr<FlagsMode>, flags_mode: Expr<FlagsMode>,
src_values: Expr<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>, src_values: Expr<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>,
) -> Expr<UnitResultCompleted<()>> { ) -> Expr<UnitResultCompleted<()>> {
@ -256,7 +264,13 @@ fn logical_flags(
#[hdl] #[hdl]
fn logical( fn logical(
mop: Expr<LogicalMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, DynSize, ConstUsize<2>>>, mop: Expr<
LogicalMOp<
UnitOutRegNum<PhantomConst<CpuConfig>>,
PRegNum<PhantomConst<CpuConfig>>,
ConstUsize<2>,
>,
>,
flags_mode: Expr<FlagsMode>, flags_mode: Expr<FlagsMode>,
src_values: Expr<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>, src_values: Expr<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>,
) -> Expr<UnitResultCompleted<()>> { ) -> Expr<UnitResultCompleted<()>> {
@ -270,7 +284,13 @@ fn logical(
#[hdl] #[hdl]
fn logical_i( fn logical_i(
mop: Expr<LogicalMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, DynSize, ConstUsize<1>>>, mop: Expr<
LogicalMOp<
UnitOutRegNum<PhantomConst<CpuConfig>>,
PRegNum<PhantomConst<CpuConfig>>,
ConstUsize<1>,
>,
>,
flags_mode: Expr<FlagsMode>, flags_mode: Expr<FlagsMode>,
src_values: Expr<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>, src_values: Expr<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>,
) -> Expr<UnitResultCompleted<()>> { ) -> Expr<UnitResultCompleted<()>> {
@ -284,7 +304,9 @@ fn logical_i(
#[hdl] #[hdl]
fn shift_rotate( fn shift_rotate(
mop: Expr<ShiftRotateMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, DynSize>>, mop: Expr<
ShiftRotateMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, PRegNum<PhantomConst<CpuConfig>>>,
>,
flags_mode: Expr<FlagsMode>, flags_mode: Expr<FlagsMode>,
src_values: Expr<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>, src_values: Expr<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>,
) -> Expr<UnitResultCompleted<()>> { ) -> Expr<UnitResultCompleted<()>> {
@ -298,7 +320,13 @@ fn shift_rotate(
#[hdl] #[hdl]
fn compare<SrcCount: KnownSize>( fn compare<SrcCount: KnownSize>(
mop: Expr<CompareMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, DynSize, SrcCount>>, mop: Expr<
CompareMOp<
UnitOutRegNum<PhantomConst<CpuConfig>>,
PRegNum<PhantomConst<CpuConfig>>,
SrcCount,
>,
>,
flags_mode: Expr<FlagsMode>, flags_mode: Expr<FlagsMode>,
src_values: Expr<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>, src_values: Expr<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>,
) -> Expr<UnitResultCompleted<()>> { ) -> Expr<UnitResultCompleted<()>> {
@ -312,7 +340,13 @@ fn compare<SrcCount: KnownSize>(
#[hdl] #[hdl]
fn branch<SrcCount: KnownSize>( fn branch<SrcCount: KnownSize>(
mop: Expr<BranchMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, DynSize, SrcCount>>, mop: Expr<
BranchMOp<
UnitOutRegNum<PhantomConst<CpuConfig>>,
PRegNum<PhantomConst<CpuConfig>>,
SrcCount,
>,
>,
pc: Expr<UInt<64>>, pc: Expr<UInt<64>>,
flags_mode: Expr<FlagsMode>, flags_mode: Expr<FlagsMode>,
src_values: Expr<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>, src_values: Expr<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>,
@ -327,7 +361,9 @@ fn branch<SrcCount: KnownSize>(
#[hdl] #[hdl]
fn read_special( fn read_special(
mop: Expr<ReadSpecialMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, DynSize>>, mop: Expr<
ReadSpecialMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, PRegNum<PhantomConst<CpuConfig>>>,
>,
pc: Expr<UInt<64>>, pc: Expr<UInt<64>>,
flags_mode: Expr<FlagsMode>, flags_mode: Expr<FlagsMode>,
src_values: Expr<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>, src_values: Expr<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>,
@ -347,12 +383,9 @@ pub fn alu_branch(config: PhantomConst<CpuConfig>, unit_index: usize) {
#[hdl] #[hdl]
let unit_to_reg_alloc: UnitToRegAlloc< let unit_to_reg_alloc: UnitToRegAlloc<
PhantomConst<CpuConfig>, PhantomConst<CpuConfig>,
AluBranchMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, DynSize>, AluBranchMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, PRegNum<PhantomConst<CpuConfig>>>,
(), (),
> = m.output( > = m.output(UnitToRegAlloc[config][AluBranchMOp[UnitOutRegNum[config]][PRegNum[config]]][()]);
UnitToRegAlloc[config][AluBranchMOp[UnitOutRegNum[config]][config.get().p_reg_num_width()]]
[()],
);
#[hdl] #[hdl]
let global_state: GlobalState = m.input(); let global_state: GlobalState = m.input();
@ -592,7 +625,8 @@ impl AluBranch {
impl UnitTrait for AluBranch { impl UnitTrait for AluBranch {
type Type = alu_branch; type Type = alu_branch;
type ExtraOut = (); type ExtraOut = ();
type MOp = AluBranchMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, DynSize>; type MOp =
AluBranchMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, PRegNum<PhantomConst<CpuConfig>>>;
fn ty(&self) -> Self::Type { fn ty(&self) -> Self::Type {
self.module.io_ty() self.module.io_ty()
@ -612,7 +646,9 @@ impl UnitTrait for AluBranch {
fn extract_mop( fn extract_mop(
&self, &self,
mop: Expr<RenamedMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, DynSize>>, mop: Expr<
RenamedMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, PRegNum<PhantomConst<CpuConfig>>>,
>,
) -> Expr<HdlOption<Self::MOp>> { ) -> Expr<HdlOption<Self::MOp>> {
UnitMOp::alu_branch_mop(mop) UnitMOp::alu_branch_mop(mop)
} }

25
crates/cpu/src/unit/unit_base.rs
View file

@ -234,7 +234,11 @@ impl InFlightOpsSummary<DynSize> {
#[hdl_module] #[hdl_module]
pub fn unit_base< pub fn unit_base<
MOp: Type + MOpTrait<DestReg = UnitOutRegNum<PhantomConst<CpuConfig>>, SrcRegWidth = DynSize>, MOp: Type
+ MOpTrait<
DestReg = UnitOutRegNum<PhantomConst<CpuConfig>>,
SrcReg = PRegNum<PhantomConst<CpuConfig>>,
>,
ExtraOut: Type, ExtraOut: Type,
>( >(
config: PhantomConst<CpuConfig>, config: PhantomConst<CpuConfig>,
@ -282,7 +286,7 @@ pub fn unit_base<
let read_src_regs = wire(mop_ty.src_regs_ty()); let read_src_regs = wire(mop_ty.src_regs_ty());
connect( connect(
read_src_regs, read_src_regs,
repeat(PRegNum[config].const_zero().cast_to_bits(), ConstUsize), repeat(PRegNum[config].const_zero(), ConstUsize),
); );
#[hdl] #[hdl]
let read_src_values = wire(); let read_src_values = wire();
@ -291,7 +295,7 @@ pub fn unit_base<
let input_src_regs = wire(mop_ty.src_regs_ty()); let input_src_regs = wire(mop_ty.src_regs_ty());
connect( connect(
input_src_regs, input_src_regs,
repeat(PRegNum[config].const_zero().cast_to_bits(), ConstUsize), repeat(PRegNum[config].const_zero(), ConstUsize),
); );
#[hdl] #[hdl]
let input_src_regs_valid = wire(); let input_src_regs_valid = wire();
@ -317,7 +321,7 @@ pub fn unit_base<
for src_index in 0..COMMON_MOP_SRC_LEN { for src_index in 0..COMMON_MOP_SRC_LEN {
let read_port = unit_output_regs.new_read_port(); let read_port = unit_output_regs.new_read_port();
let p_reg_num = read_src_regs[src_index].cast_bits_to(PRegNum[config]); let p_reg_num = read_src_regs[src_index];
connect_any(read_port.addr, p_reg_num.unit_out_reg.value); connect_any(read_port.addr, p_reg_num.unit_out_reg.value);
connect(read_port.en, false); connect(read_port.en, false);
connect(read_port.clk, cd.clk); connect(read_port.clk, cd.clk);
@ -330,7 +334,7 @@ pub fn unit_base<
for src_index in 0..COMMON_MOP_SRC_LEN { for src_index in 0..COMMON_MOP_SRC_LEN {
let read_port = unit_output_regs_valid[unit_index].new_read_port(); let read_port = unit_output_regs_valid[unit_index].new_read_port();
let p_reg_num = input_src_regs[src_index].cast_bits_to(PRegNum[config]); let p_reg_num = input_src_regs[src_index];
connect_any(read_port.addr, p_reg_num.unit_out_reg.value); connect_any(read_port.addr, p_reg_num.unit_out_reg.value);
connect(read_port.en, false); connect(read_port.en, false);
connect(read_port.clk, cd.clk); connect(read_port.clk, cd.clk);
@ -367,7 +371,7 @@ pub fn unit_base<
}; };
for src_index in 0..COMMON_MOP_SRC_LEN { for src_index in 0..COMMON_MOP_SRC_LEN {
#[hdl] #[hdl]
if input_src_regs[src_index].cmp_eq(p_reg_num.cast_to_bits()) { if input_src_regs[src_index].cmp_eq(p_reg_num) {
connect(input_src_regs_valid[src_index], true); connect(input_src_regs_valid[src_index], true);
} }
} }
@ -420,7 +424,7 @@ pub fn unit_base<
let input_mop_src_regs = wire(mop_ty.src_regs_ty()); let input_mop_src_regs = wire(mop_ty.src_regs_ty());
connect( connect(
input_mop_src_regs, input_mop_src_regs,
repeat(PRegNum[config].const_zero().cast_to_bits(), ConstUsize), repeat(PRegNum[config].const_zero(), ConstUsize),
); );
MOp::connect_src_regs(mop, input_mop_src_regs); MOp::connect_src_regs(mop, input_mop_src_regs);
let src_ready_flags = wire_with_loc( let src_ready_flags = wire_with_loc(
@ -490,10 +494,7 @@ pub fn unit_base<
SourceLocation::caller(), SourceLocation::caller(),
mop_ty.src_regs_ty(), mop_ty.src_regs_ty(),
); );
connect( connect(src_regs, repeat(PRegNum[config].const_zero(), ConstUsize));
src_regs,
repeat(PRegNum[config].const_zero().cast_to_bits(), ConstUsize),
);
MOp::connect_src_regs(mop, src_regs); MOp::connect_src_regs(mop, src_regs);
#[hdl] #[hdl]
@ -522,7 +523,7 @@ pub fn unit_base<
}; };
for src_index in 0..COMMON_MOP_SRC_LEN { for src_index in 0..COMMON_MOP_SRC_LEN {
#[hdl] #[hdl]
if p_reg_num.cast_to_bits().cmp_eq(src_regs[src_index]) { if p_reg_num.cmp_eq(src_regs[src_index]) {
connect( connect(
in_flight_op_next_src_ready_flags[in_flight_op_index][src_index], in_flight_op_next_src_ready_flags[in_flight_op_index][src_index],
true, true,

78
crates/cpu/tests/rename_execute_retire.rs
View file

@ -3,8 +3,8 @@
use cpu::{ use cpu::{
config::{ config::{
CpuConfig, CpuConfigFetchWidth, CpuConfigMaxUnitMaxInFlight, CpuConfigPRegNumWidth, CpuConfig, CpuConfigFetchWidth, CpuConfigMaxUnitMaxInFlight, PhantomConstCpuConfig,
PhantomConstCpuConfig, UnitConfig, UnitConfig,
}, },
instruction::{ instruction::{
AddSubMOp, AluBranchMOp, AluCommonMOp, BranchMOp, COMMON_MOP_SRC_LEN, CommonMOp, AddSubMOp, AluBranchMOp, AluCommonMOp, BranchMOp, COMMON_MOP_SRC_LEN, CommonMOp,
@ -246,7 +246,7 @@ impl InsnsBuilder {
move |labels| { move |labels| {
[BranchMOp::branch_i( [BranchMOp::branch_i(
MOpDestReg::new([], []), MOpDestReg::new([], []),
MOpRegNum::const_zero().value, [MOpRegNum::const_zero(); 2],
labels[target.0] labels[target.0]
.pc() .pc()
.wrapping_sub(pc) .wrapping_sub(pc)
@ -264,7 +264,7 @@ impl InsnsBuilder {
format!("blr"), format!("blr"),
[BranchMOp::branch_i( [BranchMOp::branch_i(
MOpDestReg::new([], []), MOpDestReg::new([], []),
MOpRegNum::power_isa_lr_reg().value, [MOpRegNum::const_zero(), MOpRegNum::power_isa_lr_reg()],
0i8.cast_to_static::<SInt<_>>(), 0i8.cast_to_static::<SInt<_>>(),
false, false,
false, false,
@ -281,9 +281,9 @@ impl InsnsBuilder {
[BranchMOp::branch_cond_ctr( [BranchMOp::branch_cond_ctr(
MOpDestReg::new([], []), MOpDestReg::new([], []),
[ [
MOpRegNum::power_isa_cr_reg_imm(0).value, MOpRegNum::power_isa_cr_reg_imm(0),
MOpRegNum::const_zero().value, MOpRegNum::const_zero(),
MOpRegNum::const_zero().value, MOpRegNum::const_zero(),
], ],
labels[target.0] labels[target.0]
.pc() .pc()
@ -307,7 +307,7 @@ impl InsnsBuilder {
move |labels| { move |labels| {
[BranchMOp::branch_i( [BranchMOp::branch_i(
MOpDestReg::new([MOpRegNum::power_isa_lr_reg()], []), MOpDestReg::new([MOpRegNum::power_isa_lr_reg()], []),
MOpRegNum::const_zero().value, [MOpRegNum::const_zero(); 2],
labels[target.0] labels[target.0]
.pc() .pc()
.wrapping_sub(pc) .wrapping_sub(pc)
@ -326,9 +326,9 @@ impl InsnsBuilder {
[AddSubMOp::add_sub( [AddSubMOp::add_sub(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(dest)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(dest)], &[]),
[ [
MOpRegNum::power_isa_gpr_reg_imm(src1).value, MOpRegNum::power_isa_gpr_reg_imm(src1),
MOpRegNum::power_isa_gpr_reg_imm(src2).value, MOpRegNum::power_isa_gpr_reg_imm(src2),
MOpRegNum::const_zero().value, MOpRegNum::const_zero(),
], ],
0i8.cast_to_static::<SInt<_>>(), 0i8.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -346,8 +346,8 @@ impl InsnsBuilder {
[AddSubMOp::add_sub_i( [AddSubMOp::add_sub_i(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(dest)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(dest)], &[]),
[ [
MOpRegNum::power_isa_gpr_or_zero_reg_imm(src).value, MOpRegNum::power_isa_gpr_or_zero_reg_imm(src),
MOpRegNum::const_zero().value, MOpRegNum::const_zero(),
], ],
imm.cast_to_static::<SInt<_>>(), imm.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -364,7 +364,7 @@ impl InsnsBuilder {
format!("cmpldi {dest}, {src}, {imm:#x}"), format!("cmpldi {dest}, {src}, {imm:#x}"),
[CompareMOp::compare_i( [CompareMOp::compare_i(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(dest)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(dest)], &[]),
[MOpRegNum::power_isa_gpr_reg_imm(src).value], [MOpRegNum::power_isa_gpr_reg_imm(src)],
imm.cast_to_static::<SInt<_>>(), imm.cast_to_static::<SInt<_>>(),
CompareMode.U64(), CompareMode.U64(),
)], )],
@ -378,8 +378,8 @@ impl InsnsBuilder {
AddSubMOp::add_sub_i( AddSubMOp::add_sub_i(
MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]), MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]),
[ [
MOpRegNum::power_isa_gpr_or_zero_reg_imm(src).value, MOpRegNum::power_isa_gpr_or_zero_reg_imm(src),
MOpRegNum::const_zero().value, MOpRegNum::const_zero(),
], ],
disp.cast_to_static::<SInt<_>>(), disp.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -390,7 +390,7 @@ impl InsnsBuilder {
), ),
LoadMOp::load( LoadMOp::load(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(dest)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(dest)], &[]),
[MOpRegNum::power_isa_temp_reg().value], [MOpRegNum::power_isa_temp_reg()],
LoadStoreWidth.Width64Bit(), LoadStoreWidth.Width64Bit(),
LoadStoreConversion.ZeroExt(), LoadStoreConversion.ZeroExt(),
), ),
@ -405,8 +405,8 @@ impl InsnsBuilder {
AddSubMOp::add_sub_i( AddSubMOp::add_sub_i(
MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]), MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]),
[ [
MOpRegNum::power_isa_gpr_or_zero_reg_imm(addr_src).value, MOpRegNum::power_isa_gpr_or_zero_reg_imm(addr_src),
MOpRegNum::const_zero().value, MOpRegNum::const_zero(),
], ],
disp.cast_to_static::<SInt<_>>(), disp.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -418,8 +418,8 @@ impl InsnsBuilder {
StoreMOp::store( StoreMOp::store(
MOpDestReg::new_sim(&[], &[]), MOpDestReg::new_sim(&[], &[]),
[ [
MOpRegNum::power_isa_temp_reg().value, MOpRegNum::power_isa_temp_reg(),
MOpRegNum::power_isa_gpr_reg_imm(value_src).value, MOpRegNum::power_isa_gpr_reg_imm(value_src),
], ],
LoadStoreWidth.Width64Bit(), LoadStoreWidth.Width64Bit(),
LoadStoreConversion.ZeroExt(), LoadStoreConversion.ZeroExt(),
@ -433,7 +433,7 @@ impl InsnsBuilder {
format!("mflr {dest}"), format!("mflr {dest}"),
[MoveRegMOp::move_reg( [MoveRegMOp::move_reg(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(dest)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(dest)], &[]),
[MOpRegNum::power_isa_lr_reg().value], [MOpRegNum::power_isa_lr_reg()],
0i8.cast_to_static::<SInt<_>>(), 0i8.cast_to_static::<SInt<_>>(),
)], )],
)); ));
@ -444,7 +444,7 @@ impl InsnsBuilder {
format!("mtlr {src}"), format!("mtlr {src}"),
[MoveRegMOp::move_reg( [MoveRegMOp::move_reg(
MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_LR_REG_NUM], &[]), MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_LR_REG_NUM], &[]),
[MOpRegNum::power_isa_gpr_reg_imm(src).value], [MOpRegNum::power_isa_gpr_reg_imm(src)],
0i8.cast_to_static::<SInt<_>>(), 0i8.cast_to_static::<SInt<_>>(),
)], )],
)); ));
@ -455,7 +455,7 @@ impl InsnsBuilder {
format!("mr {dest}, {src}"), format!("mr {dest}, {src}"),
[MoveRegMOp::move_reg( [MoveRegMOp::move_reg(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(dest)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(dest)], &[]),
[MOpRegNum::power_isa_gpr_reg_imm(src).value], [MOpRegNum::power_isa_gpr_reg_imm(src)],
0i8.cast_to_static::<SInt<_>>(), 0i8.cast_to_static::<SInt<_>>(),
)], )],
)); ));
@ -579,7 +579,7 @@ impl BrPredState {
} }
fn predict_branch<SrcCount: KnownSize>( fn predict_branch<SrcCount: KnownSize>(
&mut self, &mut self,
mop: &SimValue<BranchMOp<MOpDestReg, ConstUsize<{ MOpRegNum::WIDTH }>, SrcCount>>, mop: &SimValue<BranchMOp<MOpDestReg, MOpRegNum, SrcCount>>,
branch_pc: u64, branch_pc: u64,
fallthrough_pc: u64, fallthrough_pc: u64,
) -> u64 { ) -> u64 {
@ -590,7 +590,7 @@ impl BrPredState {
} }
let mut src_regs = [MOpRegNum::CONST_ZERO_REG_NUM; 3]; let mut src_regs = [MOpRegNum::CONST_ZERO_REG_NUM; 3];
MOpTrait::for_each_src_reg_sim_ref(mop, &mut |reg, index| { MOpTrait::for_each_src_reg_sim_ref(mop, &mut |reg, index| {
src_regs[index] = reg.cast_to_static::<UInt<32>>().as_int(); src_regs[index] = MOpRegNum::reg_num_sim(reg);
}); });
if src_regs[1] != MOpRegNum::CONST_ZERO_REG_NUM { if src_regs[1] != MOpRegNum::CONST_ZERO_REG_NUM {
// indirect branch -- this test doesn't implement predicting them, so just use the fallthrough_pc // indirect branch -- this test doesn't implement predicting them, so just use the fallthrough_pc
@ -1268,7 +1268,7 @@ impl MockMemory {
#[hdl] #[hdl]
fn run_mop<C: PhantomConstCpuConfig>( fn run_mop<C: PhantomConstCpuConfig>(
&mut self, &mut self,
mop: &SimValue<MOpInstance<LoadStoreMOp<PRegNum<C>, CpuConfigPRegNumWidth<C>>>>, mop: &SimValue<MOpInstance<LoadStoreMOp<PRegNum<C>, PRegNum<C>>>>,
src_values: &[SimValue<PRegValue>; COMMON_MOP_SRC_LEN], src_values: &[SimValue<PRegValue>; COMMON_MOP_SRC_LEN],
is_speculative: bool, is_speculative: bool,
) -> Result<SimValue<PRegValue>, AddressCantBeSpeculativelyAccessed> { ) -> Result<SimValue<PRegValue>, AddressCantBeSpeculativelyAccessed> {
@ -1389,7 +1389,7 @@ trait MockExecutionStateTrait: Default {
fn run_add_sub<C: PhantomConstCpuConfig, SrcCount: KnownSize>( fn run_add_sub<C: PhantomConstCpuConfig, SrcCount: KnownSize>(
&mut self, &mut self,
pc: u64, pc: u64,
mop: &SimValue<AddSubMOp<PRegNum<C>, CpuConfigPRegNumWidth<C>, SrcCount>>, mop: &SimValue<AddSubMOp<PRegNum<C>, PRegNum<C>, SrcCount>>,
src_values: &[SimValue<PRegValue>; COMMON_MOP_SRC_LEN], src_values: &[SimValue<PRegValue>; COMMON_MOP_SRC_LEN],
) -> SimValue<PRegValue> { ) -> SimValue<PRegValue> {
#[hdl(sim)] #[hdl(sim)]
@ -1453,7 +1453,7 @@ trait MockExecutionStateTrait: Default {
#[hdl] #[hdl]
fn run_compare<C: PhantomConstCpuConfig, SrcCount: KnownSize>( fn run_compare<C: PhantomConstCpuConfig, SrcCount: KnownSize>(
&mut self, &mut self,
mop: &SimValue<CompareMOp<PRegNum<C>, CpuConfigPRegNumWidth<C>, SrcCount>>, mop: &SimValue<CompareMOp<PRegNum<C>, PRegNum<C>, SrcCount>>,
src_values: &[SimValue<PRegValue>; COMMON_MOP_SRC_LEN], src_values: &[SimValue<PRegValue>; COMMON_MOP_SRC_LEN],
) -> SimValue<PRegValue> { ) -> SimValue<PRegValue> {
#[hdl(sim)] #[hdl(sim)]
@ -1513,7 +1513,7 @@ trait MockExecutionStateTrait: Default {
pc: u64, pc: u64,
fallthrough_pc: u64, fallthrough_pc: u64,
predicted_next_pc: u64, predicted_next_pc: u64,
mop: &SimValue<BranchMOp<PRegNum<C>, CpuConfigPRegNumWidth<C>, SrcCount>>, mop: &SimValue<BranchMOp<PRegNum<C>, PRegNum<C>, SrcCount>>,
src_values: &[SimValue<PRegValue>; COMMON_MOP_SRC_LEN], src_values: &[SimValue<PRegValue>; COMMON_MOP_SRC_LEN],
config: C, config: C,
) -> ( ) -> (
@ -1539,12 +1539,14 @@ trait MockExecutionStateTrait: Default {
imm, imm,
} = common; } = common;
let [src0, src1, src2] = src_values; let [src0, src1, src2] = src_values;
let has_src0 = src.as_ref().get(0).is_some_and(|src0| { let has_src0 = src
src0.cast_bits_to(PRegNum[config]) != PRegNum[config].const_zero().into_sim_value() .as_ref()
}); .get(0)
let has_src2 = src.as_ref().get(2).is_some_and(|src2| { .is_some_and(|src0| *src0 != PRegNum[config].const_zero_sim());
src2.cast_bits_to(PRegNum[config]) != PRegNum[config].const_zero().into_sim_value() let has_src2 = src
}); .as_ref()
.get(2)
.is_some_and(|src2| *src2 != PRegNum[config].const_zero_sim());
let src2_cond = if has_src2 { let src2_cond = if has_src2 {
let _ = invert_src2_eq_zero; let _ = invert_src2_eq_zero;
let _ = src2; let _ = src2;
@ -2236,7 +2238,7 @@ fn mock_unit<#[hdl(skip)] E: MockExecutionStateTrait>(
#[hdl(no_static)] #[hdl(no_static)]
struct MockLoadStoreOpDebugState<C: PhantomConstGet<CpuConfig>> { struct MockLoadStoreOpDebugState<C: PhantomConstGet<CpuConfig>> {
mop: MOpInstance<LoadStoreMOp<PRegNum<C>, CpuConfigPRegNumWidth<C>>>, mop: MOpInstance<LoadStoreMOp<PRegNum<C>, PRegNum<C>>>,
is_speculative: Bool, is_speculative: Bool,
src_values: HdlOption<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>, src_values: HdlOption<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>,
dest_value: HdlOption<PRegValue>, dest_value: HdlOption<PRegValue>,
@ -2248,7 +2250,7 @@ struct MockLoadStoreOpDebugState<C: PhantomConstGet<CpuConfig>> {
#[derive(Debug)] #[derive(Debug)]
struct MockLoadStoreOp<C: PhantomConstCpuConfig> { struct MockLoadStoreOp<C: PhantomConstCpuConfig> {
mop: SimValue<MOpInstance<LoadStoreMOp<PRegNum<C>, CpuConfigPRegNumWidth<C>>>>, mop: SimValue<MOpInstance<LoadStoreMOp<PRegNum<C>, PRegNum<C>>>>,
is_speculative: bool, is_speculative: bool,
src_values: Option<[SimValue<PRegValue>; COMMON_MOP_SRC_LEN]>, src_values: Option<[SimValue<PRegValue>; COMMON_MOP_SRC_LEN]>,
dest_value: Option<SimValue<PRegValue>>, dest_value: Option<SimValue<PRegValue>>,

49238
crates/cpu/tests/simple_power_isa_decoder/expected/decode_one_insn.vcd generated
View file

File diff suppressed because it is too large Load diff

84
crates/cpu/tests/simple_power_isa_decoder/test_cases/branch.rs
View file

@ -15,7 +15,7 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
None, None,
BranchMOp::branch_i( BranchMOp::branch_i(
MOpDestReg::new_sim(&[], &[]), MOpDestReg::new_sim(&[], &[]),
MOpRegNum::const_zero().value, [MOpRegNum::const_zero(); 2],
0x345678.cast_to_static::<SInt<_>>(), 0x345678.cast_to_static::<SInt<_>>(),
true, true,
false, false,
@ -28,7 +28,7 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
None, None,
BranchMOp::branch_i( BranchMOp::branch_i(
MOpDestReg::new_sim(&[], &[]), MOpDestReg::new_sim(&[], &[]),
MOpRegNum::const_zero().value, [MOpRegNum::const_zero(); 2],
0x345678.cast_to_static::<SInt<_>>(), 0x345678.cast_to_static::<SInt<_>>(),
false, false,
false, false,
@ -41,7 +41,7 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
None, None,
BranchMOp::branch_i( BranchMOp::branch_i(
MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_LR_REG_NUM], &[]), MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_LR_REG_NUM], &[]),
MOpRegNum::const_zero().value, [MOpRegNum::const_zero(); 2],
0x345678.cast_to_static::<SInt<_>>(), 0x345678.cast_to_static::<SInt<_>>(),
true, true,
true, true,
@ -54,7 +54,7 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
None, None,
BranchMOp::branch_i( BranchMOp::branch_i(
MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_LR_REG_NUM], &[]), MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_LR_REG_NUM], &[]),
MOpRegNum::const_zero().value, [MOpRegNum::const_zero(); 2],
0x345678.cast_to_static::<SInt<_>>(), 0x345678.cast_to_static::<SInt<_>>(),
false, false,
true, true,
@ -74,10 +74,7 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
[ [
AddSubMOp::add_sub_i::<MOp>( AddSubMOp::add_sub_i::<MOp>(
MOpDestReg::new([MOpRegNum::power_isa_ctr_reg()], []), MOpDestReg::new([MOpRegNum::power_isa_ctr_reg()], []),
[ [MOpRegNum::power_isa_ctr_reg(), MOpRegNum::const_zero()],
MOpRegNum::power_isa_ctr_reg().value,
MOpRegNum::const_zero().value,
],
(-1).cast_to_static::<SInt<_>>(), (-1).cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
false, false,
@ -143,9 +140,9 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
BranchMOp::branch_cond_ctr( BranchMOp::branch_cond_ctr(
$dest, $dest,
[ [
MOpRegNum::power_isa_cr_reg_imm(0).value, MOpRegNum::power_isa_cr_reg_imm(0),
$src1, $src1,
MOpRegNum::power_isa_ctr_reg().value, MOpRegNum::power_isa_ctr_reg(),
], ],
$imm.cast_to_static::<SInt<_>>(), $imm.cast_to_static::<SInt<_>>(),
true, true,
@ -163,9 +160,9 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
BranchMOp::branch_cond_ctr( BranchMOp::branch_cond_ctr(
$dest, $dest,
[ [
MOpRegNum::power_isa_cr_reg_imm(0).value, MOpRegNum::power_isa_cr_reg_imm(0),
$src1, $src1,
MOpRegNum::power_isa_ctr_reg().value, MOpRegNum::power_isa_ctr_reg(),
], ],
$imm.cast_to_static::<SInt<_>>(), $imm.cast_to_static::<SInt<_>>(),
true, true,
@ -183,9 +180,9 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
BranchMOp::branch_cond_ctr( BranchMOp::branch_cond_ctr(
$dest, $dest,
[ [
MOpRegNum::power_isa_cr_reg_imm(0).value, MOpRegNum::power_isa_cr_reg_imm(0),
$src1, $src1,
MOpRegNum::power_isa_ctr_reg().value, MOpRegNum::power_isa_ctr_reg(),
], ],
$imm.cast_to_static::<SInt<_>>(), $imm.cast_to_static::<SInt<_>>(),
true, true,
@ -203,9 +200,9 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
BranchMOp::branch_cond_ctr( BranchMOp::branch_cond_ctr(
$dest, $dest,
[ [
MOpRegNum::power_isa_cr_reg_imm(0).value, MOpRegNum::power_isa_cr_reg_imm(0),
$src1, $src1,
MOpRegNum::power_isa_ctr_reg().value, MOpRegNum::power_isa_ctr_reg(),
], ],
$imm.cast_to_static::<SInt<_>>(), $imm.cast_to_static::<SInt<_>>(),
true, true,
@ -223,9 +220,9 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
BranchMOp::branch_cond_ctr( BranchMOp::branch_cond_ctr(
$dest, $dest,
[ [
MOpRegNum::power_isa_cr_reg_imm(2).value, MOpRegNum::power_isa_cr_reg_imm(2),
$src1, $src1,
MOpRegNum::power_isa_ctr_reg().value, MOpRegNum::power_isa_ctr_reg(),
], ],
$imm.cast_to_static::<SInt<_>>(), $imm.cast_to_static::<SInt<_>>(),
true, true,
@ -243,9 +240,9 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
BranchMOp::branch_cond_ctr( BranchMOp::branch_cond_ctr(
$dest, $dest,
[ [
MOpRegNum::power_isa_cr_reg_imm(0).value, MOpRegNum::power_isa_cr_reg_imm(0),
$src1, $src1,
MOpRegNum::power_isa_ctr_reg().value, MOpRegNum::power_isa_ctr_reg(),
], ],
$imm.cast_to_static::<SInt<_>>(), $imm.cast_to_static::<SInt<_>>(),
true, true,
@ -264,9 +261,9 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
BranchMOp::branch_cond_ctr( BranchMOp::branch_cond_ctr(
$dest, $dest,
[ [
MOpRegNum::power_isa_cr_reg_imm(0).value, MOpRegNum::power_isa_cr_reg_imm(0),
$src1, $src1,
MOpRegNum::const_zero().value, MOpRegNum::const_zero(),
], ],
$imm.cast_to_static::<SInt<_>>(), $imm.cast_to_static::<SInt<_>>(),
true, true,
@ -285,9 +282,9 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
BranchMOp::branch_cond_ctr( BranchMOp::branch_cond_ctr(
$dest, $dest,
[ [
MOpRegNum::power_isa_cr_reg_imm(0).value, MOpRegNum::power_isa_cr_reg_imm(0),
$src1, $src1,
MOpRegNum::power_isa_ctr_reg().value, MOpRegNum::power_isa_ctr_reg(),
], ],
$imm.cast_to_static::<SInt<_>>(), $imm.cast_to_static::<SInt<_>>(),
false, false,
@ -305,9 +302,9 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
BranchMOp::branch_cond_ctr( BranchMOp::branch_cond_ctr(
$dest, $dest,
[ [
MOpRegNum::power_isa_cr_reg_imm(0).value, MOpRegNum::power_isa_cr_reg_imm(0),
$src1, $src1,
MOpRegNum::power_isa_ctr_reg().value, MOpRegNum::power_isa_ctr_reg(),
], ],
$imm.cast_to_static::<SInt<_>>(), $imm.cast_to_static::<SInt<_>>(),
false, false,
@ -326,9 +323,9 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
BranchMOp::branch_cond_ctr( BranchMOp::branch_cond_ctr(
$dest, $dest,
[ [
MOpRegNum::power_isa_cr_reg_imm(0).value, MOpRegNum::power_isa_cr_reg_imm(0),
$src1, $src1,
MOpRegNum::const_zero().value, MOpRegNum::const_zero(),
], ],
$imm.cast_to_static::<SInt<_>>(), $imm.cast_to_static::<SInt<_>>(),
false, false,
@ -346,8 +343,11 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
None, None,
BranchMOp::branch_ctr( BranchMOp::branch_ctr(
$dest, $dest,
$src1, [
MOpRegNum::power_isa_ctr_reg().value, MOpRegNum::const_zero(),
$src1,
MOpRegNum::power_isa_ctr_reg(),
],
$imm.cast_to_static::<SInt<_>>(), $imm.cast_to_static::<SInt<_>>(),
true, true,
$pc_relative, $pc_relative,
@ -361,8 +361,11 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
None, None,
BranchMOp::branch_ctr( BranchMOp::branch_ctr(
$dest, $dest,
$src1, [
MOpRegNum::power_isa_ctr_reg().value, MOpRegNum::const_zero(),
$src1,
MOpRegNum::power_isa_ctr_reg(),
],
$imm.cast_to_static::<SInt<_>>(), $imm.cast_to_static::<SInt<_>>(),
false, false,
$pc_relative, $pc_relative,
@ -377,7 +380,7 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
None, None,
BranchMOp::branch_i( BranchMOp::branch_i(
$dest, $dest,
$src1, [MOpRegNum::const_zero(), $src1],
$imm.cast_to_static::<SInt<_>>(), $imm.cast_to_static::<SInt<_>>(),
$pc_relative, $pc_relative,
$lk, $lk,
@ -392,7 +395,7 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
asm_last_arg = "0x1234"; asm_last_arg = "0x1234";
imm = 0x1234; imm = 0x1234;
encoding = 0x40001234; encoding = 0x40001234;
src1 = MOpRegNum::const_zero().value; src1 = MOpRegNum::const_zero();
pc_relative = true; pc_relative = true;
is_ret = false; is_ret = false;
} }
@ -402,7 +405,7 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
asm_last_arg = "0x1234"; asm_last_arg = "0x1234";
imm = 0x1234; imm = 0x1234;
encoding = 0x40001236; encoding = 0x40001236;
src1 = MOpRegNum::const_zero().value; src1 = MOpRegNum::const_zero();
pc_relative = false; pc_relative = false;
is_ret = false; is_ret = false;
} }
@ -412,7 +415,7 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
asm_last_arg = "0"; asm_last_arg = "0";
imm = 0; imm = 0;
encoding = 0x4c000020; encoding = 0x4c000020;
src1 = MOpRegNum::power_isa_lr_reg().value; src1 = MOpRegNum::power_isa_lr_reg();
pc_relative = false; pc_relative = false;
is_ret = true; is_ret = true;
} }
@ -422,7 +425,7 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
asm_last_arg = "0"; asm_last_arg = "0";
imm = 0; imm = 0;
encoding = 0x4c000420; encoding = 0x4c000420;
src1 = MOpRegNum::power_isa_ctr_reg().value; src1 = MOpRegNum::power_isa_ctr_reg();
pc_relative = false; pc_relative = false;
is_ret = false; is_ret = false;
} }
@ -434,8 +437,11 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
None, None,
BranchMOp::branch_ctr( BranchMOp::branch_ctr(
MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_LR_REG_NUM], &[]), MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_LR_REG_NUM], &[]),
MOpRegNum::power_isa_tar_reg().value, [
MOpRegNum::power_isa_ctr_reg().value, MOpRegNum::const_zero(),
MOpRegNum::power_isa_tar_reg(),
MOpRegNum::power_isa_ctr_reg(),
],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
false, false,
false, false,

20
crates/cpu/tests/simple_power_isa_decoder/test_cases/condition_register.rs
View file

@ -23,9 +23,9 @@ pub fn test_cases_book_i_2_5_condition_register(retval: &mut Vec<TestCase>) {
LogicalFlagsMOp::logical_flags( LogicalFlagsMOp::logical_flags(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
[ [
MOpRegNum::power_isa_cr_reg_imm(1).value, MOpRegNum::power_isa_cr_reg_imm(1),
MOpRegNum::power_isa_cr_reg_imm(5).value, MOpRegNum::power_isa_cr_reg_imm(5),
MOpRegNum::power_isa_cr_reg_imm(3).value, MOpRegNum::power_isa_cr_reg_imm(3),
], ],
LogicalFlagsMOpImm::from_swizzle_fn::<PRegFlagsPowerISA>(|src0, src1, src2| { LogicalFlagsMOpImm::from_swizzle_fn::<PRegFlagsPowerISA>(|src0, src1, src2| {
let mut dest = src2.map(|v| Some(v.into())); let mut dest = src2.map(|v| Some(v.into()));
@ -42,9 +42,9 @@ pub fn test_cases_book_i_2_5_condition_register(retval: &mut Vec<TestCase>) {
LogicalFlagsMOp::logical_flags( LogicalFlagsMOp::logical_flags(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(0)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(0)], &[]),
[ [
MOpRegNum::power_isa_cr_reg_imm(0).value, MOpRegNum::power_isa_cr_reg_imm(0),
MOpRegNum::power_isa_cr_reg_imm(0).value, MOpRegNum::power_isa_cr_reg_imm(0),
MOpRegNum::power_isa_cr_reg_imm(0).value, MOpRegNum::power_isa_cr_reg_imm(0),
], ],
LogicalFlagsMOpImm::from_swizzle_fn::<PRegFlagsPowerISA>(|src0, src1, src2| { LogicalFlagsMOpImm::from_swizzle_fn::<PRegFlagsPowerISA>(|src0, src1, src2| {
let mut dest = src2.map(|v| Some(v.into())); let mut dest = src2.map(|v| Some(v.into()));
@ -61,9 +61,9 @@ pub fn test_cases_book_i_2_5_condition_register(retval: &mut Vec<TestCase>) {
LogicalFlagsMOp::logical_flags( LogicalFlagsMOp::logical_flags(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(0)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(0)], &[]),
[ [
MOpRegNum::power_isa_cr_reg_imm(0).value, MOpRegNum::power_isa_cr_reg_imm(0),
MOpRegNum::power_isa_cr_reg_imm(0).value, MOpRegNum::power_isa_cr_reg_imm(0),
MOpRegNum::power_isa_cr_reg_imm(0).value, MOpRegNum::power_isa_cr_reg_imm(0),
], ],
LogicalFlagsMOpImm::from_swizzle_fn::<PRegFlagsPowerISA>(|src0, src1, src2| { LogicalFlagsMOpImm::from_swizzle_fn::<PRegFlagsPowerISA>(|src0, src1, src2| {
let mut dest = src2.map(|v| Some(v.into())); let mut dest = src2.map(|v| Some(v.into()));
@ -91,7 +91,7 @@ pub fn test_cases_book_i_2_5_condition_register(retval: &mut Vec<TestCase>) {
None, None,
MoveRegMOp::move_reg( MoveRegMOp::move_reg(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num($dest)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num($dest)], &[]),
[MOpRegNum::power_isa_cr_reg_imm($src).value], [MOpRegNum::power_isa_cr_reg_imm($src)],
0i8.cast_to_static::<SInt<_>>(), 0i8.cast_to_static::<SInt<_>>(),
), ),
)); ));

95
crates/cpu/tests/simple_power_isa_decoder/test_cases/fixed_point_arithmetic.rs
View file

@ -13,10 +13,7 @@ pub fn test_cases_book_i_3_3_9_fixed_point_arithmetic(retval: &mut Vec<TestCase>
None, None,
AddSubMOp::add_sub_i( AddSubMOp::add_sub_i(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
[ [MOpRegNum::power_isa_gpr_reg_imm(4), MOpRegNum::const_zero()],
MOpRegNum::power_isa_gpr_reg_imm(4).value,
MOpRegNum::const_zero().value,
],
0x1234.cast_to_static::<SInt<_>>(), 0x1234.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
false, false,
@ -31,10 +28,7 @@ pub fn test_cases_book_i_3_3_9_fixed_point_arithmetic(retval: &mut Vec<TestCase>
Some(0x38646789), Some(0x38646789),
AddSubMOp::add_sub_i( AddSubMOp::add_sub_i(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
[ [MOpRegNum::power_isa_gpr_reg_imm(4), MOpRegNum::const_zero()],
MOpRegNum::power_isa_gpr_reg_imm(4).value,
MOpRegNum::const_zero().value,
],
0x123456789i64.cast_to_static::<SInt<_>>(), 0x123456789i64.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
false, false,
@ -49,7 +43,7 @@ pub fn test_cases_book_i_3_3_9_fixed_point_arithmetic(retval: &mut Vec<TestCase>
Some(0x38606789), Some(0x38606789),
AddSubMOp::add_sub_i( AddSubMOp::add_sub_i(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
[MOpRegNum::const_zero().value, MOpRegNum::const_zero().value], [MOpRegNum::const_zero(), MOpRegNum::const_zero()],
0x123456789i64.cast_to_static::<SInt<_>>(), 0x123456789i64.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
false, false,
@ -64,10 +58,7 @@ pub fn test_cases_book_i_3_3_9_fixed_point_arithmetic(retval: &mut Vec<TestCase>
None, None,
AddSubMOp::add_sub_i( AddSubMOp::add_sub_i(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
[ [MOpRegNum::power_isa_gpr_reg_imm(4), MOpRegNum::const_zero()],
MOpRegNum::power_isa_gpr_reg_imm(4).value,
MOpRegNum::const_zero().value,
],
0x12340000.cast_to_static::<SInt<_>>(), 0x12340000.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
false, false,
@ -82,7 +73,7 @@ pub fn test_cases_book_i_3_3_9_fixed_point_arithmetic(retval: &mut Vec<TestCase>
None, None,
AddSubMOp::add_sub_i( AddSubMOp::add_sub_i(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
[MOpRegNum::const_zero().value; _], [MOpRegNum::const_zero(); _],
0x12340004.cast_to_static::<SInt<_>>(), 0x12340004.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
false, false,
@ -101,9 +92,9 @@ pub fn test_cases_book_i_3_3_9_fixed_point_arithmetic(retval: &mut Vec<TestCase>
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM], &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
), ),
[ [
MOpRegNum::power_isa_gpr_reg_imm(4).value, MOpRegNum::power_isa_gpr_reg_imm(4),
MOpRegNum::power_isa_gpr_reg_imm(5).value, MOpRegNum::power_isa_gpr_reg_imm(5),
MOpRegNum::const_zero().value, MOpRegNum::const_zero(),
], ],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -125,10 +116,7 @@ pub fn test_cases_book_i_3_3_9_fixed_point_arithmetic(retval: &mut Vec<TestCase>
], ],
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM], &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
), ),
[ [MOpRegNum::power_isa_gpr_reg_imm(4), MOpRegNum::const_zero()],
MOpRegNum::power_isa_gpr_reg_imm(4).value,
MOpRegNum::const_zero().value,
],
0x1234.cast_to_static::<SInt<_>>(), 0x1234.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
false, false,
@ -147,9 +135,9 @@ pub fn test_cases_book_i_3_3_9_fixed_point_arithmetic(retval: &mut Vec<TestCase>
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM], &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
), ),
[ [
MOpRegNum::power_isa_gpr_reg_imm(4).value, MOpRegNum::power_isa_gpr_reg_imm(4),
MOpRegNum::power_isa_gpr_reg_imm(5).value, MOpRegNum::power_isa_gpr_reg_imm(5),
MOpRegNum::const_zero().value, MOpRegNum::const_zero(),
], ],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -171,10 +159,7 @@ pub fn test_cases_book_i_3_3_9_fixed_point_arithmetic(retval: &mut Vec<TestCase>
], ],
&[], &[],
), ),
[ [MOpRegNum::power_isa_gpr_reg_imm(4), MOpRegNum::const_zero()],
MOpRegNum::power_isa_gpr_reg_imm(4).value,
MOpRegNum::const_zero().value,
],
0x1234.cast_to_static::<SInt<_>>(), 0x1234.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
true, true,
@ -196,9 +181,9 @@ pub fn test_cases_book_i_3_3_9_fixed_point_arithmetic(retval: &mut Vec<TestCase>
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM], &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
), ),
[ [
MOpRegNum::power_isa_gpr_reg_imm(4).value, MOpRegNum::power_isa_gpr_reg_imm(4),
MOpRegNum::power_isa_gpr_reg_imm(5).value, MOpRegNum::power_isa_gpr_reg_imm(5),
MOpRegNum::const_zero().value, MOpRegNum::const_zero(),
], ],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -221,9 +206,9 @@ pub fn test_cases_book_i_3_3_9_fixed_point_arithmetic(retval: &mut Vec<TestCase>
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM], &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
), ),
[ [
MOpRegNum::power_isa_gpr_reg_imm(4).value, MOpRegNum::power_isa_gpr_reg_imm(4),
MOpRegNum::power_isa_gpr_reg_imm(5).value, MOpRegNum::power_isa_gpr_reg_imm(5),
MOpRegNum::const_zero().value, MOpRegNum::const_zero(),
], ],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -246,9 +231,9 @@ pub fn test_cases_book_i_3_3_9_fixed_point_arithmetic(retval: &mut Vec<TestCase>
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM], &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
), ),
[ [
MOpRegNum::power_isa_gpr_reg_imm(4).value, MOpRegNum::power_isa_gpr_reg_imm(4),
MOpRegNum::power_isa_xer_ca_ca32_reg().value, MOpRegNum::power_isa_xer_ca_ca32_reg(),
MOpRegNum::power_isa_gpr_reg_imm(5).value, MOpRegNum::power_isa_gpr_reg_imm(5),
], ],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -271,9 +256,9 @@ pub fn test_cases_book_i_3_3_9_fixed_point_arithmetic(retval: &mut Vec<TestCase>
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM], &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
), ),
[ [
MOpRegNum::power_isa_gpr_reg_imm(4).value, MOpRegNum::power_isa_gpr_reg_imm(4),
MOpRegNum::power_isa_xer_ca_ca32_reg().value, MOpRegNum::power_isa_xer_ca_ca32_reg(),
MOpRegNum::power_isa_gpr_reg_imm(5).value, MOpRegNum::power_isa_gpr_reg_imm(5),
], ],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -296,9 +281,9 @@ pub fn test_cases_book_i_3_3_9_fixed_point_arithmetic(retval: &mut Vec<TestCase>
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM], &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
), ),
[ [
MOpRegNum::power_isa_gpr_reg_imm(4).value, MOpRegNum::power_isa_gpr_reg_imm(4),
MOpRegNum::power_isa_xer_ca_ca32_reg().value, MOpRegNum::power_isa_xer_ca_ca32_reg(),
MOpRegNum::const_zero().value, MOpRegNum::const_zero(),
], ],
(-1i8).cast_to_static::<SInt<_>>(), (-1i8).cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -321,9 +306,9 @@ pub fn test_cases_book_i_3_3_9_fixed_point_arithmetic(retval: &mut Vec<TestCase>
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM], &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
), ),
[ [
MOpRegNum::power_isa_gpr_reg_imm(4).value, MOpRegNum::power_isa_gpr_reg_imm(4),
MOpRegNum::power_isa_xer_ca_ca32_reg().value, MOpRegNum::power_isa_xer_ca_ca32_reg(),
MOpRegNum::const_zero().value, MOpRegNum::const_zero(),
], ],
(-1i8).cast_to_static::<SInt<_>>(), (-1i8).cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -346,9 +331,9 @@ pub fn test_cases_book_i_3_3_9_fixed_point_arithmetic(retval: &mut Vec<TestCase>
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM], &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
), ),
[ [
MOpRegNum::power_isa_gpr_reg_imm(4).value, MOpRegNum::power_isa_gpr_reg_imm(4),
MOpRegNum::power_isa_xer_ca_ca32_reg().value, MOpRegNum::power_isa_xer_ca_ca32_reg(),
MOpRegNum::const_zero().value, MOpRegNum::const_zero(),
], ],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -371,9 +356,9 @@ pub fn test_cases_book_i_3_3_9_fixed_point_arithmetic(retval: &mut Vec<TestCase>
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM], &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
), ),
[ [
MOpRegNum::power_isa_gpr_reg_imm(4).value, MOpRegNum::power_isa_gpr_reg_imm(4),
MOpRegNum::power_isa_xer_ca_ca32_reg().value, MOpRegNum::power_isa_xer_ca_ca32_reg(),
MOpRegNum::const_zero().value, MOpRegNum::const_zero(),
], ],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -393,9 +378,9 @@ pub fn test_cases_book_i_3_3_9_fixed_point_arithmetic(retval: &mut Vec<TestCase>
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM], &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
), ),
[ [
MOpRegNum::power_isa_gpr_reg_imm(4).value, MOpRegNum::power_isa_gpr_reg_imm(4),
MOpRegNum::const_zero().value, MOpRegNum::const_zero(),
MOpRegNum::const_zero().value, MOpRegNum::const_zero(),
], ],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),

36
crates/cpu/tests/simple_power_isa_decoder/test_cases/fixed_point_compare.rs
View file

@ -13,7 +13,7 @@ pub fn test_cases_book_i_3_3_10_fixed_point_compare(retval: &mut Vec<TestCase>)
None, None,
CompareMOp::compare_i( CompareMOp::compare_i(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
[MOpRegNum::power_isa_gpr_reg_imm(4).value], [MOpRegNum::power_isa_gpr_reg_imm(4)],
0x1234.cast_to_static::<SInt<_>>(), 0x1234.cast_to_static::<SInt<_>>(),
CompareMode.S32(), CompareMode.S32(),
), ),
@ -24,7 +24,7 @@ pub fn test_cases_book_i_3_3_10_fixed_point_compare(retval: &mut Vec<TestCase>)
None, None,
CompareMOp::compare_i( CompareMOp::compare_i(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
[MOpRegNum::power_isa_gpr_reg_imm(4).value], [MOpRegNum::power_isa_gpr_reg_imm(4)],
(0x89abu16 as i16).cast_to_static::<SInt<_>>(), (0x89abu16 as i16).cast_to_static::<SInt<_>>(),
CompareMode.S64(), CompareMode.S64(),
), ),
@ -36,8 +36,8 @@ pub fn test_cases_book_i_3_3_10_fixed_point_compare(retval: &mut Vec<TestCase>)
CompareMOp::compare( CompareMOp::compare(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
[ [
MOpRegNum::power_isa_gpr_reg_imm(4).value, MOpRegNum::power_isa_gpr_reg_imm(4),
MOpRegNum::power_isa_gpr_reg_imm(5).value, MOpRegNum::power_isa_gpr_reg_imm(5),
], ],
CompareMode.S32(), CompareMode.S32(),
), ),
@ -49,8 +49,8 @@ pub fn test_cases_book_i_3_3_10_fixed_point_compare(retval: &mut Vec<TestCase>)
CompareMOp::compare( CompareMOp::compare(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
[ [
MOpRegNum::power_isa_gpr_reg_imm(4).value, MOpRegNum::power_isa_gpr_reg_imm(4),
MOpRegNum::power_isa_gpr_reg_imm(5).value, MOpRegNum::power_isa_gpr_reg_imm(5),
], ],
CompareMode.S64(), CompareMode.S64(),
), ),
@ -61,7 +61,7 @@ pub fn test_cases_book_i_3_3_10_fixed_point_compare(retval: &mut Vec<TestCase>)
None, None,
CompareMOp::compare_i( CompareMOp::compare_i(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
[MOpRegNum::power_isa_gpr_reg_imm(4).value], [MOpRegNum::power_isa_gpr_reg_imm(4)],
0x1234.cast_to_static::<SInt<_>>(), 0x1234.cast_to_static::<SInt<_>>(),
CompareMode.U32(), CompareMode.U32(),
), ),
@ -72,7 +72,7 @@ pub fn test_cases_book_i_3_3_10_fixed_point_compare(retval: &mut Vec<TestCase>)
None, None,
CompareMOp::compare_i( CompareMOp::compare_i(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
[MOpRegNum::power_isa_gpr_reg_imm(4).value], [MOpRegNum::power_isa_gpr_reg_imm(4)],
0x89ab.cast_to_static::<SInt<_>>(), 0x89ab.cast_to_static::<SInt<_>>(),
CompareMode.U64(), CompareMode.U64(),
), ),
@ -84,8 +84,8 @@ pub fn test_cases_book_i_3_3_10_fixed_point_compare(retval: &mut Vec<TestCase>)
CompareMOp::compare( CompareMOp::compare(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
[ [
MOpRegNum::power_isa_gpr_reg_imm(4).value, MOpRegNum::power_isa_gpr_reg_imm(4),
MOpRegNum::power_isa_gpr_reg_imm(5).value, MOpRegNum::power_isa_gpr_reg_imm(5),
], ],
CompareMode.U32(), CompareMode.U32(),
), ),
@ -97,8 +97,8 @@ pub fn test_cases_book_i_3_3_10_fixed_point_compare(retval: &mut Vec<TestCase>)
CompareMOp::compare( CompareMOp::compare(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
[ [
MOpRegNum::power_isa_gpr_reg_imm(4).value, MOpRegNum::power_isa_gpr_reg_imm(4),
MOpRegNum::power_isa_gpr_reg_imm(5).value, MOpRegNum::power_isa_gpr_reg_imm(5),
], ],
CompareMode.U64(), CompareMode.U64(),
), ),
@ -110,8 +110,8 @@ pub fn test_cases_book_i_3_3_10_fixed_point_compare(retval: &mut Vec<TestCase>)
CompareMOp::compare( CompareMOp::compare(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
[ [
MOpRegNum::power_isa_gpr_reg_imm(4).value, MOpRegNum::power_isa_gpr_reg_imm(4),
MOpRegNum::power_isa_gpr_reg_imm(5).value, MOpRegNum::power_isa_gpr_reg_imm(5),
], ],
CompareMode.CmpRBOne(), CompareMode.CmpRBOne(),
), ),
@ -123,8 +123,8 @@ pub fn test_cases_book_i_3_3_10_fixed_point_compare(retval: &mut Vec<TestCase>)
CompareMOp::compare( CompareMOp::compare(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
[ [
MOpRegNum::power_isa_gpr_reg_imm(4).value, MOpRegNum::power_isa_gpr_reg_imm(4),
MOpRegNum::power_isa_gpr_reg_imm(5).value, MOpRegNum::power_isa_gpr_reg_imm(5),
], ],
CompareMode.CmpRBTwo(), CompareMode.CmpRBTwo(),
), ),
@ -136,8 +136,8 @@ pub fn test_cases_book_i_3_3_10_fixed_point_compare(retval: &mut Vec<TestCase>)
CompareMOp::compare( CompareMOp::compare(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
[ [
MOpRegNum::power_isa_gpr_reg_imm(4).value, MOpRegNum::power_isa_gpr_reg_imm(4),
MOpRegNum::power_isa_gpr_reg_imm(5).value, MOpRegNum::power_isa_gpr_reg_imm(5),
], ],
CompareMode.CmpEqB(), CompareMode.CmpEqB(),
), ),

36
crates/cpu/tests/simple_power_isa_decoder/test_cases/fixed_point_load.rs
View file

@ -26,11 +26,11 @@ pub fn test_cases_book_i_3_3_2_fixed_point_load(retval: &mut Vec<TestCase>) {
MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]), MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]),
[ [
if $r != 0 || $ra == 0 { if $r != 0 || $ra == 0 {
MOpRegNum::const_zero().value MOpRegNum::const_zero()
} else { } else {
MOpRegNum::power_isa_gpr_reg_imm($ra).value MOpRegNum::power_isa_gpr_reg_imm($ra)
}, },
MOpRegNum::const_zero().value, MOpRegNum::const_zero(),
], ],
($disp as i64).cast_to_static::<SInt<_>>(), ($disp as i64).cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -41,7 +41,7 @@ pub fn test_cases_book_i_3_3_2_fixed_point_load(retval: &mut Vec<TestCase>) {
), ),
LoadMOp::load( LoadMOp::load(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[]),
[MOpRegNum::power_isa_temp_reg().value], [MOpRegNum::power_isa_temp_reg()],
LoadStoreWidth.$width(), LoadStoreWidth.$width(),
LoadStoreConversion.$conversion(), LoadStoreConversion.$conversion(),
), ),
@ -65,11 +65,11 @@ pub fn test_cases_book_i_3_3_2_fixed_point_load(retval: &mut Vec<TestCase>) {
MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]), MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]),
[ [
if $ra == 0 { if $ra == 0 {
MOpRegNum::const_zero().value MOpRegNum::const_zero()
} else { } else {
MOpRegNum::power_isa_gpr_reg_imm($ra).value MOpRegNum::power_isa_gpr_reg_imm($ra)
}, },
MOpRegNum::const_zero().value, MOpRegNum::const_zero(),
], ],
($disp as i64).cast_to_static::<SInt<_>>(), ($disp as i64).cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -80,7 +80,7 @@ pub fn test_cases_book_i_3_3_2_fixed_point_load(retval: &mut Vec<TestCase>) {
), ),
LoadMOp::load( LoadMOp::load(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[]),
[MOpRegNum::power_isa_temp_reg().value], [MOpRegNum::power_isa_temp_reg()],
LoadStoreWidth.$width(), LoadStoreWidth.$width(),
LoadStoreConversion.$conversion(), LoadStoreConversion.$conversion(),
), ),
@ -103,8 +103,8 @@ pub fn test_cases_book_i_3_3_2_fixed_point_load(retval: &mut Vec<TestCase>) {
AddSubMOp::add_sub_i( AddSubMOp::add_sub_i(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($ra)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($ra)], &[]),
[ [
MOpRegNum::power_isa_gpr_reg_imm($ra).value, MOpRegNum::power_isa_gpr_reg_imm($ra),
MOpRegNum::const_zero().value, MOpRegNum::const_zero(),
], ],
($disp as i64).cast_to_static::<SInt<_>>(), ($disp as i64).cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -115,7 +115,7 @@ pub fn test_cases_book_i_3_3_2_fixed_point_load(retval: &mut Vec<TestCase>) {
), ),
LoadMOp::load( LoadMOp::load(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[]),
[MOpRegNum::power_isa_gpr_reg_imm($ra).value], [MOpRegNum::power_isa_gpr_reg_imm($ra)],
LoadStoreWidth.$width(), LoadStoreWidth.$width(),
LoadStoreConversion.$conversion(), LoadStoreConversion.$conversion(),
), ),
@ -139,11 +139,11 @@ pub fn test_cases_book_i_3_3_2_fixed_point_load(retval: &mut Vec<TestCase>) {
MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]), MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]),
[ [
if $ra == 0 { if $ra == 0 {
MOpRegNum::const_zero().value MOpRegNum::const_zero()
} else { } else {
MOpRegNum::power_isa_gpr_reg_imm($ra).value MOpRegNum::power_isa_gpr_reg_imm($ra)
}, },
MOpRegNum::power_isa_gpr_reg_imm($rb).value, MOpRegNum::power_isa_gpr_reg_imm($rb),
], ],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -154,7 +154,7 @@ pub fn test_cases_book_i_3_3_2_fixed_point_load(retval: &mut Vec<TestCase>) {
), ),
LoadMOp::load( LoadMOp::load(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[]),
[MOpRegNum::power_isa_temp_reg().value], [MOpRegNum::power_isa_temp_reg()],
LoadStoreWidth.$width(), LoadStoreWidth.$width(),
LoadStoreConversion.$conversion(), LoadStoreConversion.$conversion(),
), ),
@ -177,8 +177,8 @@ pub fn test_cases_book_i_3_3_2_fixed_point_load(retval: &mut Vec<TestCase>) {
AddSubMOp::add_sub_i( AddSubMOp::add_sub_i(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($ra)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($ra)], &[]),
[ [
MOpRegNum::power_isa_gpr_reg_imm($ra).value, MOpRegNum::power_isa_gpr_reg_imm($ra),
MOpRegNum::power_isa_gpr_reg_imm($rb).value, MOpRegNum::power_isa_gpr_reg_imm($rb),
], ],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -189,7 +189,7 @@ pub fn test_cases_book_i_3_3_2_fixed_point_load(retval: &mut Vec<TestCase>) {
), ),
LoadMOp::load( LoadMOp::load(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[]),
[MOpRegNum::power_isa_gpr_reg_imm($ra).value], [MOpRegNum::power_isa_gpr_reg_imm($ra)],
LoadStoreWidth.$width(), LoadStoreWidth.$width(),
LoadStoreConversion.$conversion(), LoadStoreConversion.$conversion(),
), ),

10
crates/cpu/tests/simple_power_isa_decoder/test_cases/fixed_point_logical.rs
View file

@ -34,7 +34,7 @@ pub fn test_cases_book_i_3_3_13_fixed_point_logical(retval: &mut Vec<TestCase>)
&[] &[]
}, },
), ),
[MOpRegNum::power_isa_gpr_reg_imm($src).value], [MOpRegNum::power_isa_gpr_reg_imm($src)],
(($imm as u32) << if $mnemonic.contains('s') { 16 } else { 0 }) (($imm as u32) << if $mnemonic.contains('s') { 16 } else { 0 })
.cast_to_static::<SInt<_>>(), .cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -108,8 +108,8 @@ pub fn test_cases_book_i_3_3_13_fixed_point_logical(retval: &mut Vec<TestCase>)
}, },
), ),
[ [
MOpRegNum::power_isa_gpr_reg_imm($src0).value, MOpRegNum::power_isa_gpr_reg_imm($src0),
MOpRegNum::power_isa_gpr_reg_imm($src1).value, MOpRegNum::power_isa_gpr_reg_imm($src1),
], ],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -159,7 +159,7 @@ pub fn test_cases_book_i_3_3_13_fixed_point_logical(retval: &mut Vec<TestCase>)
None, None,
MoveRegMOp::move_reg( MoveRegMOp::move_reg(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
[MOpRegNum::power_isa_gpr_reg_imm(4).value], [MOpRegNum::power_isa_gpr_reg_imm(4)],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
), ),
)); ));
@ -232,7 +232,7 @@ pub fn test_cases_book_i_3_3_13_fixed_point_logical(retval: &mut Vec<TestCase>)
&[] &[]
}, },
), ),
[MOpRegNum::power_isa_gpr_reg_imm($src).value], [MOpRegNum::power_isa_gpr_reg_imm($src)],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
OutputIntegerMode.$OutputIntegerMode(), OutputIntegerMode.$OutputIntegerMode(),
Lut4::from_fn(|a, b| a | b), Lut4::from_fn(|a, b| a | b),

84
crates/cpu/tests/simple_power_isa_decoder/test_cases/fixed_point_rotate_and_shift.rs
View file

@ -95,9 +95,9 @@ pub fn test_cases_book_i_3_3_14_fixed_point_rotate_and_shift(retval: &mut Vec<Te
ShiftRotateMOp::shift_rotate( ShiftRotateMOp::shift_rotate(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[]),
[ [
MOpRegNum::power_isa_gpr_reg_imm($src).value, MOpRegNum::power_isa_gpr_reg_imm($src),
MOpRegNum::power_isa_gpr_reg_imm($src).value, MOpRegNum::power_isa_gpr_reg_imm($src),
src2.value, src2,
], ],
&imm, &imm,
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -121,9 +121,9 @@ pub fn test_cases_book_i_3_3_14_fixed_point_rotate_and_shift(retval: &mut Vec<Te
ShiftRotateMOp::shift_rotate( ShiftRotateMOp::shift_rotate(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],),
[ [
MOpRegNum::power_isa_gpr_reg_imm($src).value, MOpRegNum::power_isa_gpr_reg_imm($src),
MOpRegNum::power_isa_gpr_reg_imm($src).value, MOpRegNum::power_isa_gpr_reg_imm($src),
src2.value, src2,
], ],
imm, imm,
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -156,9 +156,9 @@ pub fn test_cases_book_i_3_3_14_fixed_point_rotate_and_shift(retval: &mut Vec<Te
ShiftRotateMOp::shift_rotate( ShiftRotateMOp::shift_rotate(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[]),
[ [
MOpRegNum::power_isa_gpr_reg_imm($src).value, MOpRegNum::power_isa_gpr_reg_imm($src),
MOpRegNum::power_isa_gpr_reg_imm($src).value, MOpRegNum::power_isa_gpr_reg_imm($src),
MOpRegNum::power_isa_gpr_reg_imm($amount).value, MOpRegNum::power_isa_gpr_reg_imm($amount),
], ],
rotate_imm(None, $rotated_output_start_and_len, false), rotate_imm(None, $rotated_output_start_and_len, false),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -182,9 +182,9 @@ pub fn test_cases_book_i_3_3_14_fixed_point_rotate_and_shift(retval: &mut Vec<Te
ShiftRotateMOp::shift_rotate( ShiftRotateMOp::shift_rotate(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],),
[ [
MOpRegNum::power_isa_gpr_reg_imm($src).value, MOpRegNum::power_isa_gpr_reg_imm($src),
MOpRegNum::power_isa_gpr_reg_imm($src).value, MOpRegNum::power_isa_gpr_reg_imm($src),
MOpRegNum::power_isa_gpr_reg_imm($amount).value, MOpRegNum::power_isa_gpr_reg_imm($amount),
], ],
rotate_imm(None, $rotated_output_start_and_len, false), rotate_imm(None, $rotated_output_start_and_len, false),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -739,9 +739,9 @@ pub fn test_cases_book_i_3_3_14_fixed_point_rotate_and_shift(retval: &mut Vec<Te
ShiftRotateMOp::shift_rotate( ShiftRotateMOp::shift_rotate(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[]),
[ [
MOpRegNum::power_isa_gpr_reg_imm($src).value, MOpRegNum::power_isa_gpr_reg_imm($src),
MOpRegNum::const_zero().value, MOpRegNum::const_zero(),
MOpRegNum::power_isa_gpr_reg_imm($amount).value, MOpRegNum::power_isa_gpr_reg_imm($amount),
], ],
shift_imm(None, false), shift_imm(None, false),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -766,9 +766,9 @@ pub fn test_cases_book_i_3_3_14_fixed_point_rotate_and_shift(retval: &mut Vec<Te
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM], &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
), ),
[ [
MOpRegNum::power_isa_gpr_reg_imm($src).value, MOpRegNum::power_isa_gpr_reg_imm($src),
MOpRegNum::const_zero().value, MOpRegNum::const_zero(),
MOpRegNum::power_isa_gpr_reg_imm($amount).value, MOpRegNum::power_isa_gpr_reg_imm($amount),
], ],
shift_imm(None, false), shift_imm(None, false),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -798,9 +798,9 @@ pub fn test_cases_book_i_3_3_14_fixed_point_rotate_and_shift(retval: &mut Vec<Te
ShiftRotateMOp::shift_rotate( ShiftRotateMOp::shift_rotate(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[]),
[ [
MOpRegNum::const_zero().value, MOpRegNum::const_zero(),
MOpRegNum::power_isa_gpr_reg_imm($src).value, MOpRegNum::power_isa_gpr_reg_imm($src),
MOpRegNum::power_isa_gpr_reg_imm($amount).value, MOpRegNum::power_isa_gpr_reg_imm($amount),
], ],
shift_imm(None, true), shift_imm(None, true),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -825,9 +825,9 @@ pub fn test_cases_book_i_3_3_14_fixed_point_rotate_and_shift(retval: &mut Vec<Te
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM], &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
), ),
[ [
MOpRegNum::const_zero().value, MOpRegNum::const_zero(),
MOpRegNum::power_isa_gpr_reg_imm($src).value, MOpRegNum::power_isa_gpr_reg_imm($src),
MOpRegNum::power_isa_gpr_reg_imm($amount).value, MOpRegNum::power_isa_gpr_reg_imm($amount),
], ],
shift_imm(None, true), shift_imm(None, true),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -863,9 +863,9 @@ pub fn test_cases_book_i_3_3_14_fixed_point_rotate_and_shift(retval: &mut Vec<Te
&[], &[],
), ),
[ [
MOpRegNum::power_isa_gpr_reg_imm($src).value, MOpRegNum::power_isa_gpr_reg_imm($src),
MOpRegNum::const_zero().value, MOpRegNum::const_zero(),
MOpRegNum::power_isa_gpr_reg_imm($amount).value, MOpRegNum::power_isa_gpr_reg_imm($amount),
], ],
shift_imm(None, true), shift_imm(None, true),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -893,9 +893,9 @@ pub fn test_cases_book_i_3_3_14_fixed_point_rotate_and_shift(retval: &mut Vec<Te
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM], &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
), ),
[ [
MOpRegNum::power_isa_gpr_reg_imm($src).value, MOpRegNum::power_isa_gpr_reg_imm($src),
MOpRegNum::const_zero().value, MOpRegNum::const_zero(),
MOpRegNum::power_isa_gpr_reg_imm($amount).value, MOpRegNum::power_isa_gpr_reg_imm($amount),
], ],
shift_imm(None, true), shift_imm(None, true),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -931,9 +931,9 @@ pub fn test_cases_book_i_3_3_14_fixed_point_rotate_and_shift(retval: &mut Vec<Te
&[], &[],
), ),
[ [
MOpRegNum::power_isa_gpr_reg_imm($src).value, MOpRegNum::power_isa_gpr_reg_imm($src),
MOpRegNum::const_zero().value, MOpRegNum::const_zero(),
MOpRegNum::const_zero().value, MOpRegNum::const_zero(),
], ],
shift_imm(Some($amount), true), shift_imm(Some($amount), true),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -961,9 +961,9 @@ pub fn test_cases_book_i_3_3_14_fixed_point_rotate_and_shift(retval: &mut Vec<Te
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM], &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
), ),
[ [
MOpRegNum::power_isa_gpr_reg_imm($src).value, MOpRegNum::power_isa_gpr_reg_imm($src),
MOpRegNum::const_zero().value, MOpRegNum::const_zero(),
MOpRegNum::const_zero().value, MOpRegNum::const_zero(),
], ],
shift_imm(Some($amount), true), shift_imm(Some($amount), true),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -1072,9 +1072,9 @@ pub fn test_cases_book_i_3_3_14_fixed_point_rotate_and_shift(retval: &mut Vec<Te
ShiftRotateMOp::shift_rotate( ShiftRotateMOp::shift_rotate(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[]),
[ [
MOpRegNum::power_isa_gpr_reg_imm($src).value, MOpRegNum::power_isa_gpr_reg_imm($src),
MOpRegNum::const_zero().value, MOpRegNum::const_zero(),
MOpRegNum::const_zero().value, MOpRegNum::const_zero(),
], ],
shift_imm(Some($amount), false), shift_imm(Some($amount), false),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -1099,9 +1099,9 @@ pub fn test_cases_book_i_3_3_14_fixed_point_rotate_and_shift(retval: &mut Vec<Te
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM], &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
), ),
[ [
MOpRegNum::power_isa_gpr_reg_imm($src).value, MOpRegNum::power_isa_gpr_reg_imm($src),
MOpRegNum::const_zero().value, MOpRegNum::const_zero(),
MOpRegNum::const_zero().value, MOpRegNum::const_zero(),
], ],
shift_imm(Some($amount), false), shift_imm(Some($amount), false),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),

68
crates/cpu/tests/simple_power_isa_decoder/test_cases/fixed_point_store.rs
View file

@ -25,11 +25,11 @@ pub fn test_cases_book_i_3_3_3_fixed_point_store(retval: &mut Vec<TestCase>) {
MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]), MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]),
[ [
if $r != 0 || $ra == 0 { if $r != 0 || $ra == 0 {
MOpRegNum::const_zero().value MOpRegNum::const_zero()
} else { } else {
MOpRegNum::power_isa_gpr_reg_imm($ra).value MOpRegNum::power_isa_gpr_reg_imm($ra)
}, },
MOpRegNum::const_zero().value, MOpRegNum::const_zero(),
], ],
($disp as i64).cast_to_static::<SInt<_>>(), ($disp as i64).cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -41,8 +41,8 @@ pub fn test_cases_book_i_3_3_3_fixed_point_store(retval: &mut Vec<TestCase>) {
StoreMOp::store( StoreMOp::store(
MOpDestReg::new_sim(&[], &[]), MOpDestReg::new_sim(&[], &[]),
[ [
MOpRegNum::power_isa_temp_reg().value, MOpRegNum::power_isa_temp_reg(),
MOpRegNum::power_isa_gpr_reg_imm($rs).value, MOpRegNum::power_isa_gpr_reg_imm($rs),
], ],
LoadStoreWidth.$width(), LoadStoreWidth.$width(),
LoadStoreConversion.ZeroExt(), LoadStoreConversion.ZeroExt(),
@ -66,11 +66,11 @@ pub fn test_cases_book_i_3_3_3_fixed_point_store(retval: &mut Vec<TestCase>) {
MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]), MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]),
[ [
if $ra == 0 { if $ra == 0 {
MOpRegNum::const_zero().value MOpRegNum::const_zero()
} else { } else {
MOpRegNum::power_isa_gpr_reg_imm($ra).value MOpRegNum::power_isa_gpr_reg_imm($ra)
}, },
MOpRegNum::const_zero().value, MOpRegNum::const_zero(),
], ],
($disp as i64).cast_to_static::<SInt<_>>(), ($disp as i64).cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -82,8 +82,8 @@ pub fn test_cases_book_i_3_3_3_fixed_point_store(retval: &mut Vec<TestCase>) {
StoreMOp::store( StoreMOp::store(
MOpDestReg::new_sim(&[], &[]), MOpDestReg::new_sim(&[], &[]),
[ [
MOpRegNum::power_isa_temp_reg().value, MOpRegNum::power_isa_temp_reg(),
MOpRegNum::power_isa_gpr_reg_imm($rs).value, MOpRegNum::power_isa_gpr_reg_imm($rs),
], ],
LoadStoreWidth.$width(), LoadStoreWidth.$width(),
LoadStoreConversion.ZeroExt(), LoadStoreConversion.ZeroExt(),
@ -107,8 +107,8 @@ pub fn test_cases_book_i_3_3_3_fixed_point_store(retval: &mut Vec<TestCase>) {
AddSubMOp::add_sub_i( AddSubMOp::add_sub_i(
MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]), MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]),
[ [
MOpRegNum::power_isa_gpr_reg_imm($ra).value, MOpRegNum::power_isa_gpr_reg_imm($ra),
MOpRegNum::const_zero().value, MOpRegNum::const_zero(),
], ],
($disp as i64).cast_to_static::<SInt<_>>(), ($disp as i64).cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -120,15 +120,15 @@ pub fn test_cases_book_i_3_3_3_fixed_point_store(retval: &mut Vec<TestCase>) {
StoreMOp::store( StoreMOp::store(
MOpDestReg::new_sim(&[], &[]), MOpDestReg::new_sim(&[], &[]),
[ [
MOpRegNum::power_isa_temp_reg().value, MOpRegNum::power_isa_temp_reg(),
MOpRegNum::power_isa_gpr_reg_imm($rs).value, MOpRegNum::power_isa_gpr_reg_imm($rs),
], ],
LoadStoreWidth.$width(), LoadStoreWidth.$width(),
LoadStoreConversion.ZeroExt(), LoadStoreConversion.ZeroExt(),
), ),
MoveRegMOp::move_reg( MoveRegMOp::move_reg(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($ra)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($ra)], &[]),
[MOpRegNum::power_isa_temp_reg().value], [MOpRegNum::power_isa_temp_reg()],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
), ),
], ],
@ -142,8 +142,8 @@ pub fn test_cases_book_i_3_3_3_fixed_point_store(retval: &mut Vec<TestCase>) {
AddSubMOp::add_sub_i( AddSubMOp::add_sub_i(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($ra)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($ra)], &[]),
[ [
MOpRegNum::power_isa_gpr_reg_imm($ra).value, MOpRegNum::power_isa_gpr_reg_imm($ra),
MOpRegNum::const_zero().value, MOpRegNum::const_zero(),
], ],
($disp as i64).cast_to_static::<SInt<_>>(), ($disp as i64).cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -155,8 +155,8 @@ pub fn test_cases_book_i_3_3_3_fixed_point_store(retval: &mut Vec<TestCase>) {
StoreMOp::store( StoreMOp::store(
MOpDestReg::new_sim(&[], &[]), MOpDestReg::new_sim(&[], &[]),
[ [
MOpRegNum::power_isa_gpr_reg_imm($ra).value, MOpRegNum::power_isa_gpr_reg_imm($ra),
MOpRegNum::power_isa_gpr_reg_imm($rs).value, MOpRegNum::power_isa_gpr_reg_imm($rs),
], ],
LoadStoreWidth.$width(), LoadStoreWidth.$width(),
LoadStoreConversion.ZeroExt(), LoadStoreConversion.ZeroExt(),
@ -181,11 +181,11 @@ pub fn test_cases_book_i_3_3_3_fixed_point_store(retval: &mut Vec<TestCase>) {
MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]), MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]),
[ [
if $ra == 0 { if $ra == 0 {
MOpRegNum::const_zero().value MOpRegNum::const_zero()
} else { } else {
MOpRegNum::power_isa_gpr_reg_imm($ra).value MOpRegNum::power_isa_gpr_reg_imm($ra)
}, },
MOpRegNum::power_isa_gpr_reg_imm($rb).value, MOpRegNum::power_isa_gpr_reg_imm($rb),
], ],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -197,8 +197,8 @@ pub fn test_cases_book_i_3_3_3_fixed_point_store(retval: &mut Vec<TestCase>) {
StoreMOp::store( StoreMOp::store(
MOpDestReg::new_sim(&[], &[]), MOpDestReg::new_sim(&[], &[]),
[ [
MOpRegNum::power_isa_temp_reg().value, MOpRegNum::power_isa_temp_reg(),
MOpRegNum::power_isa_gpr_reg_imm($rs).value, MOpRegNum::power_isa_gpr_reg_imm($rs),
], ],
LoadStoreWidth.$width(), LoadStoreWidth.$width(),
LoadStoreConversion.ZeroExt(), LoadStoreConversion.ZeroExt(),
@ -222,8 +222,8 @@ pub fn test_cases_book_i_3_3_3_fixed_point_store(retval: &mut Vec<TestCase>) {
AddSubMOp::add_sub_i( AddSubMOp::add_sub_i(
MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]), MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]),
[ [
MOpRegNum::power_isa_gpr_reg_imm($ra).value, MOpRegNum::power_isa_gpr_reg_imm($ra),
MOpRegNum::power_isa_gpr_reg_imm($rb).value, MOpRegNum::power_isa_gpr_reg_imm($rb),
], ],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -235,15 +235,15 @@ pub fn test_cases_book_i_3_3_3_fixed_point_store(retval: &mut Vec<TestCase>) {
StoreMOp::store( StoreMOp::store(
MOpDestReg::new_sim(&[], &[]), MOpDestReg::new_sim(&[], &[]),
[ [
MOpRegNum::power_isa_temp_reg().value, MOpRegNum::power_isa_temp_reg(),
MOpRegNum::power_isa_gpr_reg_imm($rs).value, MOpRegNum::power_isa_gpr_reg_imm($rs),
], ],
LoadStoreWidth.$width(), LoadStoreWidth.$width(),
LoadStoreConversion.ZeroExt(), LoadStoreConversion.ZeroExt(),
), ),
MoveRegMOp::move_reg( MoveRegMOp::move_reg(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($ra)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($ra)], &[]),
[MOpRegNum::power_isa_temp_reg().value], [MOpRegNum::power_isa_temp_reg()],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
), ),
], ],
@ -258,11 +258,11 @@ pub fn test_cases_book_i_3_3_3_fixed_point_store(retval: &mut Vec<TestCase>) {
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($ra)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($ra)], &[]),
[ [
if $ra == 0 { if $ra == 0 {
MOpRegNum::const_zero().value MOpRegNum::const_zero()
} else { } else {
MOpRegNum::power_isa_gpr_reg_imm($ra).value MOpRegNum::power_isa_gpr_reg_imm($ra)
}, },
MOpRegNum::power_isa_gpr_reg_imm($rb).value, MOpRegNum::power_isa_gpr_reg_imm($rb),
], ],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -274,8 +274,8 @@ pub fn test_cases_book_i_3_3_3_fixed_point_store(retval: &mut Vec<TestCase>) {
StoreMOp::store( StoreMOp::store(
MOpDestReg::new_sim(&[], &[]), MOpDestReg::new_sim(&[], &[]),
[ [
MOpRegNum::power_isa_gpr_reg_imm($ra).value, MOpRegNum::power_isa_gpr_reg_imm($ra),
MOpRegNum::power_isa_gpr_reg_imm($rs).value, MOpRegNum::power_isa_gpr_reg_imm($rs),
], ],
LoadStoreWidth.$width(), LoadStoreWidth.$width(),
LoadStoreConversion.ZeroExt(), LoadStoreConversion.ZeroExt(),

26
crates/cpu/tests/simple_power_isa_decoder/test_cases/move_to_from_system_register.rs
View file

@ -30,9 +30,9 @@ pub fn test_cases_book_i_3_3_19_move_to_from_system_register(retval: &mut Vec<Te
LogicalFlagsMOp::logical_flags( LogicalFlagsMOp::logical_flags(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
[ [
MOpRegNum::power_isa_xer_ca_ca32_reg().value, MOpRegNum::power_isa_xer_ca_ca32_reg(),
MOpRegNum::const_zero().value, MOpRegNum::const_zero(),
MOpRegNum::power_isa_xer_so_ov_ov32_reg().value, MOpRegNum::power_isa_xer_so_ov_ov32_reg(),
], ],
mcrxrx_imm(), mcrxrx_imm(),
Lut4::from_fn(|a, b| a | b), Lut4::from_fn(|a, b| a | b),
@ -48,7 +48,7 @@ pub fn test_cases_book_iii_5_4_4_move_to_from_system_register(retval: &mut Vec<T
None, None,
MoveRegMOp::move_reg( MoveRegMOp::move_reg(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
[MOpRegNum::power_isa_lr_reg().value], [MOpRegNum::power_isa_lr_reg()],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
), ),
)); ));
@ -58,7 +58,7 @@ pub fn test_cases_book_iii_5_4_4_move_to_from_system_register(retval: &mut Vec<T
None, None,
MoveRegMOp::move_reg( MoveRegMOp::move_reg(
MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_LR_REG_NUM], &[]), MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_LR_REG_NUM], &[]),
[MOpRegNum::power_isa_gpr_reg_imm(3).value], [MOpRegNum::power_isa_gpr_reg_imm(3)],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
), ),
)); ));
@ -68,7 +68,7 @@ pub fn test_cases_book_iii_5_4_4_move_to_from_system_register(retval: &mut Vec<T
None, None,
MoveRegMOp::move_reg( MoveRegMOp::move_reg(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
[MOpRegNum::power_isa_ctr_reg().value], [MOpRegNum::power_isa_ctr_reg()],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
), ),
)); ));
@ -78,7 +78,7 @@ pub fn test_cases_book_iii_5_4_4_move_to_from_system_register(retval: &mut Vec<T
None, None,
MoveRegMOp::move_reg( MoveRegMOp::move_reg(
MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_CTR_REG_NUM], &[]), MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_CTR_REG_NUM], &[]),
[MOpRegNum::power_isa_gpr_reg_imm(3).value], [MOpRegNum::power_isa_gpr_reg_imm(3)],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
), ),
)); ));
@ -88,7 +88,7 @@ pub fn test_cases_book_iii_5_4_4_move_to_from_system_register(retval: &mut Vec<T
None, None,
MoveRegMOp::move_reg( MoveRegMOp::move_reg(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
[MOpRegNum::power_isa_tar_reg().value], [MOpRegNum::power_isa_tar_reg()],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
), ),
)); ));
@ -98,7 +98,7 @@ pub fn test_cases_book_iii_5_4_4_move_to_from_system_register(retval: &mut Vec<T
None, None,
MoveRegMOp::move_reg( MoveRegMOp::move_reg(
MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TAR_REG_NUM], &[]), MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TAR_REG_NUM], &[]),
[MOpRegNum::power_isa_gpr_reg_imm(3).value], [MOpRegNum::power_isa_gpr_reg_imm(3)],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
), ),
)); ));
@ -109,7 +109,7 @@ pub fn test_cases_book_iii_5_4_4_move_to_from_system_register(retval: &mut Vec<T
None, None,
ReadSpecialMOp::read_special( ReadSpecialMOp::read_special(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
[MOpRegNum::const_zero().value; 0], [MOpRegNum::const_zero(); 0],
ReadSpecialMOpImm.PowerIsaTimeBase(), ReadSpecialMOpImm.PowerIsaTimeBase(),
), ),
)); ));
@ -120,7 +120,7 @@ pub fn test_cases_book_iii_5_4_4_move_to_from_system_register(retval: &mut Vec<T
None, None,
ReadSpecialMOp::read_special( ReadSpecialMOp::read_special(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
[MOpRegNum::const_zero().value; 0], [MOpRegNum::const_zero(); 0],
ReadSpecialMOpImm.PowerIsaTimeBaseU(), ReadSpecialMOpImm.PowerIsaTimeBaseU(),
), ),
)); ));
@ -131,7 +131,7 @@ pub fn test_cases_book_iii_5_4_4_move_to_from_system_register(retval: &mut Vec<T
None, None,
ReadSpecialMOp::read_special( ReadSpecialMOp::read_special(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
[MOpRegNum::const_zero().value; 0], [MOpRegNum::const_zero(); 0],
ReadSpecialMOpImm.PowerIsaTimeBase(), ReadSpecialMOpImm.PowerIsaTimeBase(),
), ),
)); ));
@ -142,7 +142,7 @@ pub fn test_cases_book_iii_5_4_4_move_to_from_system_register(retval: &mut Vec<T
None, None,
ReadSpecialMOp::read_special( ReadSpecialMOp::read_special(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
[MOpRegNum::const_zero().value; 0], [MOpRegNum::const_zero(); 0],
ReadSpecialMOpImm.PowerIsaTimeBaseU(), ReadSpecialMOpImm.PowerIsaTimeBaseU(),
), ),
)); ));