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change MOp to use SrcReg: Type instead of UIntType<SrcRegWidth>

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This commit is contained in:
Jacob Lifshay 2026-05-07 19:52:51 -07:00
parent 409ca7bf97
commit 5e6041a97c
Signed by: programmerjake
SSH key fingerprint: SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
17 changed files with 25735 additions and 25103 deletions
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78
crates/cpu/tests/rename_execute_retire.rs
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@ -3,8 +3,8 @@
use cpu::{
config::{
CpuConfig, CpuConfigFetchWidth, CpuConfigMaxUnitMaxInFlight, CpuConfigPRegNumWidth,
PhantomConstCpuConfig, UnitConfig,
CpuConfig, CpuConfigFetchWidth, CpuConfigMaxUnitMaxInFlight, PhantomConstCpuConfig,
UnitConfig,
},
instruction::{
AddSubMOp, AluBranchMOp, AluCommonMOp, BranchMOp, COMMON_MOP_SRC_LEN, CommonMOp,
@ -246,7 +246,7 @@ impl InsnsBuilder {
move |labels| {
[BranchMOp::branch_i(
MOpDestReg::new([], []),
MOpRegNum::const_zero().value,
[MOpRegNum::const_zero(); 2],
labels[target.0]
.pc()
.wrapping_sub(pc)
@ -264,7 +264,7 @@ impl InsnsBuilder {
format!("blr"),
[BranchMOp::branch_i(
MOpDestReg::new([], []),
MOpRegNum::power_isa_lr_reg().value,
[MOpRegNum::const_zero(), MOpRegNum::power_isa_lr_reg()],
0i8.cast_to_static::<SInt<_>>(),
false,
false,
@ -281,9 +281,9 @@ impl InsnsBuilder {
[BranchMOp::branch_cond_ctr(
MOpDestReg::new([], []),
[
MOpRegNum::power_isa_cr_reg_imm(0).value,
MOpRegNum::const_zero().value,
MOpRegNum::const_zero().value,
MOpRegNum::power_isa_cr_reg_imm(0),
MOpRegNum::const_zero(),
MOpRegNum::const_zero(),
],
labels[target.0]
.pc()
@ -307,7 +307,7 @@ impl InsnsBuilder {
move |labels| {
[BranchMOp::branch_i(
MOpDestReg::new([MOpRegNum::power_isa_lr_reg()], []),
MOpRegNum::const_zero().value,
[MOpRegNum::const_zero(); 2],
labels[target.0]
.pc()
.wrapping_sub(pc)
@ -326,9 +326,9 @@ impl InsnsBuilder {
[AddSubMOp::add_sub(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(dest)], &[]),
[
MOpRegNum::power_isa_gpr_reg_imm(src1).value,
MOpRegNum::power_isa_gpr_reg_imm(src2).value,
MOpRegNum::const_zero().value,
MOpRegNum::power_isa_gpr_reg_imm(src1),
MOpRegNum::power_isa_gpr_reg_imm(src2),
MOpRegNum::const_zero(),
],
0i8.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(),
@ -346,8 +346,8 @@ impl InsnsBuilder {
[AddSubMOp::add_sub_i(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(dest)], &[]),
[
MOpRegNum::power_isa_gpr_or_zero_reg_imm(src).value,
MOpRegNum::const_zero().value,
MOpRegNum::power_isa_gpr_or_zero_reg_imm(src),
MOpRegNum::const_zero(),
],
imm.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(),
@ -364,7 +364,7 @@ impl InsnsBuilder {
format!("cmpldi {dest}, {src}, {imm:#x}"),
[CompareMOp::compare_i(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(dest)], &[]),
[MOpRegNum::power_isa_gpr_reg_imm(src).value],
[MOpRegNum::power_isa_gpr_reg_imm(src)],
imm.cast_to_static::<SInt<_>>(),
CompareMode.U64(),
)],
@ -378,8 +378,8 @@ impl InsnsBuilder {
AddSubMOp::add_sub_i(
MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]),
[
MOpRegNum::power_isa_gpr_or_zero_reg_imm(src).value,
MOpRegNum::const_zero().value,
MOpRegNum::power_isa_gpr_or_zero_reg_imm(src),
MOpRegNum::const_zero(),
],
disp.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(),
@ -390,7 +390,7 @@ impl InsnsBuilder {
),
LoadMOp::load(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(dest)], &[]),
[MOpRegNum::power_isa_temp_reg().value],
[MOpRegNum::power_isa_temp_reg()],
LoadStoreWidth.Width64Bit(),
LoadStoreConversion.ZeroExt(),
),
@ -405,8 +405,8 @@ impl InsnsBuilder {
AddSubMOp::add_sub_i(
MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]),
[
MOpRegNum::power_isa_gpr_or_zero_reg_imm(addr_src).value,
MOpRegNum::const_zero().value,
MOpRegNum::power_isa_gpr_or_zero_reg_imm(addr_src),
MOpRegNum::const_zero(),
],
disp.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(),
@ -418,8 +418,8 @@ impl InsnsBuilder {
StoreMOp::store(
MOpDestReg::new_sim(&[], &[]),
[
MOpRegNum::power_isa_temp_reg().value,
MOpRegNum::power_isa_gpr_reg_imm(value_src).value,
MOpRegNum::power_isa_temp_reg(),
MOpRegNum::power_isa_gpr_reg_imm(value_src),
],
LoadStoreWidth.Width64Bit(),
LoadStoreConversion.ZeroExt(),
@ -433,7 +433,7 @@ impl InsnsBuilder {
format!("mflr {dest}"),
[MoveRegMOp::move_reg(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(dest)], &[]),
[MOpRegNum::power_isa_lr_reg().value],
[MOpRegNum::power_isa_lr_reg()],
0i8.cast_to_static::<SInt<_>>(),
)],
));
@ -444,7 +444,7 @@ impl InsnsBuilder {
format!("mtlr {src}"),
[MoveRegMOp::move_reg(
MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_LR_REG_NUM], &[]),
[MOpRegNum::power_isa_gpr_reg_imm(src).value],
[MOpRegNum::power_isa_gpr_reg_imm(src)],
0i8.cast_to_static::<SInt<_>>(),
)],
));
@ -455,7 +455,7 @@ impl InsnsBuilder {
format!("mr {dest}, {src}"),
[MoveRegMOp::move_reg(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(dest)], &[]),
[MOpRegNum::power_isa_gpr_reg_imm(src).value],
[MOpRegNum::power_isa_gpr_reg_imm(src)],
0i8.cast_to_static::<SInt<_>>(),
)],
));
@ -579,7 +579,7 @@ impl BrPredState {
}
fn predict_branch<SrcCount: KnownSize>(
&mut self,
mop: &SimValue<BranchMOp<MOpDestReg, ConstUsize<{ MOpRegNum::WIDTH }>, SrcCount>>,
mop: &SimValue<BranchMOp<MOpDestReg, MOpRegNum, SrcCount>>,
branch_pc: u64,
fallthrough_pc: u64,
) -> u64 {
@ -590,7 +590,7 @@ impl BrPredState {
}
let mut src_regs = [MOpRegNum::CONST_ZERO_REG_NUM; 3];
MOpTrait::for_each_src_reg_sim_ref(mop, &mut |reg, index| {
src_regs[index] = reg.cast_to_static::<UInt<32>>().as_int();
src_regs[index] = MOpRegNum::reg_num_sim(reg);
});
if src_regs[1] != MOpRegNum::CONST_ZERO_REG_NUM {
// indirect branch -- this test doesn't implement predicting them, so just use the fallthrough_pc
@ -1268,7 +1268,7 @@ impl MockMemory {
#[hdl]
fn run_mop<C: PhantomConstCpuConfig>(
&mut self,
mop: &SimValue<MOpInstance<LoadStoreMOp<PRegNum<C>, CpuConfigPRegNumWidth<C>>>>,
mop: &SimValue<MOpInstance<LoadStoreMOp<PRegNum<C>, PRegNum<C>>>>,
src_values: &[SimValue<PRegValue>; COMMON_MOP_SRC_LEN],
is_speculative: bool,
) -> Result<SimValue<PRegValue>, AddressCantBeSpeculativelyAccessed> {
@ -1389,7 +1389,7 @@ trait MockExecutionStateTrait: Default {
fn run_add_sub<C: PhantomConstCpuConfig, SrcCount: KnownSize>(
&mut self,
pc: u64,
mop: &SimValue<AddSubMOp<PRegNum<C>, CpuConfigPRegNumWidth<C>, SrcCount>>,
mop: &SimValue<AddSubMOp<PRegNum<C>, PRegNum<C>, SrcCount>>,
src_values: &[SimValue<PRegValue>; COMMON_MOP_SRC_LEN],
) -> SimValue<PRegValue> {
#[hdl(sim)]
@ -1453,7 +1453,7 @@ trait MockExecutionStateTrait: Default {
#[hdl]
fn run_compare<C: PhantomConstCpuConfig, SrcCount: KnownSize>(
&mut self,
mop: &SimValue<CompareMOp<PRegNum<C>, CpuConfigPRegNumWidth<C>, SrcCount>>,
mop: &SimValue<CompareMOp<PRegNum<C>, PRegNum<C>, SrcCount>>,
src_values: &[SimValue<PRegValue>; COMMON_MOP_SRC_LEN],
) -> SimValue<PRegValue> {
#[hdl(sim)]
@ -1513,7 +1513,7 @@ trait MockExecutionStateTrait: Default {
pc: u64,
fallthrough_pc: u64,
predicted_next_pc: u64,
mop: &SimValue<BranchMOp<PRegNum<C>, CpuConfigPRegNumWidth<C>, SrcCount>>,
mop: &SimValue<BranchMOp<PRegNum<C>, PRegNum<C>, SrcCount>>,
src_values: &[SimValue<PRegValue>; COMMON_MOP_SRC_LEN],
config: C,
) -> (
@ -1539,12 +1539,14 @@ trait MockExecutionStateTrait: Default {
imm,
} = common;
let [src0, src1, src2] = src_values;
let has_src0 = src.as_ref().get(0).is_some_and(|src0| {
src0.cast_bits_to(PRegNum[config]) != PRegNum[config].const_zero().into_sim_value()
});
let has_src2 = src.as_ref().get(2).is_some_and(|src2| {
src2.cast_bits_to(PRegNum[config]) != PRegNum[config].const_zero().into_sim_value()
});
let has_src0 = src
.as_ref()
.get(0)
.is_some_and(|src0| *src0 != PRegNum[config].const_zero_sim());
let has_src2 = src
.as_ref()
.get(2)
.is_some_and(|src2| *src2 != PRegNum[config].const_zero_sim());
let src2_cond = if has_src2 {
let _ = invert_src2_eq_zero;
let _ = src2;
@ -2236,7 +2238,7 @@ fn mock_unit<#[hdl(skip)] E: MockExecutionStateTrait>(
#[hdl(no_static)]
struct MockLoadStoreOpDebugState<C: PhantomConstGet<CpuConfig>> {
mop: MOpInstance<LoadStoreMOp<PRegNum<C>, CpuConfigPRegNumWidth<C>>>,
mop: MOpInstance<LoadStoreMOp<PRegNum<C>, PRegNum<C>>>,
is_speculative: Bool,
src_values: HdlOption<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>,
dest_value: HdlOption<PRegValue>,
@ -2248,7 +2250,7 @@ struct MockLoadStoreOpDebugState<C: PhantomConstGet<CpuConfig>> {
#[derive(Debug)]
struct MockLoadStoreOp<C: PhantomConstCpuConfig> {
mop: SimValue<MOpInstance<LoadStoreMOp<PRegNum<C>, CpuConfigPRegNumWidth<C>>>>,
mop: SimValue<MOpInstance<LoadStoreMOp<PRegNum<C>, PRegNum<C>>>>,
is_speculative: bool,
src_values: Option<[SimValue<PRegValue>; COMMON_MOP_SRC_LEN]>,
dest_value: Option<SimValue<PRegValue>>,