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rename_execute_retire: implement generating L2 reg file writes
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This commit is contained in:
Jacob Lifshay 2026-05-06 20:11:50 -07:00
parent 33b5d59507
commit 3fbdab0862
Signed by: programmerjake
SSH key fingerprint: SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
6 changed files with 867356 additions and 13009 deletions
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840
crates/cpu/tests/rename_execute_retire.rs
View file

@ -8,9 +8,10 @@ use cpu::{
},
instruction::{
AddSubMOp, AluBranchMOp, AluCommonMOp, BranchMOp, COMMON_MOP_SRC_LEN, CommonMOp,
CompareMOp, CompareMode, ConditionMode, L2RegisterFileMOp, LoadMOp, LoadStoreCommonMOp,
LoadStoreConversion, LoadStoreMOp, LoadStoreWidth, MOp, MOpDestReg, MOpRegNum, MOpTrait,
MoveRegMOp, OutputIntegerMode, PRegNum, StoreMOp, UnitNum,
CompareMOp, CompareMode, ConditionMode, L2RegNum, L2RegisterFileMOp, LoadMOp,
LoadStoreCommonMOp, LoadStoreConversion, LoadStoreMOp, LoadStoreWidth, MOp, MOpDestReg,
MOpRegNum, MOpTrait, MoveRegMOp, OutputIntegerMode, PRegNum, ReadL2RegMOp, StoreMOp,
UnitNum, WriteL2RegMOp,
},
next_pc::CallStackOp,
register::{PRegFlags, PRegFlagsPowerISA, PRegValue},
@ -291,7 +292,34 @@ impl InsnsBuilder {
.cast_to_static::<SInt<_>>(),
true,
ConditionMode.SGt(),
true,
true,
false,
false,
)]
},
));
}
fn power_isa_beq(&mut self, target: InsnsBuilderLabel) {
let pc = self.pc;
self.add_insn(Insn::new_lazy(
4,
format!("beq {}", self.labels[target.0].name),
move |labels| {
[BranchMOp::branch_cond_ctr(
MOpDestReg::new_sim(&[], &[]),
[
MOpRegNum::power_isa_cr_reg_imm(0),
MOpRegNum::const_zero(),
MOpRegNum::const_zero(),
],
labels[target.0]
.pc()
.wrapping_sub(pc)
.cast_to_static::<SInt<_>>(),
false,
ConditionMode.Eq(),
true,
true,
false,
false,
@ -843,6 +871,7 @@ fn mock_next_pc<#[hdl(skip)] MI: MakeInsns>(config: PhantomConst<CpuConfig>) {
state: Cell::new(0),
};
let insns = MI::make_insns();
dbg!(&insns);
sim.resettable(
cd,
async |mut sim| {
@ -1272,7 +1301,12 @@ impl MockMemory {
src_values: &[SimValue<PRegValue>; COMMON_MOP_SRC_LEN],
is_speculative: bool,
) -> Result<SimValue<PRegValue>, AddressCantBeSpeculativelyAccessed> {
#[hdl(sim)]
println!("MockMemory::run_mop: {:#x}: {:?}", mop.pc.as_int(), mop.mop);
println!(
"<- {}{src_values:?}",
if is_speculative { "(speculative) " } else { "" },
);
let retval = #[hdl(sim)]
match &mop.mop {
LoadStoreMOp::<_, _>::Load(mop) => {
#[hdl(sim)]
@ -1323,13 +1357,11 @@ impl MockMemory {
}
}
};
Ok(
#[hdl(sim)]
PRegValue {
int_fp: loaded,
flags: PRegFlags::zeroed_sim(),
},
)
#[hdl(sim)]
PRegValue {
int_fp: loaded,
flags: PRegFlags::zeroed_sim(),
}
}
LoadStoreMOp::<_, _>::Store(mop) => {
#[hdl(sim)]
@ -1363,25 +1395,16 @@ impl MockMemory {
}
}
}
Ok(PRegValue::zeroed_sim())
PRegValue::zeroed_sim()
}
}
};
println!("-> {retval:?}");
Ok(retval)
}
}
#[hdl(no_static)]
struct MockL2RegFileDebugState {}
#[derive(Debug, Default)]
struct MockL2RegFile {}
trait MockExecutionStateTrait: Default {
type DebugState: BundleType;
fn try_get_l2_reg_file(&mut self) -> Option<&mut MockL2RegFile>;
fn get_l2_reg_file(&mut self) -> &mut MockL2RegFile {
self.try_get_l2_reg_file()
.expect("no MockL2RegFile available in this unit")
}
fn debug_state_ty() -> Self::DebugState;
fn zeroed_debug_state() -> SimValue<Self::DebugState>;
fn debug_state(&self) -> SimValue<Self::DebugState>;
@ -1732,46 +1755,17 @@ trait MockExecutionStateTrait: Default {
);
}
UnitMOp::<_, _, _>::TransformedMove(mop) => {
let l2_reg_file = self.get_l2_reg_file();
#[hdl(sim)]
match mop {
L2RegisterFileMOp::<_, _>::ReadL2Reg(mop) => {
todo!("implement ReadL2Reg")
}
L2RegisterFileMOp::<_, _>::WriteL2Reg(mop) => {
todo!("implement WriteL2Reg")
}
}
panic!(
"mock_unit can't execute L2RegisterFile MOp, that needs mock_l2_reg_file_unit: {mop:#?}"
);
}
UnitMOp::<_, _, _>::Unknown => unreachable!(),
}
}
}
impl MockExecutionStateTrait for MockL2RegFile {
type DebugState = MockL2RegFileDebugState;
fn try_get_l2_reg_file(&mut self) -> Option<&mut MockL2RegFile> {
Some(self)
}
fn debug_state_ty() -> Self::DebugState {
MockL2RegFileDebugState
}
fn zeroed_debug_state() -> SimValue<Self::DebugState> {
zeroed(Self::debug_state_ty())
}
#[hdl]
fn debug_state(&self) -> SimValue<Self::DebugState> {
let Self {} = self;
#[hdl(sim)]
MockL2RegFileDebugState {}
}
}
impl MockExecutionStateTrait for () {
type DebugState = ();
fn try_get_l2_reg_file(&mut self) -> Option<&mut MockL2RegFile> {
None
}
fn debug_state_ty() -> Self::DebugState {
()
}
@ -2228,6 +2222,547 @@ fn mock_unit<#[hdl(skip)] E: MockExecutionStateTrait>(
}
}
#[hdl(no_static)]
struct MockL2RegFileOpDebugState<C: PhantomConstGet<CpuConfig>> {
mop: MOpInstance<L2RegisterFileMOp<PRegNum<C>, PRegNum<C>>>,
src_values: HdlOption<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>,
dest_value: HdlOption<PRegValue>,
sent_cant_cause_cancel: Bool,
sent_output_ready: Bool,
config: C,
}
#[derive(Debug)]
struct MockL2RegFileOp<C: PhantomConstCpuConfig> {
mop: SimValue<MOpInstance<L2RegisterFileMOp<PRegNum<C>, PRegNum<C>>>>,
src_values: Option<[SimValue<PRegValue>; COMMON_MOP_SRC_LEN]>,
dest_value: Option<SimValue<PRegValue>>,
sent_cant_cause_cancel: bool,
sent_output_ready: bool,
config: C,
}
impl<C: PhantomConstCpuConfig> MockL2RegFileOp<C> {
#[hdl]
fn debug_state(&self) -> SimValue<MockL2RegFileOpDebugState<C>> {
let Self {
mop,
src_values,
dest_value,
sent_cant_cause_cancel,
sent_output_ready,
config,
} = self;
#[hdl(sim)]
MockL2RegFileOpDebugState::<_> {
mop,
src_values,
dest_value,
sent_cant_cause_cancel,
sent_output_ready,
config,
}
}
fn id(&self) -> &SimValue<MOpId> {
&self.mop.id
}
}
#[hdl(get(|_| L2RegNum.l2_reg_count()))]
type L2RegFileSize<C: PhantomConstGet<CpuConfig>> = DynSize;
#[hdl(no_static)]
struct MockL2RegFileUnitDebugState<C: PhantomConstGet<CpuConfig>> {
ops: ArrayVec<MockL2RegFileOpDebugState<C>, CpuConfigMaxUnitMaxInFlight<C>>,
l2_regs: ArrayType<PRegValue, L2RegFileSize<C>>,
config: C,
}
struct MockL2RegFileUnitState<C: PhantomConstCpuConfig> {
ops: VecDeque<MockL2RegFileOp<C>>,
l2_regs: Box<[SimValue<PRegValue>]>,
config: C,
}
impl<C: PhantomConstCpuConfig> MockL2RegFileUnitState<C> {
fn new(config: C) -> Self {
Self {
ops: VecDeque::new(),
l2_regs: vec![PRegValue::zeroed_sim(); L2RegFileSize[config]].into_boxed_slice(),
config,
}
}
#[hdl]
fn debug_state(&self) -> SimValue<MockL2RegFileUnitDebugState<C>> {
let Self {
ops,
l2_regs,
config,
} = self;
let ret_ty = MockL2RegFileUnitDebugState[*config];
#[hdl(sim)]
MockL2RegFileUnitDebugState::<_> {
ops: ret_ty
.ops
.from_iter_sim(
zeroed(ret_ty.ops.element()),
ops.iter().map(MockL2RegFileOp::debug_state),
)
.ok()
.expect("known to fit"),
l2_regs,
config,
}
}
fn try_op_by_id(&self, id: &SimValue<MOpId>) -> Option<&MockL2RegFileOp<C>> {
self.ops.iter().find(|op| op.id() == id)
}
fn try_op_by_id_mut(&mut self, id: &SimValue<MOpId>) -> Option<&mut MockL2RegFileOp<C>> {
self.ops.iter_mut().find(|op| op.id() == id)
}
#[track_caller]
fn op_by_id(&self, id: &SimValue<MOpId>) -> &MockL2RegFileOp<C> {
match self.try_op_by_id(id) {
Some(retval) => retval,
None => panic!("can't find MockL2RegFileOp with id: {id:?}"),
}
}
#[track_caller]
fn op_by_id_mut(&mut self, id: &SimValue<MOpId>) -> &mut MockL2RegFileOp<C> {
match self.try_op_by_id_mut(id) {
Some(retval) => retval,
None => panic!("can't find MockL2RegFileOp with id: {id:?}"),
}
}
#[hdl]
fn step(&mut self) {
for op in &mut self.ops {
let MockL2RegFileOp {
mop,
src_values,
dest_value,
sent_cant_cause_cancel: _,
sent_output_ready: _,
config: _,
} = op;
#[hdl(sim)]
match &mop.mop {
L2RegisterFileMOp::<_, _>::ReadL2Reg(mop) => {
#[hdl(sim)]
let ReadL2RegMOp::<_, _> { common } = mop;
if src_values.is_some() && dest_value.is_none() {
*dest_value = Some(self.l2_regs[L2RegNum::value_sim(&common.imm)].clone());
}
}
L2RegisterFileMOp::<_, _>::WriteL2Reg(mop) => {
#[hdl(sim)]
let WriteL2RegMOp::<_, _> { common } = mop;
if let Some(src_values) = src_values
&& dest_value.is_none()
{
self.l2_regs[L2RegNum::value_sim(&common.imm)] = src_values[0].clone();
*dest_value = Some(PRegValue::zeroed_sim());
}
if dest_value.is_none() {
// we can't run following reads yet.
break;
}
}
}
}
}
#[hdl]
fn handle_enqueue(&mut self, enqueue: SimValue<UnitEnqueue<C>>) {
#[hdl(sim)]
let UnitEnqueue::<_> { mop, config: _ } = enqueue;
#[hdl(sim)]
let MOpInstance::<_> {
fetch_block_id,
id,
pc,
predicted_next_pc,
size_in_bytes,
is_first_mop_in_insn,
is_last_mop_in_insn,
mop,
} = mop;
let mop = #[hdl(sim)]
match &mop {
RenamedMOp::<_>::TransformedMove(mop) => mop,
_ => {
panic!("MockL2RegFileUnitState can only handle L2RegisterFile MOps, got: {mop:#?}");
}
};
let mop = #[hdl(sim)]
MOpInstance::<_> {
fetch_block_id,
id,
pc,
predicted_next_pc,
size_in_bytes,
is_first_mop_in_insn,
is_last_mop_in_insn,
mop,
};
self.ops.push_back(MockL2RegFileOp {
mop,
src_values: None,
dest_value: None,
sent_cant_cause_cancel: false,
sent_output_ready: false,
config: self.config,
});
}
#[hdl]
fn handle_inputs_ready(&mut self, inputs_ready: SimValue<UnitInputsReady<C>>) {
#[hdl(sim)]
let UnitInputsReady::<_> {
mop,
config: _,
src_values,
} = inputs_ready;
let MockL2RegFileOp {
mop: _,
src_values: op_src_values,
dest_value: _,
sent_cant_cause_cancel: _,
sent_output_ready: _,
config: _,
} = self.op_by_id_mut(&mop.id);
assert!(op_src_values.is_none());
*op_src_values = Some(SimValue::into_value(src_values));
}
#[hdl]
fn handle_mop_is_no_longer_speculative(
&mut self,
is_no_longer_speculative: SimValue<UnitMOpIsNoLongerSpeculative<C>>,
) {
#[hdl(sim)]
let UnitMOpIsNoLongerSpeculative::<_> { id, config: _ } = is_no_longer_speculative;
let MockL2RegFileOp {
mop: _,
src_values: _,
dest_value: _,
sent_cant_cause_cancel: _,
sent_output_ready: _,
config: _,
} = self.op_by_id_mut(&id);
}
#[hdl]
fn peek_mop_cant_cause_cancel(&self) -> SimValue<HdlOption<UnitMOpCantCauseCancel<C>>> {
let ret_ty = HdlOption[UnitMOpCantCauseCancel[self.config]];
for MockL2RegFileOp {
mop,
src_values: _,
dest_value: _,
sent_cant_cause_cancel,
sent_output_ready: _,
config: _,
} in &self.ops
{
if *sent_cant_cause_cancel {
continue;
}
// L2 reg file ops can never cause cancels
return #[hdl(sim)]
ret_ty.HdlSome(
#[hdl(sim)]
UnitMOpCantCauseCancel::<_> {
id: &mop.id,
config: self.config,
},
);
}
#[hdl(sim)]
ret_ty.HdlNone()
}
#[hdl]
fn handle_mop_cant_cause_cancel(
&mut self,
cant_cause_cancel: SimValue<UnitMOpCantCauseCancel<C>>,
) {
#[hdl(sim)]
let UnitMOpCantCauseCancel::<_> { id, config: _ } = cant_cause_cancel;
let op = self.op_by_id_mut(&id);
assert!(!op.sent_cant_cause_cancel);
op.sent_cant_cause_cancel = true;
}
#[hdl]
fn peek_output_ready(&self) -> SimValue<HdlOption<UnitOutputReady<C>>> {
let ret_ty = HdlOption[UnitOutputReady[self.config]];
for MockL2RegFileOp {
mop,
src_values: _,
dest_value,
sent_cant_cause_cancel: _,
sent_output_ready,
config: _,
} in &self.ops
{
if *sent_output_ready {
continue;
}
if let Some(dest_value) = dest_value {
return #[hdl(sim)]
ret_ty.HdlSome(
#[hdl(sim)]
UnitOutputReady::<_> {
id: &mop.id,
dest_value,
predictor_op: #[hdl(sim)]
NextPcPredictorOp::<_> {
call_stack_op: #[hdl(sim)]
CallStackOp.None(),
cond_br_taken: #[hdl(sim)]
HdlNone(),
config: self.config,
},
},
);
}
}
#[hdl(sim)]
ret_ty.HdlNone()
}
#[hdl]
fn handle_output_ready(&mut self, output_ready: SimValue<UnitOutputReady<C>>) {
#[hdl(sim)]
let UnitOutputReady::<_> {
id,
dest_value: _,
predictor_op: _,
} = output_ready;
let op = self.op_by_id_mut(&id);
assert!(!op.sent_output_ready);
op.sent_output_ready = true;
}
#[hdl]
fn peek_finish_cause_cancel(&self) -> SimValue<HdlOption<UnitFinishCauseCancel<C>>> {
let ret_ty = HdlOption[UnitFinishCauseCancel[self.config]];
if let Some(MockL2RegFileOp {
mop,
src_values: _,
dest_value,
sent_cant_cause_cancel: _,
sent_output_ready: _,
config: _,
}) = self.ops.front()
{
if dest_value.is_some() {
return #[hdl(sim)]
ret_ty.HdlSome(
#[hdl(sim)]
UnitFinishCauseCancel::<_> {
id: &mop.id,
caused_cancel: #[hdl(sim)]
(ret_ty.HdlSome.caused_cancel).HdlNone(),
config: self.config,
},
);
}
}
#[hdl(sim)]
ret_ty.HdlNone()
}
#[hdl]
fn handle_finish_cause_cancel(
&mut self,
finish_cause_cancel: SimValue<UnitFinishCauseCancel<C>>,
) {
#[hdl(sim)]
let UnitFinishCauseCancel::<_> {
id,
caused_cancel: _,
config: _,
} = finish_cause_cancel;
let Some(op) = self.ops.pop_front() else {
unreachable!();
};
assert_eq!(*op.id(), id);
}
fn cancel_all(&mut self) {
let Self {
ops,
l2_regs: _,
config: _,
} = self;
ops.clear();
}
}
#[hdl_module(extern)]
fn mock_l2_reg_file_unit(config: PhantomConst<CpuConfig>, unit_index: usize) {
assert!(
config
.get()
.units
.iter()
.enumerate()
.all(|(i, unit)| (unit_index == i) == (unit.kind == UnitKind::TransformedMove)),
"unit index {unit_index} must be the only L2 register file unit: {config:#?}",
);
#[hdl]
let cd: ClockDomain = m.input();
#[hdl]
let from_execute: ExecuteToUnitInterface<PhantomConst<CpuConfig>> =
m.input(ExecuteToUnitInterface[config]);
#[hdl]
let debug_state: MockL2RegFileUnitDebugState<PhantomConst<CpuConfig>> =
m.output(MockL2RegFileUnitDebugState[config]);
#[hdl]
let started_any: Bool = m.output();
m.register_clock_for_past(cd.clk);
m.extern_module_simulation_fn(
(cd, from_execute, debug_state, started_any, config),
async |args, mut sim| {
let (cd, from_execute, debug_state, started_any, config) = args;
sim.resettable(
cd,
async |mut sim| {
#[hdl]
let ExecuteToUnitInterface::<_> {
enqueue,
inputs_ready: _,
is_no_longer_speculative: _,
cant_cause_cancel,
output_ready,
finish_cause_cancel,
unit_outputs_ready: _,
cancel_all,
config: _,
} = from_execute;
sim.write(enqueue.ready, false).await;
sim.write(cancel_all.ready, false).await;
sim.write(
cant_cause_cancel,
#[hdl(sim)]
(cant_cause_cancel.ty()).HdlNone(),
)
.await;
sim.write(
output_ready,
#[hdl(sim)]
(output_ready.ty()).HdlNone(),
)
.await;
sim.write(
finish_cause_cancel,
#[hdl(sim)]
(finish_cause_cancel.ty()).HdlNone(),
)
.await;
sim.write(
debug_state,
#[hdl(sim)]
MockL2RegFileUnitDebugState::<_> {
ops: zeroed(debug_state.ty().ops),
l2_regs: zeroed(debug_state.ty().l2_regs),
config,
},
)
.await;
sim.write(started_any, false).await;
},
|sim, ()| run_fn(cd, from_execute, debug_state, started_any, config, sim),
)
.await;
},
);
#[hdl]
async fn run_fn(
cd: Expr<ClockDomain>,
from_execute: Expr<ExecuteToUnitInterface<PhantomConst<CpuConfig>>>,
debug_state: Expr<MockL2RegFileUnitDebugState<PhantomConst<CpuConfig>>>,
started_any: Expr<Bool>,
config: PhantomConst<CpuConfig>,
mut sim: ExternModuleSimulationState,
) {
let mut state = MockL2RegFileUnitState::new(config);
loop {
{
#[hdl]
let ExecuteToUnitInterface::<_> {
enqueue,
inputs_ready: _,
is_no_longer_speculative: _,
cant_cause_cancel,
output_ready,
finish_cause_cancel,
unit_outputs_ready: _,
cancel_all,
config: _,
} = from_execute;
sim.write(enqueue.ready, true).await;
sim.write(cancel_all.ready, true).await;
sim.write(cant_cause_cancel, state.peek_mop_cant_cause_cancel())
.await;
sim.write(output_ready, state.peek_output_ready()).await;
sim.write(finish_cause_cancel, state.peek_finish_cause_cancel())
.await;
}
sim.write(debug_state, state.debug_state()).await;
sim.wait_for_clock_edge(cd.clk).await;
{
#[hdl]
let ExecuteToUnitInterface::<_> {
enqueue,
inputs_ready,
is_no_longer_speculative,
cant_cause_cancel,
output_ready,
finish_cause_cancel,
unit_outputs_ready,
cancel_all,
config: _,
} = from_execute;
if sim.read_past_bool(enqueue.ready, cd.clk).await {
#[hdl(sim)]
if let HdlSome(enqueue) = sim.read_past(enqueue.data, cd.clk).await {
state.handle_enqueue(enqueue);
sim.write(started_any, true).await;
}
}
#[hdl(sim)]
if let HdlSome(inputs_ready) = sim.read_past(inputs_ready, cd.clk).await {
state.handle_inputs_ready(inputs_ready);
}
#[hdl(sim)]
if let HdlSome(is_no_longer_speculative) =
sim.read_past(is_no_longer_speculative, cd.clk).await
{
state.handle_mop_is_no_longer_speculative(is_no_longer_speculative);
}
if sim.read_past_bool(unit_outputs_ready, cd.clk).await {
#[hdl(sim)]
if let HdlSome(cant_cause_cancel) =
sim.read_past(cant_cause_cancel, cd.clk).await
{
state.handle_mop_cant_cause_cancel(cant_cause_cancel);
}
#[hdl(sim)]
if let HdlSome(output_ready) = sim.read_past(output_ready, cd.clk).await {
state.handle_output_ready(output_ready);
}
#[hdl(sim)]
if let HdlSome(finish_cause_cancel) =
sim.read_past(finish_cause_cancel, cd.clk).await
{
state.handle_finish_cause_cancel(finish_cause_cancel);
}
}
if sim.read_past_bool(cancel_all.ready, cd.clk).await {
#[hdl(sim)]
if let HdlSome(cancel_all) = sim.read_past(cancel_all.data, cd.clk).await {
let () = *cancel_all;
state.cancel_all();
}
}
}
state.step();
}
}
}
#[hdl(no_static)]
struct MockLoadStoreOpDebugState<C: PhantomConstGet<CpuConfig>> {
mop: MOpInstance<LoadStoreMOp<PRegNum<C>, PRegNum<C>>>,
@ -2885,6 +3420,8 @@ fn rename_execute_retire_test_harness<#[hdl(skip)] MI: MakeInsns>(config: Phanto
#[hdl]
let all_outputs_written: Bool = m.output();
#[hdl]
let started_any_l2_reg_file_ops: Bool = m.output();
#[hdl]
let next_pc = instance(mock_next_pc::<MI>(config));
connect(next_pc.cd, cd);
#[hdl]
@ -2893,35 +3430,44 @@ fn rename_execute_retire_test_harness<#[hdl(skip)] MI: MakeInsns>(config: Phanto
connect(dut.from_post_decode, next_pc.post_decode_output);
connect(next_pc.from_retire, dut.to_next_pc);
connect(all_outputs_written, true);
connect(started_any_l2_reg_file_ops, false);
for (unit_index, to_unit) in ExecuteToUnitInterfaces::unit_fields(dut.to_units)
.into_iter()
.enumerate()
{
if config.get().units[unit_index].kind == UnitKind::LoadStore {
let mock_unit = instance_with_loc(
&dut.ty().to_units.unit_field_name(unit_index),
mock_load_store_unit::<MI>(config, unit_index),
SourceLocation::caller(),
);
connect(mock_unit.cd, cd);
connect(mock_unit.from_execute, to_unit);
#[hdl]
if !mock_unit.all_outputs_written {
connect(all_outputs_written, false);
match config.get().units[unit_index].kind {
UnitKind::LoadStore => {
let mock_unit = instance_with_loc(
&dut.ty().to_units.unit_field_name(unit_index),
mock_load_store_unit::<MI>(config, unit_index),
SourceLocation::caller(),
);
connect(mock_unit.cd, cd);
connect(mock_unit.from_execute, to_unit);
#[hdl]
if !mock_unit.all_outputs_written {
connect(all_outputs_written, false);
}
}
UnitKind::TransformedMove => {
let mock_unit = instance_with_loc(
&dut.ty().to_units.unit_field_name(unit_index),
mock_l2_reg_file_unit(config, unit_index),
SourceLocation::caller(),
);
connect(mock_unit.cd, cd);
connect(mock_unit.from_execute, to_unit);
connect(started_any_l2_reg_file_ops, mock_unit.started_any);
}
UnitKind::AluBranch => {
let mock_unit = instance_with_loc(
&dut.ty().to_units.unit_field_name(unit_index),
mock_unit::<()>(config, unit_index),
SourceLocation::caller(),
);
connect(mock_unit.cd, cd);
connect(mock_unit.from_execute, to_unit);
}
} else {
let mock_unit_module = if is_the_l2_reg_file_unit(config, unit_index) {
mock_unit::<MockL2RegFile>(config, unit_index)
} else {
mock_unit::<()>(config, unit_index)
};
let mock_unit = instance_with_loc(
&dut.ty().to_units.unit_field_name(unit_index),
mock_unit_module,
SourceLocation::caller(),
);
connect(mock_unit.cd, cd);
connect(mock_unit.from_execute, to_unit);
}
}
}
@ -2977,3 +3523,137 @@ fn test_rename_execute_retire_fibonacci() {
panic!();
}
}
struct SlowLoopInsns;
impl SlowLoopInsns {
const CONSTANTS_ADDR: u64 = 0x4000;
const CONSTANTS_COUNT: usize = 16;
const CONSTANTS_STEP: usize = 8;
const LOG2_RESULT_FACTOR: u32 = 2;
}
impl MakeInsns for SlowLoopInsns {
fn make_insns() -> Insns {
let mut b = InsnsBuilder::new();
let slow_loop = b.new_label("slow_loop");
b.power_isa_ld(3, 0, MockMemory::IO_ADDR as i16); // load input
b.power_isa_addi(1, 0, 0x4000); // setup stack pointer
b.power_isa_bl(slow_loop);
b.power_isa_std(3, 0, MockMemory::IO_ADDR as i16); // store output
let done = b.new_defined_label("done");
b.power_isa_b(done);
b.set_pc(0x1000);
b.define_label(slow_loop);
b.power_isa_addi(4, 0, 0); // clear sum
let loop_header = b.new_defined_label("loop_header");
b.power_isa_cmpldi(0, 3, 0);
let loop_done = b.new_label("loop_done");
b.power_isa_beq(loop_done); // if input == 0 goto loop_done
// long sequence of loads to provoke L2 register file store
let start_reg = 5;
assert!(
start_reg + Self::CONSTANTS_COUNT <= 32,
"too many constants to load them all into PowerISA GPRs",
);
for i in 0..Self::CONSTANTS_COUNT {
b.power_isa_ld(
start_reg + i,
0,
(Self::CONSTANTS_ADDR + (Self::CONSTANTS_STEP * i) as u64) as i16,
);
}
for i in 0..Self::CONSTANTS_COUNT {
b.power_isa_add(4, 4, start_reg + i);
}
b.power_isa_addi(3, 3, -1);
b.power_isa_b(loop_header);
b.define_label(loop_done);
b.power_isa_mr(3, 4);
for _ in 0..Self::LOG2_RESULT_FACTOR {
b.power_isa_add(3, 3, 3);
}
b.power_isa_blr(); // return
b.build()
}
fn make_load_store_execution_state() -> MockMemory {
let expected = 0x0123_4567_89AB_CDEF_u64;
let constants: [[u8; Self::CONSTANTS_STEP]; Self::CONSTANTS_COUNT] =
std::array::from_fn(|i| {
let start_bit_index = i * 64 / Self::CONSTANTS_COUNT;
let end_bit_index = (i + 1) * 64 / Self::CONSTANTS_COUNT;
let start_bit = 1u64.unbounded_shl(start_bit_index as u32);
let end_bit = 1u64.unbounded_shl(end_bit_index as u32);
let mask = end_bit.wrapping_sub(start_bit);
(expected & mask).to_le_bytes()
});
let loop_count = 4;
MockMemory::new(
loop_count,
expected * loop_count * 2u64.pow(Self::LOG2_RESULT_FACTOR),
[(Self::CONSTANTS_ADDR, constants.as_flattened())],
)
}
}
#[hdl]
#[test]
fn test_rename_execute_retire_slow_loop() {
let _n = SourceLocation::normalize_files_for_tests();
let mut config = CpuConfig::new(
vec![
UnitConfig::new(UnitKind::AluBranch),
UnitConfig::new(UnitKind::AluBranch),
UnitConfig::new(UnitKind::AluBranch),
UnitConfig::new(UnitKind::AluBranch),
UnitConfig::new(UnitKind::LoadStore),
UnitConfig::new(UnitKind::TransformedMove),
],
NonZeroUsize::new(20).unwrap(),
);
config.fetch_width = NonZeroUsize::new(4).unwrap();
let m = rename_execute_retire_test_harness::<SlowLoopInsns>(PhantomConst::new_sized(config));
let mut sim = Simulation::new(m);
let writer = RcWriter::default();
sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
struct DumpVcdOnDrop {
writer: Option<RcWriter>,
}
impl Drop for DumpVcdOnDrop {
fn drop(&mut self) {
if let Some(mut writer) = self.writer.take() {
let vcd = String::from_utf8(writer.take()).unwrap();
println!("####### VCD:\n{vcd}\n#######");
}
}
}
let mut writer = DumpVcdOnDrop {
writer: Some(writer),
};
sim.write_clock(sim.io().cd.clk, false);
sim.write_reset(sim.io().cd.rst, true);
for cycle in 0..500 {
sim.advance_time(SimDuration::from_nanos(500));
println!("clock tick: {cycle}");
sim.write_clock(sim.io().cd.clk, true);
sim.advance_time(SimDuration::from_nanos(500));
sim.write_clock(sim.io().cd.clk, false);
sim.write_reset(sim.io().cd.rst, false);
}
assert!(sim.read_bool(sim.io().all_outputs_written));
// make sure we're actually testing L2 reg file ops
assert!(sim.read_bool(sim.io().started_any_l2_reg_file_ops));
// FIXME: vcd is just whatever rename_execute_retire does now, which isn't known to be correct
let vcd = String::from_utf8(writer.writer.take().unwrap().take()).unwrap();
println!("####### VCD:\n{vcd}\n#######");
if vcd != include_str!("expected/rename_execute_retire_slow_loop.vcd") {
panic!();
}
}