WIP: completed stages of next-pc logic, still need to combine them into a pipeline

Cargo.lock

@@ -211,6 +211,7 @@ version = "0.1.0"
 dependencies = [
  "fayalite",
  "serde",
+ "simple-mermaid",
 ]
 
 [[package]]
@@ -690,6 +691,12 @@ version = "1.3.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "0fda2ff0d084019ba4d7c6f371c95d8fd75ce3524c3cb8fb653a3023f6323e64"
 
+[[package]]
+name = "simple-mermaid"
+version = "0.2.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "589144a964b4b30fe3a83b4bb1a09e2475aac194ec832a046a23e75bddf9eb29"
+
 [[package]]
 name = "strsim"
 version = "0.11.1"

Cargo.toml

@@ -16,6 +16,7 @@ rust-version = "1.89.0"
 [workspace.dependencies]
 fayalite = { git = "https://git.libre-chip.org/libre-chip/fayalite.git", version = "0.3.0", branch = "master" }
 serde = { version = "1.0.202", features = ["derive"] }
+simple-mermaid = "0.2.0"
 
 [profile.dev]
 opt-level = 1

crates/cpu/Cargo.toml

@@ -17,3 +17,4 @@ version.workspace = true
 [dependencies]
 fayalite.workspace = true
 serde.workspace = true
+simple-mermaid.workspace = true

crates/cpu/src/next_pc/next_pc.mermaid

@@ -0,0 +1,25 @@
+stateDiagram-v2
+    direction LR
+
+    state "Next PC" as next_pc
+    [*] --> next_pc
+
+    state "Fetch/Decode" as fetch_decode
+    next_pc --> fetch_decode
+
+    state "Branch Predictor" as br_pred
+    next_pc --> br_pred
+    br_pred --> next_pc: cancel following
+
+    state "Post-decode" as post_decode
+    fetch_decode --> post_decode
+    br_pred --> post_decode
+    post_decode --> next_pc: cancel following
+
+    state "Rename\nDispatch\nExecute" as execute
+    post_decode --> execute
+
+    state "Retire" as retire
+    execute --> retire
+    retire --> [*]
+    retire --> next_pc: cancel following

crates/cpu/src/reg_alloc.rs

@@ -578,7 +578,8 @@ pub fn reg_alloc(config: &CpuConfig) {
         connect(unit_to_reg_alloc.unit_forwarding_info, unit_forwarding_info);
         connect(
             unit_forwarding_info.unit_output_writes[unit_index],
-            unit_forwarding_info.ty()
+            unit_forwarding_info
+                .ty()
                 .unit_output_writes
                 .element()
                 .HdlNone(),

crates/cpu/src/unit/alu_branch.rs

@@ -272,10 +272,7 @@ pub fn alu_branch(config: &CpuConfig, unit_index: usize) {
     connect(unit_to_reg_alloc, unit_base.unit_to_reg_alloc);
     connect(unit_base.cd, cd);
     connect(unit_base.execute_start.ready, true);
-    connect(
+    connect(unit_base.execute_end, unit_base.execute_end.ty().HdlNone());
-        unit_base.execute_end,
-        unit_base.execute_end.ty().HdlNone(),
-    );
     #[hdl]
     if let HdlSome(execute_start) = ReadyValid::firing_data(unit_base.execute_start) {
         #[hdl]

crates/cpu/src/util/array_vec.rs

@@ -34,6 +34,18 @@ impl<T: Type, N: Size> ArrayVec<T, N> {
             len: 0u8.cast_to(self.len),
         }
     }
+    #[hdl]
+    pub fn new_full_sim(
+        self,
+        elements: impl ToSimValueWithType<ArrayType<T, N>>,
+    ) -> SimValue<Self> {
+        let elements = elements.to_sim_value_with_type(self.elements);
+        #[hdl(sim)]
+        Self {
+            elements,
+            len: self.elements.len().to_sim_value_with_type(self.len),
+        }
+    }
     pub fn element(self) -> T {
         self.elements.element()
     }