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_docs
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change register names to end in _reg by convention
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2024-10-06 18:50:09 -07:00 |
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expr
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add more expr casts
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2024-11-27 01:30:28 -08:00 |
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intern
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initial public commit
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2024-06-10 23:09:13 -07:00 |
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module
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working on deduce_resets
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2024-11-26 21:26:56 -08:00 |
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sim
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WIP adding VCD output
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2024-11-20 22:53:54 -08:00 |
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util
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WIP adding VCD output
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2024-11-20 22:53:54 -08:00 |
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_docs.rs
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add missing copyright headers
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2024-09-22 15:30:05 -07:00 |
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annotations.rs
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make annotations easier to use
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2024-10-01 19:54:17 -07:00 |
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array.rs
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get #[hdl] struct S<A: KnownSize, B: KnownSize> to work
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2024-10-11 17:30:49 -07:00 |
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bundle.rs
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add PhantomData as a hdl bundle
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2024-10-10 20:48:09 -07:00 |
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cli.rs
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always write formal cache json
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2024-11-20 22:51:40 -08:00 |
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clock.rs
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make ClockDomain and Reg generic over reset type
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2024-11-26 20:47:03 -08:00 |
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enum_.rs
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clean up some clippy warnings
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2024-10-07 21:49:18 -07:00 |
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expr.rs
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make ClockDomain and Reg generic over reset type
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2024-11-26 20:47:03 -08:00 |
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firrtl.rs
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make ClockDomain and Reg generic over reset type
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2024-11-26 20:47:03 -08:00 |
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formal.rs
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queue formal proof passes!
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2024-10-03 23:07:14 -07:00 |
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int.rs
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Merge remote-tracking branch 'origin/master' into adding-simulator
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2024-11-26 21:28:22 -08:00 |
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intern.rs
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remove interning contexts
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2024-10-07 21:33:56 -07:00 |
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lib.rs
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WIP adding simulator
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2024-11-20 22:53:54 -08:00 |
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memory.rs
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clean up some clippy warnings
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2024-10-07 21:49:18 -07:00 |
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module.rs
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make ClockDomain and Reg generic over reset type
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2024-11-26 20:47:03 -08:00 |
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prelude.rs
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add Bundle and Enum to prelude
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2024-10-14 17:47:58 -07:00 |
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reg.rs
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make ClockDomain and Reg generic over reset type
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2024-11-26 20:47:03 -08:00 |
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reset.rs
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make ClockDomain and Reg generic over reset type
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2024-11-26 20:47:03 -08:00 |
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sim.rs
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make ClockDomain and Reg generic over reset type
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2024-11-26 20:47:03 -08:00 |
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source_location.rs
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reformat messy code that rustfmt doesn't format
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2024-07-10 23:34:41 -07:00 |
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testing.rs
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queue formal proof passes!
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2024-10-03 23:07:14 -07:00 |
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ty.rs
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remove interning contexts
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2024-10-07 21:33:56 -07:00 |
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util.rs
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WIP adding VCD output
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2024-11-20 22:53:54 -08:00 |
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wire.rs
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simple combinatorial simulation works!
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2024-11-20 22:53:54 -08:00 |
