243 commits

Author	SHA1	Message	Date
Jacob Lifshay	edcc5927a5	don't cache external job failures if they could be caused by the user killing processes	2025-10-24 02:27:20 -07:00
Jacob Lifshay	7dc4417874	add test_many_memories so we catch if memories are iterated in an inconsistent order like in 838bd469ce	2025-10-24 01:40:30 -07:00
Jacob Lifshay	838bd469ce	change SimulationImpl::trace_memories to a BTreeMap for consistent iteration order	2025-10-24 00:53:13 -07:00
Jacob Lifshay	b6e4cd0614	move FormalMode to crate::testing and add to prelude	2025-10-24 00:14:04 -07:00
Jacob Lifshay	3e5b2f126a	make UIntInRange[Inclusive][Type] castable from/to any UInt<N> and add methods to get bit_width, start, and end	2025-10-23 23:52:41 -07:00
Jacob Lifshay	b3cc28e2b6	add transmit-only UART example	2025-10-22 20:11:02 -07:00
Jacob Lifshay	26840daf13	arty_a7: add divided clocks as available input peripherals so you're not stuck with 100MHz	2025-10-22 20:11:02 -07:00
Jacob Lifshay	c6feea6d51	properly handle all XilinxAnnotations, this makes nextpnr-xilinx properly pick up the clock frequency	2025-10-21 22:24:02 -07:00
Jacob Lifshay	409992961c	switch to using verilog for reset synchronizer so we can use attributes on FDPE instances	2025-10-21 22:24:02 -07:00
Jacob Lifshay	2bdc8a7c72	WIP adding xdc create_clock -- nextpnr-xilinx currently ignores it	2025-10-19 23:13:28 -07:00
Jacob Lifshay	477a1f2d29	Add peripherals and Arty A7 platforms -- blinky works correctly now on arty-a7-100t!	2025-10-19 23:13:28 -07:00
Jacob Lifshay	4d54f903be	move vendor module to top level	2025-10-17 15:00:19 -07:00
Jacob Lifshay	3f5dd61e46	WIP adding Platform	2025-10-17 05:55:22 -07:00
Jacob Lifshay	def406ab52	group all xilinx annotations together	2025-10-16 04:53:58 -07:00
Jacob Lifshay	a565be1b09	do some clean up	2025-10-16 04:32:56 -07:00
Jacob Lifshay	676c1e3b7d	WIP adding annotations for generating the .xdc file for yosys-nextpnr-prjxray	2025-10-15 04:29:00 -07:00
Jacob Lifshay	8a63ea89d0	WIP adding yosys-nextpnr-xray xilinx fpga toolchain -- blinky works on arty a7 100t (except for inverted reset)	2025-10-15 04:29:00 -07:00
Jacob Lifshay	42e3179a60	change cache directory name to be fayalite-specific	2025-10-15 04:29:00 -07:00
Jacob Lifshay	53ae3ff670	mark create-unix-shell-script as incomplete in CLI	2025-10-15 04:29:00 -07:00
Jacob Lifshay	7af9abfb6f	switch to using new crate::build system	2025-10-15 04:29:00 -07:00
Jacob Lifshay	aacd05378f	WIP converting from cli.rs to build/*.rs	2025-10-15 04:29:00 -07:00
Jacob Lifshay	908ccef674	added automatically-added dependencies; added caching for external jobs	2025-10-15 04:29:00 -07:00
Jacob Lifshay	057670c12a	WIP adding FPGA support -- build module should be complete	2025-10-15 04:29:00 -07:00
Jacob Lifshay	f8ac78abd6	Remove extraneous #[automatically_derived] annotations that are causing warnings as reported by Tobias	2025-10-15 04:17:47 -07:00
Jacob Lifshay	db9b1c202c	add simulator support for sim-only values	2025-09-08 22:19:43 -07:00
Jacob Lifshay	b5b1ee866c	converted to using get_state_part_kinds!	2025-09-05 19:10:06 -07:00
Jacob Lifshay	f0e3aef061	add get_state_part_kinds! macro	2025-09-05 19:07:07 -07:00
Jacob Lifshay	6d36698adf	move public paths of sim::{Compiled,Compiler} to sim::compiler	2025-08-26 19:23:21 -07:00
Jacob Lifshay	e7e831cf00	split out simulator compiler into a separate module	2025-08-26 19:17:21 -07:00
Jacob Lifshay	4008c311bf	format code after switching to edition 2024	2025-08-24 16:35:21 -07:00
Jacob Lifshay	ae7c4be9dc	remove get_many_mut since it was stabilized in std as get_disjoint_mut	2025-08-24 15:53:21 -07:00
Jacob Lifshay	65f9ab32f4	switch to edition 2024	2025-08-24 15:53:21 -07:00
Jacob Lifshay	67e66ac3bd	upgrade to rust 1.89.0	2025-08-24 15:53:21 -07:00
Jacob Lifshay	91e1b619e8	switch to petgraph 0.8.1 now that my PR was merged and released to crates.io	2025-04-09 20:48:40 -07:00
Jacob Lifshay	e2d2d4110b	upgrade hashbrown to 0.15.2	2025-04-09 20:33:21 -07:00
Jacob Lifshay	b1f9706e4e	add custom hasher for testing	2025-04-09 20:27:22 -07:00
Jacob Lifshay	4eda4366c8	check types in debug mode in impl Debug for Expr, helping to catch bugs	2025-04-09 20:23:19 -07:00
Jacob Lifshay	122c08d3cf	add fake which for miri	2025-04-09 20:21:43 -07:00
Jacob Lifshay	b08a747e20	switch to using type aliases for HashMap/HashSet to allow easily switching hashers	2025-04-09 20:17:46 -07:00
Jacob Lifshay	e0c9939147	add test that SimValue can't be interned, since its PartialEq may ignore types	2025-04-09 19:55:09 -07:00
Jacob Lifshay	07725ab489	switch interning to use HashTable rather than HashMap	2025-04-09 19:30:02 -07:00
Jacob Lifshay	36f1b9bbb6	add derive(Debug) to all types that are interned	2025-04-09 19:24:08 -07:00
Jacob Lifshay	9a1b047d2f	change TypeIdMap to not use any unsafe code	2025-04-09 16:25:56 -07:00
Jacob Lifshay	5967e812a2	fix [SU]IntValue's PartialEq for interning ... different widths must make values compare not equal otherwise interning will e.g. substitute a 0x0_u8 for a 0x0_u2	2025-04-08 21:57:56 -07:00
Jacob Lifshay	001fd31451	add UIntInRange[Inclusive][Type]	2025-04-07 18:27:54 -07:00
Jacob Lifshay	57aae7b7fb	implement [de]serializing BaseTypes, SimValues, and support PhantomConst<T> in #[hdl] struct S<T>	2025-04-04 01:04:26 -07:00
Jacob Lifshay	6929352be7	re-export bitvec and add types useful for simulation to the prelude	2025-04-03 16:01:39 -07:00
Jacob Lifshay	62058dc141	fix cargo doc warnings -- convert urls to auto links	2025-04-01 22:22:54 -07:00
Jacob Lifshay	c4b6a0fee6	add support for #[hdl(sim)] enum_ty.Variant(value) and #[hdl(sim)] EnumTy::Variant(value) and non-sim variants too	2025-04-01 22:16:47 -07:00
Jacob Lifshay	9092e45447	fix #[hdl(sim)] match on enums	2025-03-30 01:25:07 -07:00