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increase memory bandwidth and size

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This commit is contained in:
Tobias Alexandra Platen 2025-10-19 10:26:26 +02:00
parent 672a29e76d
commit 8433f4f150
3 changed files with 35 additions and 29 deletions
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2
crates/cpu/src/lib.rs
View file

@ -7,4 +7,4 @@ pub mod register;
pub mod unit; pub mod unit;
pub mod util; pub mod util;
//TODO read other modules //TODO read other modules
pub mod main_memory; pub mod main_memory;

36
crates/cpu/src/main_memory.rs
View file

@ -26,45 +26,35 @@ pub fn main_memory(config: &CpuConfig) {
#[hdl] #[hdl]
let addr: UInt<64> = m.input(); let addr: UInt<64> = m.input();
#[hdl] #[hdl]
let read_data: UInt<8> = m.output(); let read_data: UInt<64> = m.output();
#[hdl] #[hdl]
let en: Bool = m.input(); let en: Bool = m.input();
// add write support
//WIP: add write support
#[hdl] #[hdl]
let write_en: Bool = m.input(); let write_en: Bool = m.input();
#[hdl] #[hdl]
let write_data: UInt<8> = m.input(); let write_data: UInt<64> = m.input();
#[hdl] #[hdl]
let cd: ClockDomain = m.input(); let cd: ClockDomain = m.input();
// for each instance do
// connect(instance.cd, cd);
#[hdl] #[hdl] // FIXME: do not hardcode memory size and content --
//let mut mem = memory_with_init([0x12u8, 0x34, 0x56, 0x78]); //let mut my_memory = memory_with_init([0x12_hdl_u8, 0x34_hdl_u8, 0x56_hdl_u8, 0x78_hdl_u8]);
let mut my_memory = memory_with_init([0x12_hdl_u8, 0x34_hdl_u8, 0x56_hdl_u8, 0x78_hdl_u8]); let mut my_memory = memory();
my_memory.depth(256); //TODO make configurable
let read_port = my_memory.new_read_port(); let read_port = my_memory.new_read_port();
// note that `read_addr` is `UInt<2>` since the memory only has 4 elements connect_any(read_port.addr, addr);
//need to connect addr en clk and data->out connect_any(read_port.en, addr.cmp_lt(256u64) & en); // and not write_en
connect_any(read_port.addr, addr); //FIXME
connect_any(read_port.en, addr.cmp_lt(4u64));
connect(read_port.clk, cd.clk); connect(read_port.clk, cd.clk);
connect(read_data, read_port.data); connect(read_data, read_port.data);
let write_port = my_memory.new_write_port(); let write_port = my_memory.new_write_port();
connect_any(write_port.addr, addr); connect_any(write_port.addr, addr);
connect_any(write_port.en, addr.cmp_lt(4u64) & write_en); connect_any(write_port.en, addr.cmp_lt(256u64) & en & write_en);
connect_any(write_port.data, write_data); connect_any(write_port.data, write_data);
connect(write_port.clk, cd.clk); connect(write_port.clk, cd.clk);
//connect_any(write_port.mask, 0xFFu8); //try that one
connect_any(write_port.mask, true); connect_any(write_port.mask, true); //can only write 8 bits at a time
} }
// see https://git.libre-chip.org/libre-chip/fayalite/src/branch/master/crates/fayalite/tests/sim.rs
// how to write testbenches
// start with a very simple memory model ->
// TODO create a branch for the memory
// 1 connect up the read port, add write later
// ask how I make the memory pipelined later ... not today

26
crates/cpu/tests/main_memory.rs
View file

@ -42,7 +42,7 @@ fn test_main_memory() {
sim.write(sim.io().cd.rst, false); sim.write(sim.io().cd.rst, false);
sim.write(sim.io().cd.clk, false); sim.write(sim.io().cd.clk, false);
sim.write(sim.io().write_en, false); sim.write(sim.io().write_en, false);
sim.write(sim.io().write_data, 0xFFu8); sim.write(sim.io().write_data, 0xFF00FF00FF00FF00u64);
// TODO convert to for loop // TODO convert to for loop
// you need to write an initial value to all inputs before you can start running the simulation // you need to write an initial value to all inputs before you can start running the simulation
@ -60,16 +60,32 @@ fn test_main_memory() {
sim.write(sim.io().write_en, true); sim.write(sim.io().write_en, true);
sim.write(sim.io().addr, 0u64); sim.write(sim.io().addr, 0u64);
sim.write(sim.io().write_data, 0x11u8); sim.write(sim.io().write_data, 0xFFFFFFFFFFFFFFFFu64); //fill with ones
sim.write_clock(sim.io().cd.clk, true);
sim.advance_time(SimDuration::from_micros(1)); sim.advance_time(SimDuration::from_micros(1));
sim.write_clock(sim.io().cd.clk, false);
sim.advance_time(SimDuration::from_micros(1));
sim.write(sim.io().addr, 1u64); sim.write(sim.io().addr, 1u64);
sim.write(sim.io().write_data, 0x22u8);
sim.write_clock(sim.io().cd.clk, true);
sim.advance_time(SimDuration::from_micros(1)); sim.advance_time(SimDuration::from_micros(1));
sim.write_clock(sim.io().cd.clk, false);
sim.advance_time(SimDuration::from_micros(1));
sim.write(sim.io().addr, 2u64); sim.write(sim.io().addr, 2u64);
sim.write(sim.io().write_data, 0x33u8);
sim.write_clock(sim.io().cd.clk, true);
sim.advance_time(SimDuration::from_micros(1)); sim.advance_time(SimDuration::from_micros(1));
sim.write_clock(sim.io().cd.clk, false);
sim.advance_time(SimDuration::from_micros(1));
sim.write(sim.io().addr, 3u64); sim.write(sim.io().addr, 3u64);
sim.write(sim.io().write_data, 0x44u8);
sim.write_clock(sim.io().cd.clk, true);
sim.advance_time(SimDuration::from_micros(1));
sim.write_clock(sim.io().cd.clk, false);
sim.advance_time(SimDuration::from_micros(1)); sim.advance_time(SimDuration::from_micros(1));
sim.flush_traces().unwrap(); // make sure everything is written to the output file sim.flush_traces().unwrap(); // make sure everything is written to the output file