From 8433f4f1507a123aa95929ae317ce848533ffde5 Mon Sep 17 00:00:00 2001 From: Tobias Alexandra Platen Date: Sun, 19 Oct 2025 10:26:26 +0200 Subject: [PATCH] increase memory bandwidth and size --- crates/cpu/src/lib.rs | 2 +- crates/cpu/src/main_memory.rs | 36 ++++++++++++--------------------- crates/cpu/tests/main_memory.rs | 26 +++++++++++++++++++----- 3 files changed, 35 insertions(+), 29 deletions(-) diff --git a/crates/cpu/src/lib.rs b/crates/cpu/src/lib.rs index c6fd36c..575357b 100644 --- a/crates/cpu/src/lib.rs +++ b/crates/cpu/src/lib.rs @@ -7,4 +7,4 @@ pub mod register; pub mod unit; pub mod util; //TODO read other modules -pub mod main_memory; +pub mod main_memory; diff --git a/crates/cpu/src/main_memory.rs b/crates/cpu/src/main_memory.rs index 1719927..b933cb9 100644 --- a/crates/cpu/src/main_memory.rs +++ b/crates/cpu/src/main_memory.rs @@ -26,45 +26,35 @@ pub fn main_memory(config: &CpuConfig) { #[hdl] let addr: UInt<64> = m.input(); #[hdl] - let read_data: UInt<8> = m.output(); + let read_data: UInt<64> = m.output(); #[hdl] let en: Bool = m.input(); - // add write support + + //WIP: add write support #[hdl] let write_en: Bool = m.input(); #[hdl] - let write_data: UInt<8> = m.input(); + let write_data: UInt<64> = m.input(); #[hdl] let cd: ClockDomain = m.input(); - // for each instance do - // connect(instance.cd, cd); - #[hdl] - //let mut mem = memory_with_init([0x12u8, 0x34, 0x56, 0x78]); - let mut my_memory = memory_with_init([0x12_hdl_u8, 0x34_hdl_u8, 0x56_hdl_u8, 0x78_hdl_u8]); + #[hdl] // FIXME: do not hardcode memory size and content -- + //let mut my_memory = memory_with_init([0x12_hdl_u8, 0x34_hdl_u8, 0x56_hdl_u8, 0x78_hdl_u8]); + let mut my_memory = memory(); + my_memory.depth(256); //TODO make configurable let read_port = my_memory.new_read_port(); - // note that `read_addr` is `UInt<2>` since the memory only has 4 elements - //need to connect addr en clk and data->out - connect_any(read_port.addr, addr); //FIXME - connect_any(read_port.en, addr.cmp_lt(4u64)); + connect_any(read_port.addr, addr); + connect_any(read_port.en, addr.cmp_lt(256u64) & en); // and not write_en connect(read_port.clk, cd.clk); connect(read_data, read_port.data); let write_port = my_memory.new_write_port(); connect_any(write_port.addr, addr); - connect_any(write_port.en, addr.cmp_lt(4u64) & write_en); + connect_any(write_port.en, addr.cmp_lt(256u64) & en & write_en); connect_any(write_port.data, write_data); connect(write_port.clk, cd.clk); - //connect_any(write_port.mask, 0xFFu8); //try that one - connect_any(write_port.mask, true); + + connect_any(write_port.mask, true); //can only write 8 bits at a time } - -// see https://git.libre-chip.org/libre-chip/fayalite/src/branch/master/crates/fayalite/tests/sim.rs -// how to write testbenches -// start with a very simple memory model -> -// TODO create a branch for the memory - -// 1 connect up the read port, add write later -// ask how I make the memory pipelined later ... not today diff --git a/crates/cpu/tests/main_memory.rs b/crates/cpu/tests/main_memory.rs index d558c79..7ac85a2 100644 --- a/crates/cpu/tests/main_memory.rs +++ b/crates/cpu/tests/main_memory.rs @@ -42,7 +42,7 @@ fn test_main_memory() { sim.write(sim.io().cd.rst, false); sim.write(sim.io().cd.clk, false); sim.write(sim.io().write_en, false); - sim.write(sim.io().write_data, 0xFFu8); + sim.write(sim.io().write_data, 0xFF00FF00FF00FF00u64); // TODO convert to for loop // you need to write an initial value to all inputs before you can start running the simulation @@ -60,16 +60,32 @@ fn test_main_memory() { sim.write(sim.io().write_en, true); sim.write(sim.io().addr, 0u64); - sim.write(sim.io().write_data, 0x11u8); + sim.write(sim.io().write_data, 0xFFFFFFFFFFFFFFFFu64); //fill with ones + + sim.write_clock(sim.io().cd.clk, true); sim.advance_time(SimDuration::from_micros(1)); + sim.write_clock(sim.io().cd.clk, false); + sim.advance_time(SimDuration::from_micros(1)); + sim.write(sim.io().addr, 1u64); - sim.write(sim.io().write_data, 0x22u8); + + sim.write_clock(sim.io().cd.clk, true); sim.advance_time(SimDuration::from_micros(1)); + sim.write_clock(sim.io().cd.clk, false); + sim.advance_time(SimDuration::from_micros(1)); + sim.write(sim.io().addr, 2u64); - sim.write(sim.io().write_data, 0x33u8); + + sim.write_clock(sim.io().cd.clk, true); sim.advance_time(SimDuration::from_micros(1)); + sim.write_clock(sim.io().cd.clk, false); + sim.advance_time(SimDuration::from_micros(1)); + sim.write(sim.io().addr, 3u64); - sim.write(sim.io().write_data, 0x44u8); + + sim.write_clock(sim.io().cd.clk, true); + sim.advance_time(SimDuration::from_micros(1)); + sim.write_clock(sim.io().cd.clk, false); sim.advance_time(SimDuration::from_micros(1)); sim.flush_traces().unwrap(); // make sure everything is written to the output file