update fayalite for libre-chip/fayalite#68 change vcd output to have module contents under instance's name

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This commit is contained in:

Jacob Lifshay 2026-03-26 19:21:52 -07:00

parent a1147f0f05

commit 6ed04c809e

Signed by: programmerjake

SSH key fingerprint: SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ

10 changed files with 482113 additions and 958901 deletions

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16705

crates/cpu/tests/expected/fetch.vcd generated

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crates/cpu/tests/expected/main_memory_and_io.vcd generated

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crates/cpu/tests/expected/memory_interface_adapter_no_split.vcd generated

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crates/cpu/tests/expected/next_pc.vcd generated

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crates/cpu/tests/expected/receiver_and_uart_clock_gen.vcd generated

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crates/cpu/tests/expected/receiver_no_queue_and_uart_clock_gen.vcd generated

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crates/cpu/tests/expected/reg_alloc.vcd generated

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crates/cpu/tests/expected/simple_uart.vcd generated

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crates/cpu/tests/expected/transmitter_and_uart_clock_gen.vcd generated

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