run cargo fmt on main_memory

crates/cpu/src/main_memory.rs

@@ -40,7 +40,6 @@ pub fn main_memory(config: &CpuConfig) {
     // for each instance do
     // connect(instance.cd, cd);
 
-    
     #[hdl]
     //let mut mem = memory_with_init([0x12u8, 0x34, 0x56, 0x78]);
     let mut my_memory = memory_with_init([0x12_hdl_u8, 0x34_hdl_u8, 0x56_hdl_u8, 0x78_hdl_u8]);
@@ -60,12 +59,6 @@ pub fn main_memory(config: &CpuConfig) {
     connect(write_port.clk, cd.clk);
     //connect_any(write_port.mask, 0xFFu8); //try that one
     connect_any(write_port.mask, true);
-    
-    
-
-    
-
-
 }
 
 // see https://git.libre-chip.org/libre-chip/fayalite/src/branch/master/crates/fayalite/tests/sim.rs

crates/cpu/tests/main_memory.rs

@@ -4,10 +4,10 @@
 use cpu::{
     config::{CpuConfig, UnitConfig},
     instruction::{AddSubMOp, LogicalMOp, MOp, MOpDestReg, MOpRegNum, OutputIntegerMode},
+    main_memory::main_memory,
     reg_alloc::{FetchedDecodedMOp, reg_alloc},
     register::{FlagsMode, PRegFlagsPowerISA},
     unit::{GlobalState, UnitKind},
-    main_memory::main_memory,
 };
 use fayalite::{
     assert_export_firrtl,
@@ -52,7 +52,6 @@ fn test_main_memory() {
 
     dbg!(sim.read(sim.io().read_data)); // dbg! macro just displays the value you pass to it
 
-   
     for n in 0u64..4u64 {
         sim.write(sim.io().addr, n);
         // now wait 1us because why not
@@ -73,8 +72,5 @@ fn test_main_memory() {
     sim.write(sim.io().write_data, 0x44u8);
     sim.advance_time(SimDuration::from_micros(1));
 
-    
-
-
     sim.flush_traces().unwrap(); // make sure everything is written to the output file
 }