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run cargo fmt on main_memory

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This commit is contained in:
Tobias Alexandra Platen 2025-10-14 20:11:24 +02:00
parent 35ea85d074
commit 672a29e76d
2 changed files with 20 additions and 31 deletions
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23
crates/cpu/src/main_memory.rs
View file

@ -34,14 +34,13 @@ pub fn main_memory(config: &CpuConfig) {
let write_en: Bool = m.input(); let write_en: Bool = m.input();
#[hdl] #[hdl]
let write_data: UInt<8> = m.input(); let write_data: UInt<8> = m.input();
#[hdl] #[hdl]
let cd: ClockDomain = m.input(); let cd: ClockDomain = m.input();
// for each instance do // for each instance do
// connect(instance.cd, cd); // connect(instance.cd, cd);
#[hdl]
#[hdl]
//let mut mem = memory_with_init([0x12u8, 0x34, 0x56, 0x78]); //let mut mem = memory_with_init([0x12u8, 0x34, 0x56, 0x78]);
let mut my_memory = memory_with_init([0x12_hdl_u8, 0x34_hdl_u8, 0x56_hdl_u8, 0x78_hdl_u8]); let mut my_memory = memory_with_init([0x12_hdl_u8, 0x34_hdl_u8, 0x56_hdl_u8, 0x78_hdl_u8]);
@ -51,8 +50,8 @@ pub fn main_memory(config: &CpuConfig) {
connect_any(read_port.addr, addr); //FIXME connect_any(read_port.addr, addr); //FIXME
connect_any(read_port.en, addr.cmp_lt(4u64)); connect_any(read_port.en, addr.cmp_lt(4u64));
connect(read_port.clk, cd.clk); connect(read_port.clk, cd.clk);
connect(read_data,read_port.data); connect(read_data, read_port.data);
let write_port = my_memory.new_write_port(); let write_port = my_memory.new_write_port();
connect_any(write_port.addr, addr); connect_any(write_port.addr, addr);
connect_any(write_port.en, addr.cmp_lt(4u64) & write_en); connect_any(write_port.en, addr.cmp_lt(4u64) & write_en);
@ -60,18 +59,12 @@ pub fn main_memory(config: &CpuConfig) {
connect(write_port.clk, cd.clk); connect(write_port.clk, cd.clk);
//connect_any(write_port.mask, 0xFFu8); //try that one //connect_any(write_port.mask, 0xFFu8); //try that one
connect_any(write_port.mask, true); connect_any(write_port.mask, true);
} }
// see https://git.libre-chip.org/libre-chip/fayalite/src/branch/master/crates/fayalite/tests/sim.rs // see https://git.libre-chip.org/libre-chip/fayalite/src/branch/master/crates/fayalite/tests/sim.rs
// how to write testbenches // how to write testbenches
// start with a very simple memory model -> // start with a very simple memory model ->
// TODO create a branch for the memory // TODO create a branch for the memory
// 1 connect up the read port, add write later // 1 connect up the read port, add write later
// ask how I make the memory pipelined later ... not today // ask how I make the memory pipelined later ... not today

28
crates/cpu/tests/main_memory.rs
View file

@ -4,10 +4,10 @@
use cpu::{ use cpu::{
config::{CpuConfig, UnitConfig}, config::{CpuConfig, UnitConfig},
instruction::{AddSubMOp, LogicalMOp, MOp, MOpDestReg, MOpRegNum, OutputIntegerMode}, instruction::{AddSubMOp, LogicalMOp, MOp, MOpDestReg, MOpRegNum, OutputIntegerMode},
main_memory::main_memory,
reg_alloc::{FetchedDecodedMOp, reg_alloc}, reg_alloc::{FetchedDecodedMOp, reg_alloc},
register::{FlagsMode, PRegFlagsPowerISA}, register::{FlagsMode, PRegFlagsPowerISA},
unit::{GlobalState, UnitKind}, unit::{GlobalState, UnitKind},
main_memory::main_memory,
}; };
use fayalite::{ use fayalite::{
assert_export_firrtl, assert_export_firrtl,
@ -51,30 +51,26 @@ fn test_main_memory() {
sim.advance_time(SimDuration::from_micros(1)); //panic here at simulation sim.advance_time(SimDuration::from_micros(1)); //panic here at simulation
dbg!(sim.read(sim.io().read_data)); // dbg! macro just displays the value you pass to it dbg!(sim.read(sim.io().read_data)); // dbg! macro just displays the value you pass to it
for n in 0u64..4u64 { for n in 0u64..4u64 {
sim.write(sim.io().addr, n); sim.write(sim.io().addr, n);
// now wait 1us because why not // now wait 1us because why not
sim.advance_time(SimDuration::from_micros(1)); sim.advance_time(SimDuration::from_micros(1));
} }
sim.write(sim.io().write_en, true); sim.write(sim.io().write_en, true);
sim.write(sim.io().addr, 0u64); sim.write(sim.io().addr, 0u64);
sim.write(sim.io().write_data, 0x11u8); sim.write(sim.io().write_data, 0x11u8);
sim.advance_time(SimDuration::from_micros(1)); sim.advance_time(SimDuration::from_micros(1));
sim.write(sim.io().addr, 1u64); sim.write(sim.io().addr, 1u64);
sim.write(sim.io().write_data, 0x22u8); sim.write(sim.io().write_data, 0x22u8);
sim.advance_time(SimDuration::from_micros(1)); sim.advance_time(SimDuration::from_micros(1));
sim.write(sim.io().addr, 2u64); sim.write(sim.io().addr, 2u64);
sim.write(sim.io().write_data, 0x33u8); sim.write(sim.io().write_data, 0x33u8);
sim.advance_time(SimDuration::from_micros(1)); sim.advance_time(SimDuration::from_micros(1));
sim.write(sim.io().addr, 3u64); sim.write(sim.io().addr, 3u64);
sim.write(sim.io().write_data, 0x44u8); sim.write(sim.io().write_data, 0x44u8);
sim.advance_time(SimDuration::from_micros(1)); sim.advance_time(SimDuration::from_micros(1));
sim.flush_traces().unwrap(); // make sure everything is written to the output file sim.flush_traces().unwrap(); // make sure everything is written to the output file
} }