forked from libre-chip/cpu
		
	use for loop in unit test
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					 1 changed files with 10 additions and 1 deletions
				
			
		|  | @ -49,7 +49,16 @@ fn test_main_memory() { | |||
|     sim.advance_time(SimDuration::from_micros(1)); //panic here at simulation
 | ||||
| 
 | ||||
|     dbg!(sim.read(sim.io().read_data)); // dbg! macro just displays the value you pass to it
 | ||||
|     
 | ||||
|    
 | ||||
|     for n in 0u64..4u64 { | ||||
|         sim.write(sim.io().addr, n); | ||||
| 		// now wait 1us because why not
 | ||||
| 		sim.advance_time(SimDuration::from_micros(1)); | ||||
|     } | ||||
|     
 | ||||
|     
 | ||||
| 
 | ||||
| 
 | ||||
|     sim.flush_traces().unwrap(); // make sure everything is written to the output file
 | ||||
| } | ||||
| } | ||||
|  |  | |||
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