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more work on test case

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This commit is contained in:
Tobias Alexandra Platen 2025-10-05 12:11:27 +02:00
parent 9f68cbb953
commit 540a91878c
2 changed files with 28 additions and 36 deletions
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3
crates/cpu/src/main_memory.rs
View file

@ -44,9 +44,10 @@ pub fn main_memory(config: &CpuConfig) {
// note that `read_addr` is `UInt<2>` since the memory only has 4 elements
//need to connect addr en clk and data->out
connect_any(read_port.addr, addr); //FIXME
connect(read_port.en, en);
connect_any(read_port.en, addr.cmp_lt(4u64));
connect(read_port.clk, cd.clk);
connect(read_data,read_port.data);

61
crates/cpu/tests/main_memory.rs
View file

@ -18,11 +18,9 @@ use fayalite::{
};
use std::num::NonZeroUsize;
#[hdl]
//new test - much simpler
#[test]
fn test_main_memory() {
// see reg_alloc.rs for reference
let _n = SourceLocation::normalize_files_for_tests();
let mut config = CpuConfig::new(
vec![
UnitConfig::new(UnitKind::AluBranch),
@ -30,35 +28,28 @@ fn test_main_memory() {
],
NonZeroUsize::new(20).unwrap(),
);
config.fetch_width = NonZeroUsize::new(2).unwrap(); //unchanged for now
let m = main_memory(&config);
let mut sim = Simulation::new(m);
let mut writer = RcWriter::default();
sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
sim.write_clock(sim.io().cd.clk, false);
sim.write_reset(sim.io().cd.rst, true);
//TODO sim.write_bool
//TODO sim.write(
//footer for tests
// FIXME: vcd is just whatever reg_alloc does now, which isn't known to be correct
let vcd = String::from_utf8(writer.take()).unwrap();
println!("####### VCD:\n{vcd}\n#######");
//if vcd != include_str!("expected/reg_alloc.vcd") { //FIXME panic on result compare
// panic!(); //test is incomplete here, getting panic
//}
// #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
// assert_export_firrtl! {
// m =>
// options: ExportOptions {
// simplify_enums: None,
// ..ExportOptions::default()
// },
// "/test/reg_alloc.fir": "",
// };
// let sim_debug = format!("{sim:#?}");
// println!("#######\n{sim_debug}\n#######");
// if sim_debug != include_str!("expected/reg_alloc.txt") {
// panic!();
// }
}
// create a simulation from main_memory()
let mut sim = Simulation::new(main_memory(&config));
// add a .vcd writer that writes to main_memory.vcd -- this is simple for demo purposes,
// but for our actual code we should do better than just writing
// to main_memory.vcd in the repository's root
//WRONG: sim.add_trace_writer(std::fs::File::create("main_memory.vcd").unwrap());
let out_file = std::fs::File::create("main_memory.vcd").unwrap();
sim.add_trace_writer(VcdWriterDecls::new(out_file));
sim.write(sim.io().en, true);
sim.write(sim.io().cd.rst, false);
sim.write(sim.io().cd.clk, false);
// TODO convert to for loop
// you need to write an initial value to all inputs before you can start running the simulation
sim.write(sim.io().addr, 0x12345u64);
// now wait 1us because why not
sim.advance_time(SimDuration::from_micros(1)); //panic here at simulation
dbg!(sim.read(sim.io().read_data)); // dbg! macro just displays the value you pass to it
sim.flush_traces().unwrap(); // make sure everything is written to the output file
}