forked from libre-chip/website
add WIP CPU architecture draft proposal
This commit is contained in:
parent
0442390142
commit
e9aaaec5f1
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@ -13,8 +13,10 @@ jobs:
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- uses: https://code.forgejo.org/actions/checkout@v3
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with:
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fetch-depth: 0
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- name: Install latest mdbook
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- name: Install dependencies
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run: |
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apt-get update -qq
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apt-get install -qq dia python3
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scripts/install_deps.sh
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echo "`pwd`"/bin >> $GITHUB_PATH
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- name: Build Book
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3
.gitignore
vendored
3
.gitignore
vendored
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@ -1,3 +1,4 @@
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book
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/*.tar.gz
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/mermaid.min.js
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/mermaid.min.js
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*.dia.svg
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@ -14,6 +14,9 @@ edition = "2021"
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[preprocessor.mermaid]
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command = "mdbook-mermaid"
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[preprocessor.dia]
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command = "scripts/mdbook-dia.py"
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[output.html]
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mathjax-support = true
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no-section-label = true
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@ -25,4 +28,8 @@ additional-css = ["src/custom.css"]
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additional-js = ["mermaid.min.js", "mermaid-init.js"]
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[output.html.print]
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enable = false
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enable = false
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[output.html.fold]
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enable = true
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level = 1
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26
scripts/mdbook-dia.py
Executable file
26
scripts/mdbook-dia.py
Executable file
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@ -0,0 +1,26 @@
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#!/usr/bin/env python3
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import json
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import sys
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import os
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import subprocess
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from pathlib import Path
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def main():
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if len(sys.argv) > 1:
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if sys.argv[1] == "supports":
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sys.exit(0)
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sys.exit(1)
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out = sys.stdout
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sys.stdout = sys.stderr
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context, book = json.load(sys.stdin)
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src: Path = Path(context["root"]) / context["config"]["book"]["src"]
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for root, dirs, files in os.walk(src):
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for file in files:
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file = Path(root) / file
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if file.suffix == ".dia":
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out_file = file.with_suffix(".dia.svg")
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subprocess.run(["dia", "-n", "-e", out_file, file], check=True)
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print(json.dumps(book), file=out)
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if __name__ == "__main__":
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main()
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@ -1,4 +1,5 @@
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* [Libre-Chip](README.md)
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* [Proposal for Libre-Chip's First CPU Architecture (Draft)](first_arch/index.md)
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* [Conduct](Conduct.md)
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* [License](LICENSE.md)
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* [GPL 3.0](gpl-3.0.md)
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145
src/first_arch/architecture.dia
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145
src/first_arch/architecture.dia
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@ -0,0 +1,145 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<dia:diagram xmlns:dia="http://www.lysator.liu.se/~alla/dia/">
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<dia:diagramdata>
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<dia:attribute name="background">
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<dia:color val="#ffffffff"/>
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</dia:attribute>
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<dia:attribute name="pagebreak">
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<dia:color val="#000099ff"/>
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</dia:attribute>
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<dia:attribute name="paper">
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<dia:composite type="paper">
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<dia:attribute name="name">
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<dia:string>#Letter#</dia:string>
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</dia:attribute>
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<dia:attribute name="tmargin">
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<dia:real val="2.5399999618530273"/>
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</dia:attribute>
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<dia:attribute name="bmargin">
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<dia:real val="2.5399999618530273"/>
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</dia:attribute>
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<dia:attribute name="lmargin">
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<dia:real val="2.5399999618530273"/>
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</dia:attribute>
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<dia:attribute name="rmargin">
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<dia:real val="2.5399999618530273"/>
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</dia:attribute>
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<dia:attribute name="is_portrait">
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<dia:boolean val="true"/>
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</dia:attribute>
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<dia:attribute name="scaling">
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<dia:real val="1"/>
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</dia:attribute>
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<dia:attribute name="fitto">
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<dia:boolean val="false"/>
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</dia:attribute>
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</dia:composite>
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</dia:attribute>
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<dia:attribute name="grid">
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<dia:composite type="grid">
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<dia:attribute name="dynamic">
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<dia:boolean val="true"/>
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</dia:attribute>
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<dia:attribute name="width_x">
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<dia:real val="0.125"/>
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</dia:attribute>
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<dia:attribute name="width_y">
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<dia:real val="0.125"/>
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</dia:attribute>
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<dia:attribute name="visible_x">
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<dia:int val="1"/>
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</dia:attribute>
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<dia:attribute name="visible_y">
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<dia:int val="1"/>
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</dia:attribute>
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<dia:composite type="color"/>
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</dia:composite>
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</dia:attribute>
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<dia:attribute name="color">
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<dia:color val="#d8e5e5ff"/>
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</dia:attribute>
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<dia:attribute name="guides">
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<dia:composite type="guides">
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<dia:attribute name="hguides"/>
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<dia:attribute name="vguides"/>
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</dia:composite>
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</dia:attribute>
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<dia:attribute name="display">
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<dia:composite type="display">
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<dia:attribute name="antialiased">
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<dia:boolean val="true"/>
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</dia:attribute>
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<dia:attribute name="snap-to-grid">
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<dia:boolean val="true"/>
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</dia:attribute>
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<dia:attribute name="snap-to-object">
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<dia:boolean val="true"/>
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</dia:attribute>
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<dia:attribute name="show-grid">
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<dia:boolean val="true"/>
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</dia:attribute>
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<dia:attribute name="show-connection-points">
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<dia:boolean val="true"/>
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</dia:attribute>
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</dia:composite>
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</dia:attribute>
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</dia:diagramdata>
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<dia:layer name="Background" visible="true" connectable="true" active="true">
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<dia:object type="Standard - Box" version="0" id="O0">
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<dia:attribute name="obj_pos">
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<dia:point val="1,1"/>
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</dia:attribute>
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<dia:attribute name="obj_bb">
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<dia:rectangle val="0.95,0.95;10.05,9.05"/>
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</dia:attribute>
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<dia:attribute name="elem_corner">
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<dia:point val="1,1"/>
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</dia:attribute>
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<dia:attribute name="elem_width">
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<dia:real val="9"/>
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</dia:attribute>
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<dia:attribute name="elem_height">
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<dia:real val="8"/>
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</dia:attribute>
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<dia:attribute name="show_background">
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<dia:boolean val="true"/>
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</dia:attribute>
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</dia:object>
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<dia:object type="Standard - Text" version="1" id="O1">
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<dia:attribute name="obj_pos">
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<dia:point val="5.5,5"/>
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</dia:attribute>
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<dia:attribute name="obj_bb">
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<dia:rectangle val="5.5,4.38732;7.40612,5.18818"/>
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</dia:attribute>
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<dia:attribute name="text">
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<dia:composite type="text">
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<dia:attribute name="string">
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<dia:string>#TODO#</dia:string>
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</dia:attribute>
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<dia:attribute name="font">
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<dia:font family="sans" style="0" name="Helvetica"/>
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</dia:attribute>
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<dia:attribute name="height">
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<dia:real val="0.80000000000000004"/>
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</dia:attribute>
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<dia:attribute name="pos">
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<dia:point val="5.5,5"/>
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</dia:attribute>
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<dia:attribute name="color">
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<dia:color val="#000000ff"/>
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</dia:attribute>
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<dia:attribute name="alignment">
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<dia:enum val="0"/>
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</dia:attribute>
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</dia:composite>
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</dia:attribute>
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<dia:attribute name="valign">
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<dia:enum val="3"/>
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</dia:attribute>
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<dia:connections>
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<dia:connection handle="0" to="O0" connection="8"/>
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</dia:connections>
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</dia:object>
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</dia:layer>
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</dia:diagram>
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17
src/first_arch/index.md
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src/first_arch/index.md
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# Proposal for Libre-Chip's First CPU Architecture (Draft)
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## Stages
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The CPU architecture will be developed in several stages:
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1. Getting an initial working CPU -- First NLNet/etc. Grant
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Possible follow-on work, order TBD:
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* Expand CPU to support more operations (e.g. floating-point, vector ops., paging)
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* Add FPGA-style programmable decoder and μOp Cache, with trap-to-software fallback for uncommon/complex ops, which allows running more ISAs such as RISC-V, older x86-32/64, more PowerISA support, and then if we can figure out the legal situation, ARM and modern x86-64. The idea is QEMU (or similar) will be compiled with a special compiler that generates both the fallback software and the bitstream for the decoder, the compiled output will be covered by QEMU's license which has some patent clauses, which hopefully helps with the legal situation. Jacob Lifshay came up with this idea [back in 2022](https://web.archive.org/web/20220612082603/https://bugs.libre-soc.org/show_bug.cgi?id=841)
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* Formal proof that the CPU doesn't have any spectre-style bugs even though it still is OoO superscalar with speculative execution. Jacob Lifshay came up with this idea [back in 2020](https://web.archive.org/web/20201021124234/https://bugs.libre-soc.org/show_bug.cgi?id=209)
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## Architecture
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![](architecture.dia.svg)
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