forked from libre-chip/fayalite
Jacob Lifshay
d4d9706798
Add support to the simulator for running hdl asserts/assumes and being able to write to the formal global clock/reset and all any/all_const/seq that are used. This allows you to use the exact same HDL code for running a simulation and for running a formal proof.
213 lines
No EOL
7.1 KiB
Text
213 lines
No EOL
7.1 KiB
Text
Simulation {
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state: State {
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insns: Insns {
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state_layout: StateLayout {
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ty: TypeLayout {
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small_slots: StatePartLayout<SmallSlots> {
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len: 0,
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debug_data: [],
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..
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},
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big_slots: StatePartLayout<BigSlots> {
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len: 5,
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debug_data: [
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SlotDebugData {
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name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out",
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ty: AsyncReset,
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},
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SlotDebugData {
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name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::bit_out",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: UInt<1>,
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},
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SlotDebugData {
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name: "",
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ty: AsyncReset,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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],
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..
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},
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sim_only_slots: StatePartLayout<SimOnlySlots> {
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len: 0,
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debug_data: [],
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layout_data: [],
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..
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},
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},
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memories: StatePartLayout<Memories> {
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len: 0,
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debug_data: [],
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layout_data: [],
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..
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},
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},
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insns: [
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// at: module-XXXXXXXXXX.rs:1:1
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0: Const {
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dest: StatePartIndex<BigSlots>(2), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
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value: 0x1,
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},
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1: Copy {
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dest: StatePartIndex<BigSlots>(3), // (0x1) SlotDebugData { name: "", ty: AsyncReset },
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src: StatePartIndex<BigSlots>(2), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
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},
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// at: module-XXXXXXXXXX.rs:4:1
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2: Copy {
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dest: StatePartIndex<BigSlots>(0), // (0x1) SlotDebugData { name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out", ty: AsyncReset },
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src: StatePartIndex<BigSlots>(3), // (0x1) SlotDebugData { name: "", ty: AsyncReset },
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},
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// at: module-XXXXXXXXXX.rs:1:1
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3: Copy {
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dest: StatePartIndex<BigSlots>(4), // (0x1) SlotDebugData { name: "", ty: Bool },
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src: StatePartIndex<BigSlots>(0), // (0x1) SlotDebugData { name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out", ty: AsyncReset },
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},
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// at: module-XXXXXXXXXX.rs:5:1
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4: Copy {
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dest: StatePartIndex<BigSlots>(1), // (0x1) SlotDebugData { name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::bit_out", ty: Bool },
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src: StatePartIndex<BigSlots>(4), // (0x1) SlotDebugData { name: "", ty: Bool },
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},
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// at: module-XXXXXXXXXX.rs:1:1
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5: Return,
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],
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..
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},
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pc: 5,
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memory_write_log: [],
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assert_failed_log: [],
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memories: StatePart {
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value: [],
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},
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small_slots: StatePart {
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value: [],
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},
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big_slots: StatePart {
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value: [
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1,
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1,
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1,
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1,
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1,
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],
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},
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sim_only_slots: StatePart {
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value: [],
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},
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},
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io: Instance {
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name: <simulator>::connect_const_reset,
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instantiated: Module {
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name: connect_const_reset,
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..
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},
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},
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global_io: {},
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main_module: SimulationModuleState {
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base_targets: [
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Instance {
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name: <simulator>::connect_const_reset,
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instantiated: Module {
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name: connect_const_reset,
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..
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},
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}.reset_out,
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Instance {
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name: <simulator>::connect_const_reset,
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instantiated: Module {
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name: connect_const_reset,
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..
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},
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}.bit_out,
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],
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uninitialized_ios: {},
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io_targets: {
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Instance {
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name: <simulator>::connect_const_reset,
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instantiated: Module {
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name: connect_const_reset,
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..
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},
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}.bit_out,
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Instance {
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name: <simulator>::connect_const_reset,
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instantiated: Module {
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name: connect_const_reset,
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..
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},
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}.reset_out,
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},
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did_initial_settle: true,
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clocks_for_past: {},
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},
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extern_modules: [],
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trace_decls: TraceModule {
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name: "connect_const_reset",
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children: [
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TraceModuleIO {
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name: "reset_out",
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child: TraceAsyncReset {
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location: TraceScalarId(0),
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name: "reset_out",
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flow: Sink,
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},
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ty: AsyncReset,
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flow: Sink,
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},
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TraceModuleIO {
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name: "bit_out",
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child: TraceBool {
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location: TraceScalarId(1),
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name: "bit_out",
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flow: Sink,
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},
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ty: Bool,
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flow: Sink,
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},
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],
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},
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traces: [
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SimTrace {
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id: TraceScalarId(0),
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kind: BigAsyncReset {
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index: StatePartIndex<BigSlots>(0),
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},
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maybe_changed: true,
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state: 0x1,
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last_state: 0x1,
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},
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SimTrace {
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id: TraceScalarId(1),
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kind: BigBool {
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index: StatePartIndex<BigSlots>(1),
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},
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maybe_changed: true,
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state: 0x1,
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last_state: 0x1,
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},
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],
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trace_memories: {},
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trace_writers: [
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Running(
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VcdWriter {
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finished_init: true,
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timescale: 1 ps,
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..
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},
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),
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],
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clocks_triggered: [],
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event_queue: EventQueue(EventQueueData {
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instant: 1 μs,
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events: {},
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}),
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waiting_sensitivity_sets_by_address: {},
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waiting_sensitivity_sets_by_compiled_value: {},
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asserts: [],
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..
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} |