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fayalite/crates/fayalite/tests/sim/expected/many_memories.txt

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Simulation {
state: State {
insns: Insns {
state_layout: StateLayout {
ty: TypeLayout {
small_slots: StatePartLayout<SmallSlots> {
len: 96,
debug_data: [
SlotDebugData {
name: "",
ty: Bool,
},
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SlotDebugData {
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SlotDebugData {
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],
..
},
big_slots: StatePartLayout<BigSlots> {
len: 160,
debug_data: [
SlotDebugData {
name: "InstantiatedModule(many_memories: many_memories).many_memories::r[0].addr",
ty: UInt<4>,
},
SlotDebugData {
name: "InstantiatedModule(many_memories: many_memories).many_memories::r[0].en",
ty: Bool,
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SlotDebugData {
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SlotDebugData {
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SlotDebugData {
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SlotDebugData {
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SlotDebugData {
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SlotDebugData {
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SlotDebugData {
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ty: UInt<4>,
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SlotDebugData {
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SlotDebugData {
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SlotDebugData {
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SlotDebugData {
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ty: Clock,
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SlotDebugData {
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ty: Bool,
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SlotDebugData {
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SlotDebugData {
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SlotDebugData {
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SlotDebugData {
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SlotDebugData {
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SlotDebugData {
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SlotDebugData {
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SlotDebugData {
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SlotDebugData {
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SlotDebugData {
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SlotDebugData {
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SlotDebugData {
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SlotDebugData {
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SlotDebugData {
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SlotDebugData {
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SlotDebugData {
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SlotDebugData {
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ty: Bool,
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SlotDebugData {
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SlotDebugData {
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SlotDebugData {
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ty: Bool,
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SlotDebugData {
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SlotDebugData {
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ty: Bool,
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SlotDebugData {
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ty: Bool,
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SlotDebugData {
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ty: UInt<4>,
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SlotDebugData {
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SlotDebugData {
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SlotDebugData {
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SlotDebugData {
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SlotDebugData {
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ty: UInt<4>,
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SlotDebugData {
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ty: Bool,
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SlotDebugData {
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SlotDebugData {
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SlotDebugData {
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SlotDebugData {
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SlotDebugData {
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SlotDebugData {
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ty: UInt<4>,
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SlotDebugData {
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SlotDebugData {
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ty: Clock,
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SlotDebugData {
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SlotDebugData {
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ty: UInt<4>,
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SlotDebugData {
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SlotDebugData {
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SlotDebugData {
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SlotDebugData {
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SlotDebugData {
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SlotDebugData {
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SlotDebugData {
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ty: UInt<4>,
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SlotDebugData {
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SlotDebugData {
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SlotDebugData {
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SlotDebugData {
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SlotDebugData {
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SlotDebugData {
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SlotDebugData {
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SlotDebugData {
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SlotDebugData {
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SlotDebugData {
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ty: UInt<4>,
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SlotDebugData {
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ty: Bool,
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SlotDebugData {
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SlotDebugData {
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SlotDebugData {
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SlotDebugData {
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SlotDebugData {
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ty: Clock,
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SlotDebugData {
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ty: Bool,
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SlotDebugData {
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SlotDebugData {
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ty: Bool,
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SlotDebugData {
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ty: Bool,
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SlotDebugData {
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ty: UInt<4>,
},
SlotDebugData {
name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::r0.en",
ty: Bool,
},
SlotDebugData {
name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::r0.clk",
ty: Clock,
},
SlotDebugData {
name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::r0.data",
ty: Bool,
},
SlotDebugData {
name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::w1.addr",
ty: UInt<4>,
},
SlotDebugData {
name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::w1.en",
ty: Bool,
},
SlotDebugData {
name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::w1.clk",
ty: Clock,
},
SlotDebugData {
name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::w1.data",
ty: Bool,
},
SlotDebugData {
name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::w1.mask",
ty: Bool,
},
SlotDebugData {
name: "",
ty: Bool,
},
SlotDebugData {
name: "",
ty: Bool,
},
SlotDebugData {
name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::r0.addr",
ty: UInt<4>,
},
SlotDebugData {
name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::r0.en",
ty: Bool,
},
SlotDebugData {
name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::r0.clk",
ty: Clock,
},
SlotDebugData {
name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::r0.data",
ty: Bool,
},
SlotDebugData {
name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::w1.addr",
ty: UInt<4>,
},
SlotDebugData {
name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::w1.en",
ty: Bool,
},
SlotDebugData {
name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::w1.clk",
ty: Clock,
},
SlotDebugData {
name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::w1.data",
ty: Bool,
},
SlotDebugData {
name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::w1.mask",
ty: Bool,
},
SlotDebugData {
name: "",
ty: Bool,
},
SlotDebugData {
name: "",
ty: Bool,
},
SlotDebugData {
name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::r0.addr",
ty: UInt<4>,
},
SlotDebugData {
name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::r0.en",
ty: Bool,
},
SlotDebugData {
name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::r0.clk",
ty: Clock,
},
SlotDebugData {
name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::r0.data",
ty: Bool,
},
SlotDebugData {
name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::w1.addr",
ty: UInt<4>,
},
SlotDebugData {
name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::w1.en",
ty: Bool,
},
SlotDebugData {
name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::w1.clk",
ty: Clock,
},
SlotDebugData {
name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::w1.data",
ty: Bool,
},
SlotDebugData {
name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::w1.mask",
ty: Bool,
},
SlotDebugData {
name: "",
ty: Bool,
},
SlotDebugData {
name: "",
ty: Bool,
},
],
..
},
sim_only_slots: StatePartLayout<SimOnlySlots> {
len: 0,
debug_data: [],
layout_data: [],
..
},
},
memories: StatePartLayout<Memories> {
len: 8,
debug_data: [
(),
(),
(),
(),
(),
(),
(),
(),
],
layout_data: [
MemoryData {
array_type: Array<Bool, 16>,
data: [
// len = 0x10
[0x0]: 0x0,
[0x1]: 0x0,
[0x2]: 0x0,
[0x3]: 0x0,
[0x4]: 0x0,
[0x5]: 0x0,
[0x6]: 0x0,
[0x7]: 0x0,
[0x8]: 0x0,
[0x9]: 0x0,
[0xa]: 0x0,
[0xb]: 0x0,
[0xc]: 0x0,
[0xd]: 0x0,
[0xe]: 0x0,
[0xf]: 0x0,
],
},
MemoryData {
array_type: Array<Bool, 16>,
data: [
// len = 0x10
[0x0]: 0x1,
[0x1]: 0x0,
[0x2]: 0x0,
[0x3]: 0x0,
[0x4]: 0x0,
[0x5]: 0x0,
[0x6]: 0x0,
[0x7]: 0x0,
[0x8]: 0x0,
[0x9]: 0x0,
[0xa]: 0x0,
[0xb]: 0x0,
[0xc]: 0x0,
[0xd]: 0x0,
[0xe]: 0x0,
[0xf]: 0x0,
],
},
MemoryData {
array_type: Array<Bool, 16>,
data: [
// len = 0x10
[0x0]: 0x0,
[0x1]: 0x0,
[0x2]: 0x0,
[0x3]: 0x0,
[0x4]: 0x0,
[0x5]: 0x1,
[0x6]: 0x0,
[0x7]: 0x0,
[0x8]: 0x0,
[0x9]: 0x0,
[0xa]: 0x0,
[0xb]: 0x0,
[0xc]: 0x0,
[0xd]: 0x0,
[0xe]: 0x0,
[0xf]: 0x0,
],
},
MemoryData {
array_type: Array<Bool, 16>,
data: [
// len = 0x10
[0x0]: 0x1,
[0x1]: 0x1,
[0x2]: 0x0,
[0x3]: 0x0,
[0x4]: 0x1,
[0x5]: 0x1,
[0x6]: 0x1,
[0x7]: 0x1,
[0x8]: 0x0,
[0x9]: 0x0,
[0xa]: 0x0,
[0xb]: 0x0,
[0xc]: 0x0,
[0xd]: 0x0,
[0xe]: 0x0,
[0xf]: 0x0,
],
},
MemoryData {
array_type: Array<Bool, 16>,
data: [
// len = 0x10
[0x0]: 0x0,
[0x1]: 0x0,
[0x2]: 0x0,
[0x3]: 0x0,
[0x4]: 0x0,
[0x5]: 0x0,
[0x6]: 0x0,
[0x7]: 0x0,
[0x8]: 0x0,
[0x9]: 0x0,
[0xa]: 0x1,
[0xb]: 0x0,
[0xc]: 0x0,
[0xd]: 0x0,
[0xe]: 0x0,
[0xf]: 0x0,
],
},
MemoryData {
array_type: Array<Bool, 16>,
data: [
// len = 0x10
[0x0]: 0x1,
[0x1]: 0x0,
[0x2]: 0x1,
[0x3]: 0x0,
[0x4]: 0x1,
[0x5]: 0x1,
[0x6]: 0x0,
[0x7]: 0x0,
[0x8]: 0x0,
[0x9]: 0x0,
[0xa]: 0x1,
[0xb]: 0x1,
[0xc]: 0x0,
[0xd]: 0x0,
[0xe]: 0x0,
[0xf]: 0x0,
],
},
MemoryData {
array_type: Array<Bool, 16>,
data: [
// len = 0x10
[0x0]: 0x0,
[0x1]: 0x0,
[0x2]: 0x0,
[0x3]: 0x0,
[0x4]: 0x0,
[0x5]: 0x1,
[0x6]: 0x1,
[0x7]: 0x0,
[0x8]: 0x0,
[0x9]: 0x1,
[0xa]: 0x1,
[0xb]: 0x1,
[0xc]: 0x1,
[0xd]: 0x0,
[0xe]: 0x0,
[0xf]: 0x0,
],
},
MemoryData {
array_type: Array<Bool, 16>,
data: [
// len = 0x10
[0x0]: 0x1,
[0x1]: 0x1,
[0x2]: 0x1,
[0x3]: 0x0,
[0x4]: 0x0,
[0x5]: 0x1,
[0x6]: 0x0,
[0x7]: 0x1,
[0x8]: 0x1,
[0x9]: 0x0,
[0xa]: 0x0,
[0xb]: 0x0,
[0xc]: 0x0,
[0xd]: 0x0,
[0xe]: 0x1,
[0xf]: 0x0,
],
},
],
..
},
},
insns: [
// at: module-XXXXXXXXXX.rs:8:1
0: Copy {
dest: StatePartIndex<BigSlots>(153), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::w1.addr", ty: UInt<4> },
src: StatePartIndex<BigSlots>(67), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[7].addr", ty: UInt<4> },
},
1: Copy {
dest: StatePartIndex<BigSlots>(154), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::w1.en", ty: Bool },
src: StatePartIndex<BigSlots>(68), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[7].en", ty: Bool },
},
2: Copy {
dest: StatePartIndex<BigSlots>(155), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::w1.clk", ty: Clock },
src: StatePartIndex<BigSlots>(69), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[7].clk", ty: Clock },
},
3: Copy {
dest: StatePartIndex<BigSlots>(156), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::w1.data", ty: Bool },
src: StatePartIndex<BigSlots>(70), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[7].data", ty: Bool },
},
4: Copy {
dest: StatePartIndex<BigSlots>(157), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::w1.mask", ty: Bool },
src: StatePartIndex<BigSlots>(71), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[7].mask", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:6:1
5: Copy {
dest: StatePartIndex<BigSlots>(151), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::r0.clk", ty: Clock },
src: StatePartIndex<BigSlots>(30), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[7].clk", ty: Clock },
},
6: Copy {
dest: StatePartIndex<BigSlots>(150), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::r0.en", ty: Bool },
src: StatePartIndex<BigSlots>(29), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[7].en", ty: Bool },
},
7: Copy {
dest: StatePartIndex<BigSlots>(149), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::r0.addr", ty: UInt<4> },
src: StatePartIndex<BigSlots>(28), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[7].addr", ty: UInt<4> },
},
// at: module-XXXXXXXXXX.rs:8:1
8: Copy {
dest: StatePartIndex<BigSlots>(142), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::w1.addr", ty: UInt<4> },
src: StatePartIndex<BigSlots>(62), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[6].addr", ty: UInt<4> },
},
9: Copy {
dest: StatePartIndex<BigSlots>(143), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::w1.en", ty: Bool },
src: StatePartIndex<BigSlots>(63), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[6].en", ty: Bool },
},
10: Copy {
dest: StatePartIndex<BigSlots>(144), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::w1.clk", ty: Clock },
src: StatePartIndex<BigSlots>(64), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[6].clk", ty: Clock },
},
11: Copy {
dest: StatePartIndex<BigSlots>(145), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::w1.data", ty: Bool },
src: StatePartIndex<BigSlots>(65), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[6].data", ty: Bool },
},
12: Copy {
dest: StatePartIndex<BigSlots>(146), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::w1.mask", ty: Bool },
src: StatePartIndex<BigSlots>(66), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[6].mask", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:6:1
13: Copy {
dest: StatePartIndex<BigSlots>(140), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::r0.clk", ty: Clock },
src: StatePartIndex<BigSlots>(26), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[6].clk", ty: Clock },
},
14: Copy {
dest: StatePartIndex<BigSlots>(139), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::r0.en", ty: Bool },
src: StatePartIndex<BigSlots>(25), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[6].en", ty: Bool },
},
15: Copy {
dest: StatePartIndex<BigSlots>(138), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::r0.addr", ty: UInt<4> },
src: StatePartIndex<BigSlots>(24), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[6].addr", ty: UInt<4> },
},
// at: module-XXXXXXXXXX.rs:8:1
16: Copy {
dest: StatePartIndex<BigSlots>(131), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::w1.addr", ty: UInt<4> },
src: StatePartIndex<BigSlots>(57), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[5].addr", ty: UInt<4> },
},
17: Copy {
dest: StatePartIndex<BigSlots>(132), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::w1.en", ty: Bool },
src: StatePartIndex<BigSlots>(58), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[5].en", ty: Bool },
},
18: Copy {
dest: StatePartIndex<BigSlots>(133), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::w1.clk", ty: Clock },
src: StatePartIndex<BigSlots>(59), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[5].clk", ty: Clock },
},
19: Copy {
dest: StatePartIndex<BigSlots>(134), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::w1.data", ty: Bool },
src: StatePartIndex<BigSlots>(60), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[5].data", ty: Bool },
},
20: Copy {
dest: StatePartIndex<BigSlots>(135), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::w1.mask", ty: Bool },
src: StatePartIndex<BigSlots>(61), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[5].mask", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:6:1
21: Copy {
dest: StatePartIndex<BigSlots>(129), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::r0.clk", ty: Clock },
src: StatePartIndex<BigSlots>(22), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[5].clk", ty: Clock },
},
22: Copy {
dest: StatePartIndex<BigSlots>(128), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::r0.en", ty: Bool },
src: StatePartIndex<BigSlots>(21), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[5].en", ty: Bool },
},
23: Copy {
dest: StatePartIndex<BigSlots>(127), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::r0.addr", ty: UInt<4> },
src: StatePartIndex<BigSlots>(20), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[5].addr", ty: UInt<4> },
},
// at: module-XXXXXXXXXX.rs:8:1
24: Copy {
dest: StatePartIndex<BigSlots>(120), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::w1.addr", ty: UInt<4> },
src: StatePartIndex<BigSlots>(52), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[4].addr", ty: UInt<4> },
},
25: Copy {
dest: StatePartIndex<BigSlots>(121), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::w1.en", ty: Bool },
src: StatePartIndex<BigSlots>(53), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[4].en", ty: Bool },
},
26: Copy {
dest: StatePartIndex<BigSlots>(122), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::w1.clk", ty: Clock },
src: StatePartIndex<BigSlots>(54), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[4].clk", ty: Clock },
},
27: Copy {
dest: StatePartIndex<BigSlots>(123), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::w1.data", ty: Bool },
src: StatePartIndex<BigSlots>(55), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[4].data", ty: Bool },
},
28: Copy {
dest: StatePartIndex<BigSlots>(124), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::w1.mask", ty: Bool },
src: StatePartIndex<BigSlots>(56), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[4].mask", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:6:1
29: Copy {
dest: StatePartIndex<BigSlots>(118), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::r0.clk", ty: Clock },
src: StatePartIndex<BigSlots>(18), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[4].clk", ty: Clock },
},
30: Copy {
dest: StatePartIndex<BigSlots>(117), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::r0.en", ty: Bool },
src: StatePartIndex<BigSlots>(17), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[4].en", ty: Bool },
},
31: Copy {
dest: StatePartIndex<BigSlots>(116), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::r0.addr", ty: UInt<4> },
src: StatePartIndex<BigSlots>(16), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[4].addr", ty: UInt<4> },
},
// at: module-XXXXXXXXXX.rs:8:1
32: Copy {
dest: StatePartIndex<BigSlots>(109), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::w1.addr", ty: UInt<4> },
src: StatePartIndex<BigSlots>(47), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[3].addr", ty: UInt<4> },
},
33: Copy {
dest: StatePartIndex<BigSlots>(110), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::w1.en", ty: Bool },
src: StatePartIndex<BigSlots>(48), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[3].en", ty: Bool },
},
34: Copy {
dest: StatePartIndex<BigSlots>(111), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::w1.clk", ty: Clock },
src: StatePartIndex<BigSlots>(49), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[3].clk", ty: Clock },
},
35: Copy {
dest: StatePartIndex<BigSlots>(112), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::w1.data", ty: Bool },
src: StatePartIndex<BigSlots>(50), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[3].data", ty: Bool },
},
36: Copy {
dest: StatePartIndex<BigSlots>(113), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::w1.mask", ty: Bool },
src: StatePartIndex<BigSlots>(51), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[3].mask", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:6:1
37: Copy {
dest: StatePartIndex<BigSlots>(107), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::r0.clk", ty: Clock },
src: StatePartIndex<BigSlots>(14), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[3].clk", ty: Clock },
},
38: Copy {
dest: StatePartIndex<BigSlots>(106), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::r0.en", ty: Bool },
src: StatePartIndex<BigSlots>(13), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[3].en", ty: Bool },
},
39: Copy {
dest: StatePartIndex<BigSlots>(105), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::r0.addr", ty: UInt<4> },
src: StatePartIndex<BigSlots>(12), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[3].addr", ty: UInt<4> },
},
// at: module-XXXXXXXXXX.rs:8:1
40: Copy {
dest: StatePartIndex<BigSlots>(98), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::w1.addr", ty: UInt<4> },
src: StatePartIndex<BigSlots>(42), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[2].addr", ty: UInt<4> },
},
41: Copy {
dest: StatePartIndex<BigSlots>(99), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::w1.en", ty: Bool },
src: StatePartIndex<BigSlots>(43), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[2].en", ty: Bool },
},
42: Copy {
dest: StatePartIndex<BigSlots>(100), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::w1.clk", ty: Clock },
src: StatePartIndex<BigSlots>(44), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[2].clk", ty: Clock },
},
43: Copy {
dest: StatePartIndex<BigSlots>(101), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::w1.data", ty: Bool },
src: StatePartIndex<BigSlots>(45), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[2].data", ty: Bool },
},
44: Copy {
dest: StatePartIndex<BigSlots>(102), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::w1.mask", ty: Bool },
src: StatePartIndex<BigSlots>(46), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[2].mask", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:6:1
45: Copy {
dest: StatePartIndex<BigSlots>(96), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::r0.clk", ty: Clock },
src: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[2].clk", ty: Clock },
},
46: Copy {
dest: StatePartIndex<BigSlots>(95), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::r0.en", ty: Bool },
src: StatePartIndex<BigSlots>(9), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[2].en", ty: Bool },
},
47: Copy {
dest: StatePartIndex<BigSlots>(94), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::r0.addr", ty: UInt<4> },
src: StatePartIndex<BigSlots>(8), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[2].addr", ty: UInt<4> },
},
// at: module-XXXXXXXXXX.rs:8:1
48: Copy {
dest: StatePartIndex<BigSlots>(87), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::w1.addr", ty: UInt<4> },
src: StatePartIndex<BigSlots>(37), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[1].addr", ty: UInt<4> },
},
49: Copy {
dest: StatePartIndex<BigSlots>(88), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::w1.en", ty: Bool },
src: StatePartIndex<BigSlots>(38), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[1].en", ty: Bool },
},
50: Copy {
dest: StatePartIndex<BigSlots>(89), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::w1.clk", ty: Clock },
src: StatePartIndex<BigSlots>(39), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[1].clk", ty: Clock },
},
51: Copy {
dest: StatePartIndex<BigSlots>(90), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::w1.data", ty: Bool },
src: StatePartIndex<BigSlots>(40), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[1].data", ty: Bool },
},
52: Copy {
dest: StatePartIndex<BigSlots>(91), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::w1.mask", ty: Bool },
src: StatePartIndex<BigSlots>(41), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[1].mask", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:6:1
53: Copy {
dest: StatePartIndex<BigSlots>(85), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::r0.clk", ty: Clock },
src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[1].clk", ty: Clock },
},
54: Copy {
dest: StatePartIndex<BigSlots>(84), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::r0.en", ty: Bool },
src: StatePartIndex<BigSlots>(5), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[1].en", ty: Bool },
},
55: Copy {
dest: StatePartIndex<BigSlots>(83), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::r0.addr", ty: UInt<4> },
src: StatePartIndex<BigSlots>(4), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[1].addr", ty: UInt<4> },
},
// at: module-XXXXXXXXXX.rs:8:1
56: Copy {
dest: StatePartIndex<BigSlots>(76), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::w1.addr", ty: UInt<4> },
src: StatePartIndex<BigSlots>(32), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[0].addr", ty: UInt<4> },
},
57: Copy {
dest: StatePartIndex<BigSlots>(77), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::w1.en", ty: Bool },
src: StatePartIndex<BigSlots>(33), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[0].en", ty: Bool },
},
58: Copy {
dest: StatePartIndex<BigSlots>(78), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::w1.clk", ty: Clock },
src: StatePartIndex<BigSlots>(34), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[0].clk", ty: Clock },
},
59: Copy {
dest: StatePartIndex<BigSlots>(79), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::w1.data", ty: Bool },
src: StatePartIndex<BigSlots>(35), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[0].data", ty: Bool },
},
60: Copy {
dest: StatePartIndex<BigSlots>(80), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::w1.mask", ty: Bool },
src: StatePartIndex<BigSlots>(36), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[0].mask", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:6:1
61: Copy {
dest: StatePartIndex<BigSlots>(74), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::r0.clk", ty: Clock },
src: StatePartIndex<BigSlots>(2), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[0].clk", ty: Clock },
},
62: Copy {
dest: StatePartIndex<BigSlots>(73), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::r0.en", ty: Bool },
src: StatePartIndex<BigSlots>(1), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[0].en", ty: Bool },
},
63: Copy {
dest: StatePartIndex<BigSlots>(72), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::r0.addr", ty: UInt<4> },
src: StatePartIndex<BigSlots>(0), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[0].addr", ty: UInt<4> },
},
// at: module-XXXXXXXXXX.rs:4:1
64: CastBigToArrayIndex {
dest: StatePartIndex<SmallSlots>(93), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> },
src: StatePartIndex<BigSlots>(153), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::w1.addr", ty: UInt<4> },
},
65: IsNonZeroDestIsSmall {
dest: StatePartIndex<SmallSlots>(92), // (0x0 0) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(154), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::w1.en", ty: Bool },
},
66: IsNonZeroDestIsSmall {
dest: StatePartIndex<SmallSlots>(91), // (0x0 0) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(155), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::w1.clk", ty: Clock },
},
67: AndSmall {
dest: StatePartIndex<SmallSlots>(90), // (0x0 0) SlotDebugData { name: "", ty: Bool },
lhs: StatePartIndex<SmallSlots>(91), // (0x0 0) SlotDebugData { name: "", ty: Bool },
rhs: StatePartIndex<SmallSlots>(89), // (0x1 1) SlotDebugData { name: "", ty: Bool },
},
68: CastBigToArrayIndex {
dest: StatePartIndex<SmallSlots>(88), // (0xf 15) SlotDebugData { name: "", ty: UInt<4> },
src: StatePartIndex<BigSlots>(149), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::r0.addr", ty: UInt<4> },
},
69: IsNonZeroDestIsSmall {
dest: StatePartIndex<SmallSlots>(87), // (0x1 1) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(150), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::r0.en", ty: Bool },
},
70: BranchIfSmallZero {
target: 73,
value: StatePartIndex<SmallSlots>(87), // (0x1 1) SlotDebugData { name: "", ty: Bool },
},
71: MemoryReadUInt {
dest: StatePartIndex<BigSlots>(152), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::r0.data", ty: Bool },
memory: StatePartIndex<Memories>(7), // (MemoryData {
// array_type: Array<Bool, 16>,
// data: [
// // len = 0x10
// [0x0]: 0x0,
// [0x1]: 0x1,
// [0x2]: 0x1,
// [0x3]: 0x0,
// [0x4]: 0x0,
// [0x5]: 0x1,
// [0x6]: 0x0,
// [0x7]: 0x1,
// [0x8]: 0x1,
// [0x9]: 0x0,
// [0xa]: 0x0,
// [0xb]: 0x0,
// [0xc]: 0x0,
// [0xd]: 0x0,
// [0xe]: 0x1,
// [0xf]: 0x0,
// ],
// }) (),
addr: StatePartIndex<SmallSlots>(88), // (0xf 15) SlotDebugData { name: "", ty: UInt<4> },
stride: 1,
start: 0,
width: 1,
},
72: Branch {
target: 74,
},
73: Const {
dest: StatePartIndex<BigSlots>(152), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::r0.data", ty: Bool },
value: 0x0,
},
// at: module-XXXXXXXXXX.rs:6:1
74: Copy {
dest: StatePartIndex<BigSlots>(31), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[7].data", ty: Bool },
src: StatePartIndex<BigSlots>(152), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::r0.data", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:4:1
75: IsNonZeroDestIsSmall {
dest: StatePartIndex<SmallSlots>(86), // (0x0 0) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(151), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::r0.clk", ty: Clock },
},
76: AndSmall {
dest: StatePartIndex<SmallSlots>(85), // (0x0 0) SlotDebugData { name: "", ty: Bool },
lhs: StatePartIndex<SmallSlots>(86), // (0x0 0) SlotDebugData { name: "", ty: Bool },
rhs: StatePartIndex<SmallSlots>(84), // (0x1 1) SlotDebugData { name: "", ty: Bool },
},
77: CastBigToArrayIndex {
dest: StatePartIndex<SmallSlots>(81), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> },
src: StatePartIndex<BigSlots>(142), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::w1.addr", ty: UInt<4> },
},
78: IsNonZeroDestIsSmall {
dest: StatePartIndex<SmallSlots>(80), // (0x0 0) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(143), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::w1.en", ty: Bool },
},
79: IsNonZeroDestIsSmall {
dest: StatePartIndex<SmallSlots>(79), // (0x0 0) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(144), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::w1.clk", ty: Clock },
},
80: AndSmall {
dest: StatePartIndex<SmallSlots>(78), // (0x0 0) SlotDebugData { name: "", ty: Bool },
lhs: StatePartIndex<SmallSlots>(79), // (0x0 0) SlotDebugData { name: "", ty: Bool },
rhs: StatePartIndex<SmallSlots>(77), // (0x1 1) SlotDebugData { name: "", ty: Bool },
},
81: CastBigToArrayIndex {
dest: StatePartIndex<SmallSlots>(76), // (0xf 15) SlotDebugData { name: "", ty: UInt<4> },
src: StatePartIndex<BigSlots>(138), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::r0.addr", ty: UInt<4> },
},
82: IsNonZeroDestIsSmall {
dest: StatePartIndex<SmallSlots>(75), // (0x1 1) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(139), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::r0.en", ty: Bool },
},
83: BranchIfSmallZero {
target: 86,
value: StatePartIndex<SmallSlots>(75), // (0x1 1) SlotDebugData { name: "", ty: Bool },
},
84: MemoryReadUInt {
dest: StatePartIndex<BigSlots>(141), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::r0.data", ty: Bool },
memory: StatePartIndex<Memories>(6), // (MemoryData {
// array_type: Array<Bool, 16>,
// data: [
// // len = 0x10
// [0x0]: 0x0,
// [0x1]: 0x0,
// [0x2]: 0x0,
// [0x3]: 0x0,
// [0x4]: 0x0,
// [0x5]: 0x1,
// [0x6]: 0x1,
// [0x7]: 0x0,
// [0x8]: 0x0,
// [0x9]: 0x1,
// [0xa]: 0x1,
// [0xb]: 0x1,
// [0xc]: 0x1,
// [0xd]: 0x0,
// [0xe]: 0x0,
// [0xf]: 0x0,
// ],
// }) (),
addr: StatePartIndex<SmallSlots>(76), // (0xf 15) SlotDebugData { name: "", ty: UInt<4> },
stride: 1,
start: 0,
width: 1,
},
85: Branch {
target: 87,
},
86: Const {
dest: StatePartIndex<BigSlots>(141), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::r0.data", ty: Bool },
value: 0x0,
},
// at: module-XXXXXXXXXX.rs:6:1
87: Copy {
dest: StatePartIndex<BigSlots>(27), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[6].data", ty: Bool },
src: StatePartIndex<BigSlots>(141), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::r0.data", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:4:1
88: IsNonZeroDestIsSmall {
dest: StatePartIndex<SmallSlots>(74), // (0x0 0) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(140), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::r0.clk", ty: Clock },
},
89: AndSmall {
dest: StatePartIndex<SmallSlots>(73), // (0x0 0) SlotDebugData { name: "", ty: Bool },
lhs: StatePartIndex<SmallSlots>(74), // (0x0 0) SlotDebugData { name: "", ty: Bool },
rhs: StatePartIndex<SmallSlots>(72), // (0x1 1) SlotDebugData { name: "", ty: Bool },
},
90: CastBigToArrayIndex {
dest: StatePartIndex<SmallSlots>(69), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> },
src: StatePartIndex<BigSlots>(131), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::w1.addr", ty: UInt<4> },
},
91: IsNonZeroDestIsSmall {
dest: StatePartIndex<SmallSlots>(68), // (0x0 0) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(132), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::w1.en", ty: Bool },
},
92: IsNonZeroDestIsSmall {
dest: StatePartIndex<SmallSlots>(67), // (0x0 0) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(133), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::w1.clk", ty: Clock },
},
93: AndSmall {
dest: StatePartIndex<SmallSlots>(66), // (0x0 0) SlotDebugData { name: "", ty: Bool },
lhs: StatePartIndex<SmallSlots>(67), // (0x0 0) SlotDebugData { name: "", ty: Bool },
rhs: StatePartIndex<SmallSlots>(65), // (0x1 1) SlotDebugData { name: "", ty: Bool },
},
94: CastBigToArrayIndex {
dest: StatePartIndex<SmallSlots>(64), // (0xf 15) SlotDebugData { name: "", ty: UInt<4> },
src: StatePartIndex<BigSlots>(127), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::r0.addr", ty: UInt<4> },
},
95: IsNonZeroDestIsSmall {
dest: StatePartIndex<SmallSlots>(63), // (0x1 1) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(128), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::r0.en", ty: Bool },
},
96: BranchIfSmallZero {
target: 99,
value: StatePartIndex<SmallSlots>(63), // (0x1 1) SlotDebugData { name: "", ty: Bool },
},
97: MemoryReadUInt {
dest: StatePartIndex<BigSlots>(130), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::r0.data", ty: Bool },
memory: StatePartIndex<Memories>(5), // (MemoryData {
// array_type: Array<Bool, 16>,
// data: [
// // len = 0x10
// [0x0]: 0x0,
// [0x1]: 0x0,
// [0x2]: 0x1,
// [0x3]: 0x0,
// [0x4]: 0x1,
// [0x5]: 0x1,
// [0x6]: 0x0,
// [0x7]: 0x0,
// [0x8]: 0x0,
// [0x9]: 0x0,
// [0xa]: 0x1,
// [0xb]: 0x1,
// [0xc]: 0x0,
// [0xd]: 0x0,
// [0xe]: 0x0,
// [0xf]: 0x0,
// ],
// }) (),
addr: StatePartIndex<SmallSlots>(64), // (0xf 15) SlotDebugData { name: "", ty: UInt<4> },
stride: 1,
start: 0,
width: 1,
},
98: Branch {
target: 100,
},
99: Const {
dest: StatePartIndex<BigSlots>(130), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::r0.data", ty: Bool },
value: 0x0,
},
// at: module-XXXXXXXXXX.rs:6:1
100: Copy {
dest: StatePartIndex<BigSlots>(23), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[5].data", ty: Bool },
src: StatePartIndex<BigSlots>(130), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::r0.data", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:4:1
101: IsNonZeroDestIsSmall {
dest: StatePartIndex<SmallSlots>(62), // (0x0 0) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(129), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::r0.clk", ty: Clock },
},
102: AndSmall {
dest: StatePartIndex<SmallSlots>(61), // (0x0 0) SlotDebugData { name: "", ty: Bool },
lhs: StatePartIndex<SmallSlots>(62), // (0x0 0) SlotDebugData { name: "", ty: Bool },
rhs: StatePartIndex<SmallSlots>(60), // (0x1 1) SlotDebugData { name: "", ty: Bool },
},
103: CastBigToArrayIndex {
dest: StatePartIndex<SmallSlots>(57), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> },
src: StatePartIndex<BigSlots>(120), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::w1.addr", ty: UInt<4> },
},
104: IsNonZeroDestIsSmall {
dest: StatePartIndex<SmallSlots>(56), // (0x0 0) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(121), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::w1.en", ty: Bool },
},
105: IsNonZeroDestIsSmall {
dest: StatePartIndex<SmallSlots>(55), // (0x0 0) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(122), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::w1.clk", ty: Clock },
},
106: AndSmall {
dest: StatePartIndex<SmallSlots>(54), // (0x0 0) SlotDebugData { name: "", ty: Bool },
lhs: StatePartIndex<SmallSlots>(55), // (0x0 0) SlotDebugData { name: "", ty: Bool },
rhs: StatePartIndex<SmallSlots>(53), // (0x1 1) SlotDebugData { name: "", ty: Bool },
},
107: CastBigToArrayIndex {
dest: StatePartIndex<SmallSlots>(52), // (0xf 15) SlotDebugData { name: "", ty: UInt<4> },
src: StatePartIndex<BigSlots>(116), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::r0.addr", ty: UInt<4> },
},
108: IsNonZeroDestIsSmall {
dest: StatePartIndex<SmallSlots>(51), // (0x1 1) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(117), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::r0.en", ty: Bool },
},
109: BranchIfSmallZero {
target: 112,
value: StatePartIndex<SmallSlots>(51), // (0x1 1) SlotDebugData { name: "", ty: Bool },
},
110: MemoryReadUInt {
dest: StatePartIndex<BigSlots>(119), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::r0.data", ty: Bool },
memory: StatePartIndex<Memories>(4), // (MemoryData {
// array_type: Array<Bool, 16>,
// data: [
// // len = 0x10
// [0x0]: 0x0,
// [0x1]: 0x0,
// [0x2]: 0x0,
// [0x3]: 0x0,
// [0x4]: 0x0,
// [0x5]: 0x0,
// [0x6]: 0x0,
// [0x7]: 0x0,
// [0x8]: 0x0,
// [0x9]: 0x0,
// [0xa]: 0x1,
// [0xb]: 0x0,
// [0xc]: 0x0,
// [0xd]: 0x0,
// [0xe]: 0x0,
// [0xf]: 0x0,
// ],
// }) (),
addr: StatePartIndex<SmallSlots>(52), // (0xf 15) SlotDebugData { name: "", ty: UInt<4> },
stride: 1,
start: 0,
width: 1,
},
111: Branch {
target: 113,
},
112: Const {
dest: StatePartIndex<BigSlots>(119), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::r0.data", ty: Bool },
value: 0x0,
},
// at: module-XXXXXXXXXX.rs:6:1
113: Copy {
dest: StatePartIndex<BigSlots>(19), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[4].data", ty: Bool },
src: StatePartIndex<BigSlots>(119), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::r0.data", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:4:1
114: IsNonZeroDestIsSmall {
dest: StatePartIndex<SmallSlots>(50), // (0x0 0) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(118), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::r0.clk", ty: Clock },
},
115: AndSmall {
dest: StatePartIndex<SmallSlots>(49), // (0x0 0) SlotDebugData { name: "", ty: Bool },
lhs: StatePartIndex<SmallSlots>(50), // (0x0 0) SlotDebugData { name: "", ty: Bool },
rhs: StatePartIndex<SmallSlots>(48), // (0x1 1) SlotDebugData { name: "", ty: Bool },
},
116: CastBigToArrayIndex {
dest: StatePartIndex<SmallSlots>(45), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> },
src: StatePartIndex<BigSlots>(109), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::w1.addr", ty: UInt<4> },
},
117: IsNonZeroDestIsSmall {
dest: StatePartIndex<SmallSlots>(44), // (0x0 0) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(110), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::w1.en", ty: Bool },
},
118: IsNonZeroDestIsSmall {
dest: StatePartIndex<SmallSlots>(43), // (0x0 0) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(111), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::w1.clk", ty: Clock },
},
119: AndSmall {
dest: StatePartIndex<SmallSlots>(42), // (0x0 0) SlotDebugData { name: "", ty: Bool },
lhs: StatePartIndex<SmallSlots>(43), // (0x0 0) SlotDebugData { name: "", ty: Bool },
rhs: StatePartIndex<SmallSlots>(41), // (0x1 1) SlotDebugData { name: "", ty: Bool },
},
120: CastBigToArrayIndex {
dest: StatePartIndex<SmallSlots>(40), // (0xf 15) SlotDebugData { name: "", ty: UInt<4> },
src: StatePartIndex<BigSlots>(105), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::r0.addr", ty: UInt<4> },
},
121: IsNonZeroDestIsSmall {
dest: StatePartIndex<SmallSlots>(39), // (0x1 1) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(106), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::r0.en", ty: Bool },
},
122: BranchIfSmallZero {
target: 125,
value: StatePartIndex<SmallSlots>(39), // (0x1 1) SlotDebugData { name: "", ty: Bool },
},
123: MemoryReadUInt {
dest: StatePartIndex<BigSlots>(108), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::r0.data", ty: Bool },
memory: StatePartIndex<Memories>(3), // (MemoryData {
// array_type: Array<Bool, 16>,
// data: [
// // len = 0x10
// [0x0]: 0x0,
// [0x1]: 0x1,
// [0x2]: 0x0,
// [0x3]: 0x0,
// [0x4]: 0x1,
// [0x5]: 0x1,
// [0x6]: 0x1,
// [0x7]: 0x1,
// [0x8]: 0x0,
// [0x9]: 0x0,
// [0xa]: 0x0,
// [0xb]: 0x0,
// [0xc]: 0x0,
// [0xd]: 0x0,
// [0xe]: 0x0,
// [0xf]: 0x0,
// ],
// }) (),
addr: StatePartIndex<SmallSlots>(40), // (0xf 15) SlotDebugData { name: "", ty: UInt<4> },
stride: 1,
start: 0,
width: 1,
},
124: Branch {
target: 126,
},
125: Const {
dest: StatePartIndex<BigSlots>(108), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::r0.data", ty: Bool },
value: 0x0,
},
// at: module-XXXXXXXXXX.rs:6:1
126: Copy {
dest: StatePartIndex<BigSlots>(15), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[3].data", ty: Bool },
src: StatePartIndex<BigSlots>(108), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::r0.data", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:4:1
127: IsNonZeroDestIsSmall {
dest: StatePartIndex<SmallSlots>(38), // (0x0 0) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(107), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::r0.clk", ty: Clock },
},
128: AndSmall {
dest: StatePartIndex<SmallSlots>(37), // (0x0 0) SlotDebugData { name: "", ty: Bool },
lhs: StatePartIndex<SmallSlots>(38), // (0x0 0) SlotDebugData { name: "", ty: Bool },
rhs: StatePartIndex<SmallSlots>(36), // (0x1 1) SlotDebugData { name: "", ty: Bool },
},
129: CastBigToArrayIndex {
dest: StatePartIndex<SmallSlots>(33), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> },
src: StatePartIndex<BigSlots>(98), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::w1.addr", ty: UInt<4> },
},
130: IsNonZeroDestIsSmall {
dest: StatePartIndex<SmallSlots>(32), // (0x0 0) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(99), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::w1.en", ty: Bool },
},
131: IsNonZeroDestIsSmall {
dest: StatePartIndex<SmallSlots>(31), // (0x0 0) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(100), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::w1.clk", ty: Clock },
},
132: AndSmall {
dest: StatePartIndex<SmallSlots>(30), // (0x0 0) SlotDebugData { name: "", ty: Bool },
lhs: StatePartIndex<SmallSlots>(31), // (0x0 0) SlotDebugData { name: "", ty: Bool },
rhs: StatePartIndex<SmallSlots>(29), // (0x1 1) SlotDebugData { name: "", ty: Bool },
},
133: CastBigToArrayIndex {
dest: StatePartIndex<SmallSlots>(28), // (0xf 15) SlotDebugData { name: "", ty: UInt<4> },
src: StatePartIndex<BigSlots>(94), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::r0.addr", ty: UInt<4> },
},
134: IsNonZeroDestIsSmall {
dest: StatePartIndex<SmallSlots>(27), // (0x1 1) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(95), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::r0.en", ty: Bool },
},
135: BranchIfSmallZero {
target: 138,
value: StatePartIndex<SmallSlots>(27), // (0x1 1) SlotDebugData { name: "", ty: Bool },
},
136: MemoryReadUInt {
dest: StatePartIndex<BigSlots>(97), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::r0.data", ty: Bool },
memory: StatePartIndex<Memories>(2), // (MemoryData {
// array_type: Array<Bool, 16>,
// data: [
// // len = 0x10
// [0x0]: 0x0,
// [0x1]: 0x0,
// [0x2]: 0x0,
// [0x3]: 0x0,
// [0x4]: 0x0,
// [0x5]: 0x1,
// [0x6]: 0x0,
// [0x7]: 0x0,
// [0x8]: 0x0,
// [0x9]: 0x0,
// [0xa]: 0x0,
// [0xb]: 0x0,
// [0xc]: 0x0,
// [0xd]: 0x0,
// [0xe]: 0x0,
// [0xf]: 0x0,
// ],
// }) (),
addr: StatePartIndex<SmallSlots>(28), // (0xf 15) SlotDebugData { name: "", ty: UInt<4> },
stride: 1,
start: 0,
width: 1,
},
137: Branch {
target: 139,
},
138: Const {
dest: StatePartIndex<BigSlots>(97), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::r0.data", ty: Bool },
value: 0x0,
},
// at: module-XXXXXXXXXX.rs:6:1
139: Copy {
dest: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[2].data", ty: Bool },
src: StatePartIndex<BigSlots>(97), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::r0.data", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:4:1
140: IsNonZeroDestIsSmall {
dest: StatePartIndex<SmallSlots>(26), // (0x0 0) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(96), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::r0.clk", ty: Clock },
},
141: AndSmall {
dest: StatePartIndex<SmallSlots>(25), // (0x0 0) SlotDebugData { name: "", ty: Bool },
lhs: StatePartIndex<SmallSlots>(26), // (0x0 0) SlotDebugData { name: "", ty: Bool },
rhs: StatePartIndex<SmallSlots>(24), // (0x1 1) SlotDebugData { name: "", ty: Bool },
},
142: CastBigToArrayIndex {
dest: StatePartIndex<SmallSlots>(21), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> },
src: StatePartIndex<BigSlots>(87), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::w1.addr", ty: UInt<4> },
},
143: IsNonZeroDestIsSmall {
dest: StatePartIndex<SmallSlots>(20), // (0x0 0) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(88), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::w1.en", ty: Bool },
},
144: IsNonZeroDestIsSmall {
dest: StatePartIndex<SmallSlots>(19), // (0x0 0) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(89), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::w1.clk", ty: Clock },
},
145: AndSmall {
dest: StatePartIndex<SmallSlots>(18), // (0x0 0) SlotDebugData { name: "", ty: Bool },
lhs: StatePartIndex<SmallSlots>(19), // (0x0 0) SlotDebugData { name: "", ty: Bool },
rhs: StatePartIndex<SmallSlots>(17), // (0x1 1) SlotDebugData { name: "", ty: Bool },
},
146: CastBigToArrayIndex {
dest: StatePartIndex<SmallSlots>(16), // (0xf 15) SlotDebugData { name: "", ty: UInt<4> },
src: StatePartIndex<BigSlots>(83), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::r0.addr", ty: UInt<4> },
},
147: IsNonZeroDestIsSmall {
dest: StatePartIndex<SmallSlots>(15), // (0x1 1) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(84), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::r0.en", ty: Bool },
},
148: BranchIfSmallZero {
target: 151,
value: StatePartIndex<SmallSlots>(15), // (0x1 1) SlotDebugData { name: "", ty: Bool },
},
149: MemoryReadUInt {
dest: StatePartIndex<BigSlots>(86), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::r0.data", ty: Bool },
memory: StatePartIndex<Memories>(1), // (MemoryData {
// array_type: Array<Bool, 16>,
// data: [
// // len = 0x10
// [0x0]: 0x0,
// [0x1]: 0x0,
// [0x2]: 0x0,
// [0x3]: 0x0,
// [0x4]: 0x0,
// [0x5]: 0x0,
// [0x6]: 0x0,
// [0x7]: 0x0,
// [0x8]: 0x0,
// [0x9]: 0x0,
// [0xa]: 0x0,
// [0xb]: 0x0,
// [0xc]: 0x0,
// [0xd]: 0x0,
// [0xe]: 0x0,
// [0xf]: 0x0,
// ],
// }) (),
addr: StatePartIndex<SmallSlots>(16), // (0xf 15) SlotDebugData { name: "", ty: UInt<4> },
stride: 1,
start: 0,
width: 1,
},
150: Branch {
target: 152,
},
151: Const {
dest: StatePartIndex<BigSlots>(86), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::r0.data", ty: Bool },
value: 0x0,
},
// at: module-XXXXXXXXXX.rs:6:1
152: Copy {
dest: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[1].data", ty: Bool },
src: StatePartIndex<BigSlots>(86), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::r0.data", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:4:1
153: IsNonZeroDestIsSmall {
dest: StatePartIndex<SmallSlots>(14), // (0x0 0) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(85), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::r0.clk", ty: Clock },
},
154: AndSmall {
dest: StatePartIndex<SmallSlots>(13), // (0x0 0) SlotDebugData { name: "", ty: Bool },
lhs: StatePartIndex<SmallSlots>(14), // (0x0 0) SlotDebugData { name: "", ty: Bool },
rhs: StatePartIndex<SmallSlots>(12), // (0x1 1) SlotDebugData { name: "", ty: Bool },
},
155: CastBigToArrayIndex {
dest: StatePartIndex<SmallSlots>(9), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> },
src: StatePartIndex<BigSlots>(76), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::w1.addr", ty: UInt<4> },
},
156: IsNonZeroDestIsSmall {
dest: StatePartIndex<SmallSlots>(8), // (0x0 0) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(77), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::w1.en", ty: Bool },
},
157: IsNonZeroDestIsSmall {
dest: StatePartIndex<SmallSlots>(7), // (0x0 0) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(78), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::w1.clk", ty: Clock },
},
158: AndSmall {
dest: StatePartIndex<SmallSlots>(6), // (0x0 0) SlotDebugData { name: "", ty: Bool },
lhs: StatePartIndex<SmallSlots>(7), // (0x0 0) SlotDebugData { name: "", ty: Bool },
rhs: StatePartIndex<SmallSlots>(5), // (0x1 1) SlotDebugData { name: "", ty: Bool },
},
159: CastBigToArrayIndex {
dest: StatePartIndex<SmallSlots>(4), // (0xf 15) SlotDebugData { name: "", ty: UInt<4> },
src: StatePartIndex<BigSlots>(72), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::r0.addr", ty: UInt<4> },
},
160: IsNonZeroDestIsSmall {
dest: StatePartIndex<SmallSlots>(3), // (0x1 1) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(73), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::r0.en", ty: Bool },
},
161: BranchIfSmallZero {
target: 164,
value: StatePartIndex<SmallSlots>(3), // (0x1 1) SlotDebugData { name: "", ty: Bool },
},
162: MemoryReadUInt {
dest: StatePartIndex<BigSlots>(75), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::r0.data", ty: Bool },
memory: StatePartIndex<Memories>(0), // (MemoryData {
// array_type: Array<Bool, 16>,
// data: [
// // len = 0x10
// [0x0]: 0x0,
// [0x1]: 0x0,
// [0x2]: 0x0,
// [0x3]: 0x0,
// [0x4]: 0x0,
// [0x5]: 0x0,
// [0x6]: 0x0,
// [0x7]: 0x0,
// [0x8]: 0x0,
// [0x9]: 0x0,
// [0xa]: 0x0,
// [0xb]: 0x0,
// [0xc]: 0x0,
// [0xd]: 0x0,
// [0xe]: 0x0,
// [0xf]: 0x0,
// ],
// }) (),
addr: StatePartIndex<SmallSlots>(4), // (0xf 15) SlotDebugData { name: "", ty: UInt<4> },
stride: 1,
start: 0,
width: 1,
},
163: Branch {
target: 165,
},
164: Const {
dest: StatePartIndex<BigSlots>(75), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::r0.data", ty: Bool },
value: 0x0,
},
// at: module-XXXXXXXXXX.rs:6:1
165: Copy {
dest: StatePartIndex<BigSlots>(3), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[0].data", ty: Bool },
src: StatePartIndex<BigSlots>(75), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::r0.data", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:4:1
166: IsNonZeroDestIsSmall {
dest: StatePartIndex<SmallSlots>(2), // (0x0 0) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(74), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::r0.clk", ty: Clock },
},
167: AndSmall {
dest: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
lhs: StatePartIndex<SmallSlots>(2), // (0x0 0) SlotDebugData { name: "", ty: Bool },
rhs: StatePartIndex<SmallSlots>(0), // (0x1 1) SlotDebugData { name: "", ty: Bool },
},
168: BranchIfSmallZero {
target: 169,
value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
},
169: BranchIfSmallZero {
target: 177,
value: StatePartIndex<SmallSlots>(6), // (0x0 0) SlotDebugData { name: "", ty: Bool },
},
170: CopySmall {
dest: StatePartIndex<SmallSlots>(10), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> },
src: StatePartIndex<SmallSlots>(9), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> },
},
171: CopySmall {
dest: StatePartIndex<SmallSlots>(11), // (0x0 0) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<SmallSlots>(8), // (0x0 0) SlotDebugData { name: "", ty: Bool },
},
172: Copy {
dest: StatePartIndex<BigSlots>(81), // (0x0) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(79), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::w1.data", ty: Bool },
},
173: Copy {
dest: StatePartIndex<BigSlots>(82), // (0x1) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(80), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::w1.mask", ty: Bool },
},
174: BranchIfSmallZero {
target: 177,
value: StatePartIndex<SmallSlots>(11), // (0x0 0) SlotDebugData { name: "", ty: Bool },
},
175: BranchIfZero {
target: 177,
value: StatePartIndex<BigSlots>(82), // (0x1) SlotDebugData { name: "", ty: Bool },
},
176: MemoryWriteUInt {
value: StatePartIndex<BigSlots>(81), // (0x0) SlotDebugData { name: "", ty: Bool },
memory: StatePartIndex<Memories>(0), // (MemoryData {
// array_type: Array<Bool, 16>,
// data: [
// // len = 0x10
// [0x0]: 0x0,
// [0x1]: 0x0,
// [0x2]: 0x0,
// [0x3]: 0x0,
// [0x4]: 0x0,
// [0x5]: 0x0,
// [0x6]: 0x0,
// [0x7]: 0x0,
// [0x8]: 0x0,
// [0x9]: 0x0,
// [0xa]: 0x0,
// [0xb]: 0x0,
// [0xc]: 0x0,
// [0xd]: 0x0,
// [0xe]: 0x0,
// [0xf]: 0x0,
// ],
// }) (),
addr: StatePartIndex<SmallSlots>(10), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> },
stride: 1,
start: 0,
width: 1,
},
177: BranchIfSmallZero {
target: 178,
value: StatePartIndex<SmallSlots>(13), // (0x0 0) SlotDebugData { name: "", ty: Bool },
},
178: BranchIfSmallZero {
target: 186,
value: StatePartIndex<SmallSlots>(18), // (0x0 0) SlotDebugData { name: "", ty: Bool },
},
179: CopySmall {
dest: StatePartIndex<SmallSlots>(22), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> },
src: StatePartIndex<SmallSlots>(21), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> },
},
180: CopySmall {
dest: StatePartIndex<SmallSlots>(23), // (0x0 0) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<SmallSlots>(20), // (0x0 0) SlotDebugData { name: "", ty: Bool },
},
181: Copy {
dest: StatePartIndex<BigSlots>(92), // (0x0) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(90), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::w1.data", ty: Bool },
},
182: Copy {
dest: StatePartIndex<BigSlots>(93), // (0x1) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(91), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::w1.mask", ty: Bool },
},
183: BranchIfSmallZero {
target: 186,
value: StatePartIndex<SmallSlots>(23), // (0x0 0) SlotDebugData { name: "", ty: Bool },
},
184: BranchIfZero {
target: 186,
value: StatePartIndex<BigSlots>(93), // (0x1) SlotDebugData { name: "", ty: Bool },
},
185: MemoryWriteUInt {
value: StatePartIndex<BigSlots>(92), // (0x0) SlotDebugData { name: "", ty: Bool },
memory: StatePartIndex<Memories>(1), // (MemoryData {
// array_type: Array<Bool, 16>,
// data: [
// // len = 0x10
// [0x0]: 0x0,
// [0x1]: 0x0,
// [0x2]: 0x0,
// [0x3]: 0x0,
// [0x4]: 0x0,
// [0x5]: 0x0,
// [0x6]: 0x0,
// [0x7]: 0x0,
// [0x8]: 0x0,
// [0x9]: 0x0,
// [0xa]: 0x0,
// [0xb]: 0x0,
// [0xc]: 0x0,
// [0xd]: 0x0,
// [0xe]: 0x0,
// [0xf]: 0x0,
// ],
// }) (),
addr: StatePartIndex<SmallSlots>(22), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> },
stride: 1,
start: 0,
width: 1,
},
186: BranchIfSmallZero {
target: 187,
value: StatePartIndex<SmallSlots>(25), // (0x0 0) SlotDebugData { name: "", ty: Bool },
},
187: BranchIfSmallZero {
target: 195,
value: StatePartIndex<SmallSlots>(30), // (0x0 0) SlotDebugData { name: "", ty: Bool },
},
188: CopySmall {
dest: StatePartIndex<SmallSlots>(34), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> },
src: StatePartIndex<SmallSlots>(33), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> },
},
189: CopySmall {
dest: StatePartIndex<SmallSlots>(35), // (0x0 0) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<SmallSlots>(32), // (0x0 0) SlotDebugData { name: "", ty: Bool },
},
190: Copy {
dest: StatePartIndex<BigSlots>(103), // (0x0) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(101), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::w1.data", ty: Bool },
},
191: Copy {
dest: StatePartIndex<BigSlots>(104), // (0x1) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(102), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::w1.mask", ty: Bool },
},
192: BranchIfSmallZero {
target: 195,
value: StatePartIndex<SmallSlots>(35), // (0x0 0) SlotDebugData { name: "", ty: Bool },
},
193: BranchIfZero {
target: 195,
value: StatePartIndex<BigSlots>(104), // (0x1) SlotDebugData { name: "", ty: Bool },
},
194: MemoryWriteUInt {
value: StatePartIndex<BigSlots>(103), // (0x0) SlotDebugData { name: "", ty: Bool },
memory: StatePartIndex<Memories>(2), // (MemoryData {
// array_type: Array<Bool, 16>,
// data: [
// // len = 0x10
// [0x0]: 0x0,
// [0x1]: 0x0,
// [0x2]: 0x0,
// [0x3]: 0x0,
// [0x4]: 0x0,
// [0x5]: 0x1,
// [0x6]: 0x0,
// [0x7]: 0x0,
// [0x8]: 0x0,
// [0x9]: 0x0,
// [0xa]: 0x0,
// [0xb]: 0x0,
// [0xc]: 0x0,
// [0xd]: 0x0,
// [0xe]: 0x0,
// [0xf]: 0x0,
// ],
// }) (),
addr: StatePartIndex<SmallSlots>(34), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> },
stride: 1,
start: 0,
width: 1,
},
195: BranchIfSmallZero {
target: 196,
value: StatePartIndex<SmallSlots>(37), // (0x0 0) SlotDebugData { name: "", ty: Bool },
},
196: BranchIfSmallZero {
target: 204,
value: StatePartIndex<SmallSlots>(42), // (0x0 0) SlotDebugData { name: "", ty: Bool },
},
197: CopySmall {
dest: StatePartIndex<SmallSlots>(46), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> },
src: StatePartIndex<SmallSlots>(45), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> },
},
198: CopySmall {
dest: StatePartIndex<SmallSlots>(47), // (0x0 0) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<SmallSlots>(44), // (0x0 0) SlotDebugData { name: "", ty: Bool },
},
199: Copy {
dest: StatePartIndex<BigSlots>(114), // (0x0) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(112), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::w1.data", ty: Bool },
},
200: Copy {
dest: StatePartIndex<BigSlots>(115), // (0x1) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(113), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::w1.mask", ty: Bool },
},
201: BranchIfSmallZero {
target: 204,
value: StatePartIndex<SmallSlots>(47), // (0x0 0) SlotDebugData { name: "", ty: Bool },
},
202: BranchIfZero {
target: 204,
value: StatePartIndex<BigSlots>(115), // (0x1) SlotDebugData { name: "", ty: Bool },
},
203: MemoryWriteUInt {
value: StatePartIndex<BigSlots>(114), // (0x0) SlotDebugData { name: "", ty: Bool },
memory: StatePartIndex<Memories>(3), // (MemoryData {
// array_type: Array<Bool, 16>,
// data: [
// // len = 0x10
// [0x0]: 0x0,
// [0x1]: 0x1,
// [0x2]: 0x0,
// [0x3]: 0x0,
// [0x4]: 0x1,
// [0x5]: 0x1,
// [0x6]: 0x1,
// [0x7]: 0x1,
// [0x8]: 0x0,
// [0x9]: 0x0,
// [0xa]: 0x0,
// [0xb]: 0x0,
// [0xc]: 0x0,
// [0xd]: 0x0,
// [0xe]: 0x0,
// [0xf]: 0x0,
// ],
// }) (),
addr: StatePartIndex<SmallSlots>(46), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> },
stride: 1,
start: 0,
width: 1,
},
204: BranchIfSmallZero {
target: 205,
value: StatePartIndex<SmallSlots>(49), // (0x0 0) SlotDebugData { name: "", ty: Bool },
},
205: BranchIfSmallZero {
target: 213,
value: StatePartIndex<SmallSlots>(54), // (0x0 0) SlotDebugData { name: "", ty: Bool },
},
206: CopySmall {
dest: StatePartIndex<SmallSlots>(58), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> },
src: StatePartIndex<SmallSlots>(57), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> },
},
207: CopySmall {
dest: StatePartIndex<SmallSlots>(59), // (0x0 0) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<SmallSlots>(56), // (0x0 0) SlotDebugData { name: "", ty: Bool },
},
208: Copy {
dest: StatePartIndex<BigSlots>(125), // (0x0) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(123), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::w1.data", ty: Bool },
},
209: Copy {
dest: StatePartIndex<BigSlots>(126), // (0x1) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(124), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::w1.mask", ty: Bool },
},
210: BranchIfSmallZero {
target: 213,
value: StatePartIndex<SmallSlots>(59), // (0x0 0) SlotDebugData { name: "", ty: Bool },
},
211: BranchIfZero {
target: 213,
value: StatePartIndex<BigSlots>(126), // (0x1) SlotDebugData { name: "", ty: Bool },
},
212: MemoryWriteUInt {
value: StatePartIndex<BigSlots>(125), // (0x0) SlotDebugData { name: "", ty: Bool },
memory: StatePartIndex<Memories>(4), // (MemoryData {
// array_type: Array<Bool, 16>,
// data: [
// // len = 0x10
// [0x0]: 0x0,
// [0x1]: 0x0,
// [0x2]: 0x0,
// [0x3]: 0x0,
// [0x4]: 0x0,
// [0x5]: 0x0,
// [0x6]: 0x0,
// [0x7]: 0x0,
// [0x8]: 0x0,
// [0x9]: 0x0,
// [0xa]: 0x1,
// [0xb]: 0x0,
// [0xc]: 0x0,
// [0xd]: 0x0,
// [0xe]: 0x0,
// [0xf]: 0x0,
// ],
// }) (),
addr: StatePartIndex<SmallSlots>(58), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> },
stride: 1,
start: 0,
width: 1,
},
213: BranchIfSmallZero {
target: 214,
value: StatePartIndex<SmallSlots>(61), // (0x0 0) SlotDebugData { name: "", ty: Bool },
},
214: BranchIfSmallZero {
target: 222,
value: StatePartIndex<SmallSlots>(66), // (0x0 0) SlotDebugData { name: "", ty: Bool },
},
215: CopySmall {
dest: StatePartIndex<SmallSlots>(70), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> },
src: StatePartIndex<SmallSlots>(69), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> },
},
216: CopySmall {
dest: StatePartIndex<SmallSlots>(71), // (0x0 0) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<SmallSlots>(68), // (0x0 0) SlotDebugData { name: "", ty: Bool },
},
217: Copy {
dest: StatePartIndex<BigSlots>(136), // (0x0) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(134), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::w1.data", ty: Bool },
},
218: Copy {
dest: StatePartIndex<BigSlots>(137), // (0x1) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(135), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::w1.mask", ty: Bool },
},
219: BranchIfSmallZero {
target: 222,
value: StatePartIndex<SmallSlots>(71), // (0x0 0) SlotDebugData { name: "", ty: Bool },
},
220: BranchIfZero {
target: 222,
value: StatePartIndex<BigSlots>(137), // (0x1) SlotDebugData { name: "", ty: Bool },
},
221: MemoryWriteUInt {
value: StatePartIndex<BigSlots>(136), // (0x0) SlotDebugData { name: "", ty: Bool },
memory: StatePartIndex<Memories>(5), // (MemoryData {
// array_type: Array<Bool, 16>,
// data: [
// // len = 0x10
// [0x0]: 0x0,
// [0x1]: 0x0,
// [0x2]: 0x1,
// [0x3]: 0x0,
// [0x4]: 0x1,
// [0x5]: 0x1,
// [0x6]: 0x0,
// [0x7]: 0x0,
// [0x8]: 0x0,
// [0x9]: 0x0,
// [0xa]: 0x1,
// [0xb]: 0x1,
// [0xc]: 0x0,
// [0xd]: 0x0,
// [0xe]: 0x0,
// [0xf]: 0x0,
// ],
// }) (),
addr: StatePartIndex<SmallSlots>(70), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> },
stride: 1,
start: 0,
width: 1,
},
222: BranchIfSmallZero {
target: 223,
value: StatePartIndex<SmallSlots>(73), // (0x0 0) SlotDebugData { name: "", ty: Bool },
},
223: BranchIfSmallZero {
target: 231,
value: StatePartIndex<SmallSlots>(78), // (0x0 0) SlotDebugData { name: "", ty: Bool },
},
224: CopySmall {
dest: StatePartIndex<SmallSlots>(82), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> },
src: StatePartIndex<SmallSlots>(81), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> },
},
225: CopySmall {
dest: StatePartIndex<SmallSlots>(83), // (0x0 0) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<SmallSlots>(80), // (0x0 0) SlotDebugData { name: "", ty: Bool },
},
226: Copy {
dest: StatePartIndex<BigSlots>(147), // (0x0) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(145), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::w1.data", ty: Bool },
},
227: Copy {
dest: StatePartIndex<BigSlots>(148), // (0x1) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(146), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::w1.mask", ty: Bool },
},
228: BranchIfSmallZero {
target: 231,
value: StatePartIndex<SmallSlots>(83), // (0x0 0) SlotDebugData { name: "", ty: Bool },
},
229: BranchIfZero {
target: 231,
value: StatePartIndex<BigSlots>(148), // (0x1) SlotDebugData { name: "", ty: Bool },
},
230: MemoryWriteUInt {
value: StatePartIndex<BigSlots>(147), // (0x0) SlotDebugData { name: "", ty: Bool },
memory: StatePartIndex<Memories>(6), // (MemoryData {
// array_type: Array<Bool, 16>,
// data: [
// // len = 0x10
// [0x0]: 0x0,
// [0x1]: 0x0,
// [0x2]: 0x0,
// [0x3]: 0x0,
// [0x4]: 0x0,
// [0x5]: 0x1,
// [0x6]: 0x1,
// [0x7]: 0x0,
// [0x8]: 0x0,
// [0x9]: 0x1,
// [0xa]: 0x1,
// [0xb]: 0x1,
// [0xc]: 0x1,
// [0xd]: 0x0,
// [0xe]: 0x0,
// [0xf]: 0x0,
// ],
// }) (),
addr: StatePartIndex<SmallSlots>(82), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> },
stride: 1,
start: 0,
width: 1,
},
231: BranchIfSmallZero {
target: 232,
value: StatePartIndex<SmallSlots>(85), // (0x0 0) SlotDebugData { name: "", ty: Bool },
},
232: BranchIfSmallZero {
target: 240,
value: StatePartIndex<SmallSlots>(90), // (0x0 0) SlotDebugData { name: "", ty: Bool },
},
233: CopySmall {
dest: StatePartIndex<SmallSlots>(94), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> },
src: StatePartIndex<SmallSlots>(93), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> },
},
234: CopySmall {
dest: StatePartIndex<SmallSlots>(95), // (0x0 0) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<SmallSlots>(92), // (0x0 0) SlotDebugData { name: "", ty: Bool },
},
235: Copy {
dest: StatePartIndex<BigSlots>(158), // (0x0) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(156), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::w1.data", ty: Bool },
},
236: Copy {
dest: StatePartIndex<BigSlots>(159), // (0x1) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(157), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::w1.mask", ty: Bool },
},
237: BranchIfSmallZero {
target: 240,
value: StatePartIndex<SmallSlots>(95), // (0x0 0) SlotDebugData { name: "", ty: Bool },
},
238: BranchIfZero {
target: 240,
value: StatePartIndex<BigSlots>(159), // (0x1) SlotDebugData { name: "", ty: Bool },
},
239: MemoryWriteUInt {
value: StatePartIndex<BigSlots>(158), // (0x0) SlotDebugData { name: "", ty: Bool },
memory: StatePartIndex<Memories>(7), // (MemoryData {
// array_type: Array<Bool, 16>,
// data: [
// // len = 0x10
// [0x0]: 0x0,
// [0x1]: 0x1,
// [0x2]: 0x1,
// [0x3]: 0x0,
// [0x4]: 0x0,
// [0x5]: 0x1,
// [0x6]: 0x0,
// [0x7]: 0x1,
// [0x8]: 0x1,
// [0x9]: 0x0,
// [0xa]: 0x0,
// [0xb]: 0x0,
// [0xc]: 0x0,
// [0xd]: 0x0,
// [0xe]: 0x1,
// [0xf]: 0x0,
// ],
// }) (),
addr: StatePartIndex<SmallSlots>(94), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> },
stride: 1,
start: 0,
width: 1,
},
240: XorSmallImmediate {
dest: StatePartIndex<SmallSlots>(0), // (0x1 1) SlotDebugData { name: "", ty: Bool },
lhs: StatePartIndex<SmallSlots>(2), // (0x0 0) SlotDebugData { name: "", ty: Bool },
rhs: 0x1,
},
241: XorSmallImmediate {
dest: StatePartIndex<SmallSlots>(5), // (0x1 1) SlotDebugData { name: "", ty: Bool },
lhs: StatePartIndex<SmallSlots>(7), // (0x0 0) SlotDebugData { name: "", ty: Bool },
rhs: 0x1,
},
242: XorSmallImmediate {
dest: StatePartIndex<SmallSlots>(12), // (0x1 1) SlotDebugData { name: "", ty: Bool },
lhs: StatePartIndex<SmallSlots>(14), // (0x0 0) SlotDebugData { name: "", ty: Bool },
rhs: 0x1,
},
243: XorSmallImmediate {
dest: StatePartIndex<SmallSlots>(17), // (0x1 1) SlotDebugData { name: "", ty: Bool },
lhs: StatePartIndex<SmallSlots>(19), // (0x0 0) SlotDebugData { name: "", ty: Bool },
rhs: 0x1,
},
244: XorSmallImmediate {
dest: StatePartIndex<SmallSlots>(24), // (0x1 1) SlotDebugData { name: "", ty: Bool },
lhs: StatePartIndex<SmallSlots>(26), // (0x0 0) SlotDebugData { name: "", ty: Bool },
rhs: 0x1,
},
245: XorSmallImmediate {
dest: StatePartIndex<SmallSlots>(29), // (0x1 1) SlotDebugData { name: "", ty: Bool },
lhs: StatePartIndex<SmallSlots>(31), // (0x0 0) SlotDebugData { name: "", ty: Bool },
rhs: 0x1,
},
246: XorSmallImmediate {
dest: StatePartIndex<SmallSlots>(36), // (0x1 1) SlotDebugData { name: "", ty: Bool },
lhs: StatePartIndex<SmallSlots>(38), // (0x0 0) SlotDebugData { name: "", ty: Bool },
rhs: 0x1,
},
247: XorSmallImmediate {
dest: StatePartIndex<SmallSlots>(41), // (0x1 1) SlotDebugData { name: "", ty: Bool },
lhs: StatePartIndex<SmallSlots>(43), // (0x0 0) SlotDebugData { name: "", ty: Bool },
rhs: 0x1,
},
248: XorSmallImmediate {
dest: StatePartIndex<SmallSlots>(48), // (0x1 1) SlotDebugData { name: "", ty: Bool },
lhs: StatePartIndex<SmallSlots>(50), // (0x0 0) SlotDebugData { name: "", ty: Bool },
rhs: 0x1,
},
249: XorSmallImmediate {
dest: StatePartIndex<SmallSlots>(53), // (0x1 1) SlotDebugData { name: "", ty: Bool },
lhs: StatePartIndex<SmallSlots>(55), // (0x0 0) SlotDebugData { name: "", ty: Bool },
rhs: 0x1,
},
250: XorSmallImmediate {
dest: StatePartIndex<SmallSlots>(60), // (0x1 1) SlotDebugData { name: "", ty: Bool },
lhs: StatePartIndex<SmallSlots>(62), // (0x0 0) SlotDebugData { name: "", ty: Bool },
rhs: 0x1,
},
251: XorSmallImmediate {
dest: StatePartIndex<SmallSlots>(65), // (0x1 1) SlotDebugData { name: "", ty: Bool },
lhs: StatePartIndex<SmallSlots>(67), // (0x0 0) SlotDebugData { name: "", ty: Bool },
rhs: 0x1,
},
252: XorSmallImmediate {
dest: StatePartIndex<SmallSlots>(72), // (0x1 1) SlotDebugData { name: "", ty: Bool },
lhs: StatePartIndex<SmallSlots>(74), // (0x0 0) SlotDebugData { name: "", ty: Bool },
rhs: 0x1,
},
253: XorSmallImmediate {
dest: StatePartIndex<SmallSlots>(77), // (0x1 1) SlotDebugData { name: "", ty: Bool },
lhs: StatePartIndex<SmallSlots>(79), // (0x0 0) SlotDebugData { name: "", ty: Bool },
rhs: 0x1,
},
254: XorSmallImmediate {
dest: StatePartIndex<SmallSlots>(84), // (0x1 1) SlotDebugData { name: "", ty: Bool },
lhs: StatePartIndex<SmallSlots>(86), // (0x0 0) SlotDebugData { name: "", ty: Bool },
rhs: 0x1,
},
255: XorSmallImmediate {
dest: StatePartIndex<SmallSlots>(89), // (0x1 1) SlotDebugData { name: "", ty: Bool },
lhs: StatePartIndex<SmallSlots>(91), // (0x0 0) SlotDebugData { name: "", ty: Bool },
rhs: 0x1,
},
// at: module-XXXXXXXXXX.rs:1:1
256: Return,
],
..
},
pc: 256,
memory_write_log: [],
memories: StatePart {
value: [
MemoryData {
array_type: Array<Bool, 16>,
data: [
// len = 0x10
[0x0]: 0x0,
[0x1]: 0x0,
[0x2]: 0x0,
[0x3]: 0x0,
[0x4]: 0x0,
[0x5]: 0x0,
[0x6]: 0x0,
[0x7]: 0x0,
[0x8]: 0x0,
[0x9]: 0x0,
[0xa]: 0x0,
[0xb]: 0x0,
[0xc]: 0x0,
[0xd]: 0x0,
[0xe]: 0x0,
[0xf]: 0x0,
],
},
MemoryData {
array_type: Array<Bool, 16>,
data: [
// len = 0x10
[0x0]: 0x0,
[0x1]: 0x0,
[0x2]: 0x0,
[0x3]: 0x0,
[0x4]: 0x0,
[0x5]: 0x0,
[0x6]: 0x0,
[0x7]: 0x0,
[0x8]: 0x0,
[0x9]: 0x0,
[0xa]: 0x0,
[0xb]: 0x0,
[0xc]: 0x0,
[0xd]: 0x0,
[0xe]: 0x0,
[0xf]: 0x0,
],
},
MemoryData {
array_type: Array<Bool, 16>,
data: [
// len = 0x10
[0x0]: 0x0,
[0x1]: 0x0,
[0x2]: 0x0,
[0x3]: 0x0,
[0x4]: 0x0,
[0x5]: 0x1,
[0x6]: 0x0,
[0x7]: 0x0,
[0x8]: 0x0,
[0x9]: 0x0,
[0xa]: 0x0,
[0xb]: 0x0,
[0xc]: 0x0,
[0xd]: 0x0,
[0xe]: 0x0,
[0xf]: 0x0,
],
},
MemoryData {
array_type: Array<Bool, 16>,
data: [
// len = 0x10
[0x0]: 0x0,
[0x1]: 0x1,
[0x2]: 0x0,
[0x3]: 0x0,
[0x4]: 0x1,
[0x5]: 0x1,
[0x6]: 0x1,
[0x7]: 0x1,
[0x8]: 0x0,
[0x9]: 0x0,
[0xa]: 0x0,
[0xb]: 0x0,
[0xc]: 0x0,
[0xd]: 0x0,
[0xe]: 0x0,
[0xf]: 0x0,
],
},
MemoryData {
array_type: Array<Bool, 16>,
data: [
// len = 0x10
[0x0]: 0x0,
[0x1]: 0x0,
[0x2]: 0x0,
[0x3]: 0x0,
[0x4]: 0x0,
[0x5]: 0x0,
[0x6]: 0x0,
[0x7]: 0x0,
[0x8]: 0x0,
[0x9]: 0x0,
[0xa]: 0x1,
[0xb]: 0x0,
[0xc]: 0x0,
[0xd]: 0x0,
[0xe]: 0x0,
[0xf]: 0x0,
],
},
MemoryData {
array_type: Array<Bool, 16>,
data: [
// len = 0x10
[0x0]: 0x0,
[0x1]: 0x0,
[0x2]: 0x1,
[0x3]: 0x0,
[0x4]: 0x1,
[0x5]: 0x1,
[0x6]: 0x0,
[0x7]: 0x0,
[0x8]: 0x0,
[0x9]: 0x0,
[0xa]: 0x1,
[0xb]: 0x1,
[0xc]: 0x0,
[0xd]: 0x0,
[0xe]: 0x0,
[0xf]: 0x0,
],
},
MemoryData {
array_type: Array<Bool, 16>,
data: [
// len = 0x10
[0x0]: 0x0,
[0x1]: 0x0,
[0x2]: 0x0,
[0x3]: 0x0,
[0x4]: 0x0,
[0x5]: 0x1,
[0x6]: 0x1,
[0x7]: 0x0,
[0x8]: 0x0,
[0x9]: 0x1,
[0xa]: 0x1,
[0xb]: 0x1,
[0xc]: 0x1,
[0xd]: 0x0,
[0xe]: 0x0,
[0xf]: 0x0,
],
},
MemoryData {
array_type: Array<Bool, 16>,
data: [
// len = 0x10
[0x0]: 0x0,
[0x1]: 0x1,
[0x2]: 0x1,
[0x3]: 0x0,
[0x4]: 0x0,
[0x5]: 0x1,
[0x6]: 0x0,
[0x7]: 0x1,
[0x8]: 0x1,
[0x9]: 0x0,
[0xa]: 0x0,
[0xb]: 0x0,
[0xc]: 0x0,
[0xd]: 0x0,
[0xe]: 0x1,
[0xf]: 0x0,
],
},
],
},
small_slots: StatePart {
value: [
1,
0,
0,
1,
15,
1,
0,
0,
0,
0,
0,
0,
1,
0,
0,
1,
15,
1,
0,
0,
0,
0,
0,
0,
1,
0,
0,
1,
15,
1,
0,
0,
0,
0,
0,
0,
1,
0,
0,
1,
15,
1,
0,
0,
0,
0,
0,
0,
1,
0,
0,
1,
15,
1,
0,
0,
0,
0,
0,
0,
1,
0,
0,
1,
15,
1,
0,
0,
0,
0,
0,
0,
1,
0,
0,
1,
15,
1,
0,
0,
0,
0,
0,
0,
1,
0,
0,
1,
15,
1,
0,
0,
0,
0,
0,
0,
],
},
big_slots: StatePart {
value: [
15,
1,
0,
0,
15,
1,
0,
0,
15,
1,
0,
0,
15,
1,
0,
0,
15,
1,
0,
0,
15,
1,
0,
0,
15,
1,
0,
0,
15,
1,
0,
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
1,
0,
0,
0,
0,
1,
0,
0,
0,
0,
1,
0,
0,
0,
0,
1,
0,
0,
0,
0,
1,
0,
0,
0,
0,
1,
0,
0,
0,
0,
1,
15,
1,
0,
0,
0,
0,
0,
0,
1,
0,
1,
15,
1,
0,
0,
0,
0,
0,
0,
1,
0,
1,
15,
1,
0,
0,
0,
0,
0,
0,
1,
0,
1,
15,
1,
0,
0,
0,
0,
0,
0,
1,
0,
1,
15,
1,
0,
0,
0,
0,
0,
0,
1,
0,
1,
15,
1,
0,
0,
0,
0,
0,
0,
1,
0,
1,
15,
1,
0,
0,
0,
0,
0,
0,
1,
0,
1,
15,
1,
0,
0,
0,
0,
0,
0,
1,
0,
1,
],
},
sim_only_slots: StatePart {
value: [],
},
},
io: Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
},
main_module: SimulationModuleState {
base_targets: [
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.r,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.w,
],
uninitialized_ios: {},
io_targets: {
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.r,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.r[0],
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.r[0].addr,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.r[0].clk,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.r[0].data,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.r[0].en,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.r[1],
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.r[1].addr,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.r[1].clk,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.r[1].data,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.r[1].en,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.r[2],
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.r[2].addr,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.r[2].clk,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.r[2].data,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.r[2].en,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.r[3],
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.r[3].addr,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.r[3].clk,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.r[3].data,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.r[3].en,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.r[4],
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.r[4].addr,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.r[4].clk,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.r[4].data,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.r[4].en,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.r[5],
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.r[5].addr,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.r[5].clk,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.r[5].data,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.r[5].en,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.r[6],
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.r[6].addr,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.r[6].clk,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.r[6].data,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.r[6].en,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.r[7],
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.r[7].addr,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.r[7].clk,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.r[7].data,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.r[7].en,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.w,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.w[0],
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.w[0].addr,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.w[0].clk,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.w[0].data,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.w[0].en,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.w[0].mask,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.w[1],
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.w[1].addr,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.w[1].clk,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.w[1].data,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.w[1].en,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.w[1].mask,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.w[2],
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.w[2].addr,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.w[2].clk,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.w[2].data,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.w[2].en,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.w[2].mask,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.w[3],
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.w[3].addr,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.w[3].clk,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.w[3].data,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.w[3].en,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.w[3].mask,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.w[4],
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.w[4].addr,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.w[4].clk,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.w[4].data,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.w[4].en,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.w[4].mask,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.w[5],
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.w[5].addr,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.w[5].clk,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.w[5].data,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.w[5].en,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.w[5].mask,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.w[6],
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.w[6].addr,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.w[6].clk,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.w[6].data,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.w[6].en,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.w[6].mask,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.w[7],
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.w[7].addr,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.w[7].clk,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.w[7].data,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.w[7].en,
Instance {
name: <simulator>::many_memories,
instantiated: Module {
name: many_memories,
..
},
}.w[7].mask,
},
did_initial_settle: true,
},
extern_modules: [],
trace_decls: TraceModule {
name: "many_memories",
children: [
TraceModuleIO {
name: "r",
child: TraceArray {
name: "r",
elements: [
TraceBundle {
name: "[0]",
fields: [
TraceUInt {
location: TraceScalarId(0),
name: "addr",
ty: UInt<4>,
flow: Source,
},
TraceBool {
location: TraceScalarId(1),
name: "en",
flow: Source,
},
TraceClock {
location: TraceScalarId(2),
name: "clk",
flow: Source,
},
TraceBool {
location: TraceScalarId(3),
name: "data",
flow: Sink,
},
],
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
#[hdl(flip)] /* offset = 6 */
data: Bool,
},
flow: Source,
},
TraceBundle {
name: "[1]",
fields: [
TraceUInt {
location: TraceScalarId(4),
name: "addr",
ty: UInt<4>,
flow: Source,
},
TraceBool {
location: TraceScalarId(5),
name: "en",
flow: Source,
},
TraceClock {
location: TraceScalarId(6),
name: "clk",
flow: Source,
},
TraceBool {
location: TraceScalarId(7),
name: "data",
flow: Sink,
},
],
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
#[hdl(flip)] /* offset = 6 */
data: Bool,
},
flow: Source,
},
TraceBundle {
name: "[2]",
fields: [
TraceUInt {
location: TraceScalarId(8),
name: "addr",
ty: UInt<4>,
flow: Source,
},
TraceBool {
location: TraceScalarId(9),
name: "en",
flow: Source,
},
TraceClock {
location: TraceScalarId(10),
name: "clk",
flow: Source,
},
TraceBool {
location: TraceScalarId(11),
name: "data",
flow: Sink,
},
],
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
#[hdl(flip)] /* offset = 6 */
data: Bool,
},
flow: Source,
},
TraceBundle {
name: "[3]",
fields: [
TraceUInt {
location: TraceScalarId(12),
name: "addr",
ty: UInt<4>,
flow: Source,
},
TraceBool {
location: TraceScalarId(13),
name: "en",
flow: Source,
},
TraceClock {
location: TraceScalarId(14),
name: "clk",
flow: Source,
},
TraceBool {
location: TraceScalarId(15),
name: "data",
flow: Sink,
},
],
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
#[hdl(flip)] /* offset = 6 */
data: Bool,
},
flow: Source,
},
TraceBundle {
name: "[4]",
fields: [
TraceUInt {
location: TraceScalarId(16),
name: "addr",
ty: UInt<4>,
flow: Source,
},
TraceBool {
location: TraceScalarId(17),
name: "en",
flow: Source,
},
TraceClock {
location: TraceScalarId(18),
name: "clk",
flow: Source,
},
TraceBool {
location: TraceScalarId(19),
name: "data",
flow: Sink,
},
],
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
#[hdl(flip)] /* offset = 6 */
data: Bool,
},
flow: Source,
},
TraceBundle {
name: "[5]",
fields: [
TraceUInt {
location: TraceScalarId(20),
name: "addr",
ty: UInt<4>,
flow: Source,
},
TraceBool {
location: TraceScalarId(21),
name: "en",
flow: Source,
},
TraceClock {
location: TraceScalarId(22),
name: "clk",
flow: Source,
},
TraceBool {
location: TraceScalarId(23),
name: "data",
flow: Sink,
},
],
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
#[hdl(flip)] /* offset = 6 */
data: Bool,
},
flow: Source,
},
TraceBundle {
name: "[6]",
fields: [
TraceUInt {
location: TraceScalarId(24),
name: "addr",
ty: UInt<4>,
flow: Source,
},
TraceBool {
location: TraceScalarId(25),
name: "en",
flow: Source,
},
TraceClock {
location: TraceScalarId(26),
name: "clk",
flow: Source,
},
TraceBool {
location: TraceScalarId(27),
name: "data",
flow: Sink,
},
],
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
#[hdl(flip)] /* offset = 6 */
data: Bool,
},
flow: Source,
},
TraceBundle {
name: "[7]",
fields: [
TraceUInt {
location: TraceScalarId(28),
name: "addr",
ty: UInt<4>,
flow: Source,
},
TraceBool {
location: TraceScalarId(29),
name: "en",
flow: Source,
},
TraceClock {
location: TraceScalarId(30),
name: "clk",
flow: Source,
},
TraceBool {
location: TraceScalarId(31),
name: "data",
flow: Sink,
},
],
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
#[hdl(flip)] /* offset = 6 */
data: Bool,
},
flow: Source,
},
],
ty: Array<Bundle {addr: UInt<4>, en: Bool, clk: Clock, #[hdl(flip)] data: Bool}, 8>,
flow: Source,
},
ty: Array<Bundle {addr: UInt<4>, en: Bool, clk: Clock, #[hdl(flip)] data: Bool}, 8>,
flow: Source,
},
TraceModuleIO {
name: "w",
child: TraceArray {
name: "w",
elements: [
TraceBundle {
name: "[0]",
fields: [
TraceUInt {
location: TraceScalarId(32),
name: "addr",
ty: UInt<4>,
flow: Source,
},
TraceBool {
location: TraceScalarId(33),
name: "en",
flow: Source,
},
TraceClock {
location: TraceScalarId(34),
name: "clk",
flow: Source,
},
TraceBool {
location: TraceScalarId(35),
name: "data",
flow: Source,
},
TraceBool {
location: TraceScalarId(36),
name: "mask",
flow: Source,
},
],
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
/* offset = 6 */
data: Bool,
/* offset = 7 */
mask: Bool,
},
flow: Source,
},
TraceBundle {
name: "[1]",
fields: [
TraceUInt {
location: TraceScalarId(37),
name: "addr",
ty: UInt<4>,
flow: Source,
},
TraceBool {
location: TraceScalarId(38),
name: "en",
flow: Source,
},
TraceClock {
location: TraceScalarId(39),
name: "clk",
flow: Source,
},
TraceBool {
location: TraceScalarId(40),
name: "data",
flow: Source,
},
TraceBool {
location: TraceScalarId(41),
name: "mask",
flow: Source,
},
],
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
/* offset = 6 */
data: Bool,
/* offset = 7 */
mask: Bool,
},
flow: Source,
},
TraceBundle {
name: "[2]",
fields: [
TraceUInt {
location: TraceScalarId(42),
name: "addr",
ty: UInt<4>,
flow: Source,
},
TraceBool {
location: TraceScalarId(43),
name: "en",
flow: Source,
},
TraceClock {
location: TraceScalarId(44),
name: "clk",
flow: Source,
},
TraceBool {
location: TraceScalarId(45),
name: "data",
flow: Source,
},
TraceBool {
location: TraceScalarId(46),
name: "mask",
flow: Source,
},
],
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
/* offset = 6 */
data: Bool,
/* offset = 7 */
mask: Bool,
},
flow: Source,
},
TraceBundle {
name: "[3]",
fields: [
TraceUInt {
location: TraceScalarId(47),
name: "addr",
ty: UInt<4>,
flow: Source,
},
TraceBool {
location: TraceScalarId(48),
name: "en",
flow: Source,
},
TraceClock {
location: TraceScalarId(49),
name: "clk",
flow: Source,
},
TraceBool {
location: TraceScalarId(50),
name: "data",
flow: Source,
},
TraceBool {
location: TraceScalarId(51),
name: "mask",
flow: Source,
},
],
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
/* offset = 6 */
data: Bool,
/* offset = 7 */
mask: Bool,
},
flow: Source,
},
TraceBundle {
name: "[4]",
fields: [
TraceUInt {
location: TraceScalarId(52),
name: "addr",
ty: UInt<4>,
flow: Source,
},
TraceBool {
location: TraceScalarId(53),
name: "en",
flow: Source,
},
TraceClock {
location: TraceScalarId(54),
name: "clk",
flow: Source,
},
TraceBool {
location: TraceScalarId(55),
name: "data",
flow: Source,
},
TraceBool {
location: TraceScalarId(56),
name: "mask",
flow: Source,
},
],
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
/* offset = 6 */
data: Bool,
/* offset = 7 */
mask: Bool,
},
flow: Source,
},
TraceBundle {
name: "[5]",
fields: [
TraceUInt {
location: TraceScalarId(57),
name: "addr",
ty: UInt<4>,
flow: Source,
},
TraceBool {
location: TraceScalarId(58),
name: "en",
flow: Source,
},
TraceClock {
location: TraceScalarId(59),
name: "clk",
flow: Source,
},
TraceBool {
location: TraceScalarId(60),
name: "data",
flow: Source,
},
TraceBool {
location: TraceScalarId(61),
name: "mask",
flow: Source,
},
],
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
/* offset = 6 */
data: Bool,
/* offset = 7 */
mask: Bool,
},
flow: Source,
},
TraceBundle {
name: "[6]",
fields: [
TraceUInt {
location: TraceScalarId(62),
name: "addr",
ty: UInt<4>,
flow: Source,
},
TraceBool {
location: TraceScalarId(63),
name: "en",
flow: Source,
},
TraceClock {
location: TraceScalarId(64),
name: "clk",
flow: Source,
},
TraceBool {
location: TraceScalarId(65),
name: "data",
flow: Source,
},
TraceBool {
location: TraceScalarId(66),
name: "mask",
flow: Source,
},
],
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
/* offset = 6 */
data: Bool,
/* offset = 7 */
mask: Bool,
},
flow: Source,
},
TraceBundle {
name: "[7]",
fields: [
TraceUInt {
location: TraceScalarId(67),
name: "addr",
ty: UInt<4>,
flow: Source,
},
TraceBool {
location: TraceScalarId(68),
name: "en",
flow: Source,
},
TraceClock {
location: TraceScalarId(69),
name: "clk",
flow: Source,
},
TraceBool {
location: TraceScalarId(70),
name: "data",
flow: Source,
},
TraceBool {
location: TraceScalarId(71),
name: "mask",
flow: Source,
},
],
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
/* offset = 6 */
data: Bool,
/* offset = 7 */
mask: Bool,
},
flow: Source,
},
],
ty: Array<Bundle {addr: UInt<4>, en: Bool, clk: Clock, data: Bool, mask: Bool}, 8>,
flow: Source,
},
ty: Array<Bundle {addr: UInt<4>, en: Bool, clk: Clock, data: Bool, mask: Bool}, 8>,
flow: Source,
},
TraceMem {
id: TraceMemoryId(0),
name: "mem_0",
stride: 1,
element_type: TraceBool {
location: TraceMemoryLocation {
id: TraceMemoryId(0),
depth: 16,
stride: 1,
start: 0,
len: 1,
},
name: "mem_0",
flow: Duplex,
},
ports: [
TraceMemPort {
name: "r0",
bundle: TraceBundle {
name: "r0",
fields: [
TraceUInt {
location: TraceScalarId(72),
name: "addr",
ty: UInt<4>,
flow: Sink,
},
TraceBool {
location: TraceScalarId(73),
name: "en",
flow: Sink,
},
TraceClock {
location: TraceScalarId(74),
name: "clk",
flow: Sink,
},
TraceBool {
location: TraceScalarId(75),
name: "data",
flow: Source,
},
],
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
#[hdl(flip)] /* offset = 6 */
data: Bool,
},
flow: Sink,
},
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
#[hdl(flip)] /* offset = 6 */
data: Bool,
},
},
TraceMemPort {
name: "w1",
bundle: TraceBundle {
name: "w1",
fields: [
TraceUInt {
location: TraceScalarId(76),
name: "addr",
ty: UInt<4>,
flow: Sink,
},
TraceBool {
location: TraceScalarId(77),
name: "en",
flow: Sink,
},
TraceClock {
location: TraceScalarId(78),
name: "clk",
flow: Sink,
},
TraceBool {
location: TraceScalarId(79),
name: "data",
flow: Sink,
},
TraceBool {
location: TraceScalarId(80),
name: "mask",
flow: Sink,
},
],
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
/* offset = 6 */
data: Bool,
/* offset = 7 */
mask: Bool,
},
flow: Sink,
},
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
/* offset = 6 */
data: Bool,
/* offset = 7 */
mask: Bool,
},
},
],
array_type: Array<Bool, 16>,
},
TraceMem {
id: TraceMemoryId(1),
name: "mem_1",
stride: 1,
element_type: TraceBool {
location: TraceMemoryLocation {
id: TraceMemoryId(1),
depth: 16,
stride: 1,
start: 0,
len: 1,
},
name: "mem_1",
flow: Duplex,
},
ports: [
TraceMemPort {
name: "r0",
bundle: TraceBundle {
name: "r0",
fields: [
TraceUInt {
location: TraceScalarId(81),
name: "addr",
ty: UInt<4>,
flow: Sink,
},
TraceBool {
location: TraceScalarId(82),
name: "en",
flow: Sink,
},
TraceClock {
location: TraceScalarId(83),
name: "clk",
flow: Sink,
},
TraceBool {
location: TraceScalarId(84),
name: "data",
flow: Source,
},
],
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
#[hdl(flip)] /* offset = 6 */
data: Bool,
},
flow: Sink,
},
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
#[hdl(flip)] /* offset = 6 */
data: Bool,
},
},
TraceMemPort {
name: "w1",
bundle: TraceBundle {
name: "w1",
fields: [
TraceUInt {
location: TraceScalarId(85),
name: "addr",
ty: UInt<4>,
flow: Sink,
},
TraceBool {
location: TraceScalarId(86),
name: "en",
flow: Sink,
},
TraceClock {
location: TraceScalarId(87),
name: "clk",
flow: Sink,
},
TraceBool {
location: TraceScalarId(88),
name: "data",
flow: Sink,
},
TraceBool {
location: TraceScalarId(89),
name: "mask",
flow: Sink,
},
],
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
/* offset = 6 */
data: Bool,
/* offset = 7 */
mask: Bool,
},
flow: Sink,
},
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
/* offset = 6 */
data: Bool,
/* offset = 7 */
mask: Bool,
},
},
],
array_type: Array<Bool, 16>,
},
TraceMem {
id: TraceMemoryId(2),
name: "mem_2",
stride: 1,
element_type: TraceBool {
location: TraceMemoryLocation {
id: TraceMemoryId(2),
depth: 16,
stride: 1,
start: 0,
len: 1,
},
name: "mem_2",
flow: Duplex,
},
ports: [
TraceMemPort {
name: "r0",
bundle: TraceBundle {
name: "r0",
fields: [
TraceUInt {
location: TraceScalarId(90),
name: "addr",
ty: UInt<4>,
flow: Sink,
},
TraceBool {
location: TraceScalarId(91),
name: "en",
flow: Sink,
},
TraceClock {
location: TraceScalarId(92),
name: "clk",
flow: Sink,
},
TraceBool {
location: TraceScalarId(93),
name: "data",
flow: Source,
},
],
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
#[hdl(flip)] /* offset = 6 */
data: Bool,
},
flow: Sink,
},
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
#[hdl(flip)] /* offset = 6 */
data: Bool,
},
},
TraceMemPort {
name: "w1",
bundle: TraceBundle {
name: "w1",
fields: [
TraceUInt {
location: TraceScalarId(94),
name: "addr",
ty: UInt<4>,
flow: Sink,
},
TraceBool {
location: TraceScalarId(95),
name: "en",
flow: Sink,
},
TraceClock {
location: TraceScalarId(96),
name: "clk",
flow: Sink,
},
TraceBool {
location: TraceScalarId(97),
name: "data",
flow: Sink,
},
TraceBool {
location: TraceScalarId(98),
name: "mask",
flow: Sink,
},
],
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
/* offset = 6 */
data: Bool,
/* offset = 7 */
mask: Bool,
},
flow: Sink,
},
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
/* offset = 6 */
data: Bool,
/* offset = 7 */
mask: Bool,
},
},
],
array_type: Array<Bool, 16>,
},
TraceMem {
id: TraceMemoryId(3),
name: "mem_3",
stride: 1,
element_type: TraceBool {
location: TraceMemoryLocation {
id: TraceMemoryId(3),
depth: 16,
stride: 1,
start: 0,
len: 1,
},
name: "mem_3",
flow: Duplex,
},
ports: [
TraceMemPort {
name: "r0",
bundle: TraceBundle {
name: "r0",
fields: [
TraceUInt {
location: TraceScalarId(99),
name: "addr",
ty: UInt<4>,
flow: Sink,
},
TraceBool {
location: TraceScalarId(100),
name: "en",
flow: Sink,
},
TraceClock {
location: TraceScalarId(101),
name: "clk",
flow: Sink,
},
TraceBool {
location: TraceScalarId(102),
name: "data",
flow: Source,
},
],
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
#[hdl(flip)] /* offset = 6 */
data: Bool,
},
flow: Sink,
},
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
#[hdl(flip)] /* offset = 6 */
data: Bool,
},
},
TraceMemPort {
name: "w1",
bundle: TraceBundle {
name: "w1",
fields: [
TraceUInt {
location: TraceScalarId(103),
name: "addr",
ty: UInt<4>,
flow: Sink,
},
TraceBool {
location: TraceScalarId(104),
name: "en",
flow: Sink,
},
TraceClock {
location: TraceScalarId(105),
name: "clk",
flow: Sink,
},
TraceBool {
location: TraceScalarId(106),
name: "data",
flow: Sink,
},
TraceBool {
location: TraceScalarId(107),
name: "mask",
flow: Sink,
},
],
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
/* offset = 6 */
data: Bool,
/* offset = 7 */
mask: Bool,
},
flow: Sink,
},
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
/* offset = 6 */
data: Bool,
/* offset = 7 */
mask: Bool,
},
},
],
array_type: Array<Bool, 16>,
},
TraceMem {
id: TraceMemoryId(4),
name: "mem_4",
stride: 1,
element_type: TraceBool {
location: TraceMemoryLocation {
id: TraceMemoryId(4),
depth: 16,
stride: 1,
start: 0,
len: 1,
},
name: "mem_4",
flow: Duplex,
},
ports: [
TraceMemPort {
name: "r0",
bundle: TraceBundle {
name: "r0",
fields: [
TraceUInt {
location: TraceScalarId(108),
name: "addr",
ty: UInt<4>,
flow: Sink,
},
TraceBool {
location: TraceScalarId(109),
name: "en",
flow: Sink,
},
TraceClock {
location: TraceScalarId(110),
name: "clk",
flow: Sink,
},
TraceBool {
location: TraceScalarId(111),
name: "data",
flow: Source,
},
],
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
#[hdl(flip)] /* offset = 6 */
data: Bool,
},
flow: Sink,
},
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
#[hdl(flip)] /* offset = 6 */
data: Bool,
},
},
TraceMemPort {
name: "w1",
bundle: TraceBundle {
name: "w1",
fields: [
TraceUInt {
location: TraceScalarId(112),
name: "addr",
ty: UInt<4>,
flow: Sink,
},
TraceBool {
location: TraceScalarId(113),
name: "en",
flow: Sink,
},
TraceClock {
location: TraceScalarId(114),
name: "clk",
flow: Sink,
},
TraceBool {
location: TraceScalarId(115),
name: "data",
flow: Sink,
},
TraceBool {
location: TraceScalarId(116),
name: "mask",
flow: Sink,
},
],
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
/* offset = 6 */
data: Bool,
/* offset = 7 */
mask: Bool,
},
flow: Sink,
},
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
/* offset = 6 */
data: Bool,
/* offset = 7 */
mask: Bool,
},
},
],
array_type: Array<Bool, 16>,
},
TraceMem {
id: TraceMemoryId(5),
name: "mem_5",
stride: 1,
element_type: TraceBool {
location: TraceMemoryLocation {
id: TraceMemoryId(5),
depth: 16,
stride: 1,
start: 0,
len: 1,
},
name: "mem_5",
flow: Duplex,
},
ports: [
TraceMemPort {
name: "r0",
bundle: TraceBundle {
name: "r0",
fields: [
TraceUInt {
location: TraceScalarId(117),
name: "addr",
ty: UInt<4>,
flow: Sink,
},
TraceBool {
location: TraceScalarId(118),
name: "en",
flow: Sink,
},
TraceClock {
location: TraceScalarId(119),
name: "clk",
flow: Sink,
},
TraceBool {
location: TraceScalarId(120),
name: "data",
flow: Source,
},
],
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
#[hdl(flip)] /* offset = 6 */
data: Bool,
},
flow: Sink,
},
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
#[hdl(flip)] /* offset = 6 */
data: Bool,
},
},
TraceMemPort {
name: "w1",
bundle: TraceBundle {
name: "w1",
fields: [
TraceUInt {
location: TraceScalarId(121),
name: "addr",
ty: UInt<4>,
flow: Sink,
},
TraceBool {
location: TraceScalarId(122),
name: "en",
flow: Sink,
},
TraceClock {
location: TraceScalarId(123),
name: "clk",
flow: Sink,
},
TraceBool {
location: TraceScalarId(124),
name: "data",
flow: Sink,
},
TraceBool {
location: TraceScalarId(125),
name: "mask",
flow: Sink,
},
],
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
/* offset = 6 */
data: Bool,
/* offset = 7 */
mask: Bool,
},
flow: Sink,
},
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
/* offset = 6 */
data: Bool,
/* offset = 7 */
mask: Bool,
},
},
],
array_type: Array<Bool, 16>,
},
TraceMem {
id: TraceMemoryId(6),
name: "mem_6",
stride: 1,
element_type: TraceBool {
location: TraceMemoryLocation {
id: TraceMemoryId(6),
depth: 16,
stride: 1,
start: 0,
len: 1,
},
name: "mem_6",
flow: Duplex,
},
ports: [
TraceMemPort {
name: "r0",
bundle: TraceBundle {
name: "r0",
fields: [
TraceUInt {
location: TraceScalarId(126),
name: "addr",
ty: UInt<4>,
flow: Sink,
},
TraceBool {
location: TraceScalarId(127),
name: "en",
flow: Sink,
},
TraceClock {
location: TraceScalarId(128),
name: "clk",
flow: Sink,
},
TraceBool {
location: TraceScalarId(129),
name: "data",
flow: Source,
},
],
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
#[hdl(flip)] /* offset = 6 */
data: Bool,
},
flow: Sink,
},
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
#[hdl(flip)] /* offset = 6 */
data: Bool,
},
},
TraceMemPort {
name: "w1",
bundle: TraceBundle {
name: "w1",
fields: [
TraceUInt {
location: TraceScalarId(130),
name: "addr",
ty: UInt<4>,
flow: Sink,
},
TraceBool {
location: TraceScalarId(131),
name: "en",
flow: Sink,
},
TraceClock {
location: TraceScalarId(132),
name: "clk",
flow: Sink,
},
TraceBool {
location: TraceScalarId(133),
name: "data",
flow: Sink,
},
TraceBool {
location: TraceScalarId(134),
name: "mask",
flow: Sink,
},
],
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
/* offset = 6 */
data: Bool,
/* offset = 7 */
mask: Bool,
},
flow: Sink,
},
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
/* offset = 6 */
data: Bool,
/* offset = 7 */
mask: Bool,
},
},
],
array_type: Array<Bool, 16>,
},
TraceMem {
id: TraceMemoryId(7),
name: "mem_7",
stride: 1,
element_type: TraceBool {
location: TraceMemoryLocation {
id: TraceMemoryId(7),
depth: 16,
stride: 1,
start: 0,
len: 1,
},
name: "mem_7",
flow: Duplex,
},
ports: [
TraceMemPort {
name: "r0",
bundle: TraceBundle {
name: "r0",
fields: [
TraceUInt {
location: TraceScalarId(135),
name: "addr",
ty: UInt<4>,
flow: Sink,
},
TraceBool {
location: TraceScalarId(136),
name: "en",
flow: Sink,
},
TraceClock {
location: TraceScalarId(137),
name: "clk",
flow: Sink,
},
TraceBool {
location: TraceScalarId(138),
name: "data",
flow: Source,
},
],
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
#[hdl(flip)] /* offset = 6 */
data: Bool,
},
flow: Sink,
},
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
#[hdl(flip)] /* offset = 6 */
data: Bool,
},
},
TraceMemPort {
name: "w1",
bundle: TraceBundle {
name: "w1",
fields: [
TraceUInt {
location: TraceScalarId(139),
name: "addr",
ty: UInt<4>,
flow: Sink,
},
TraceBool {
location: TraceScalarId(140),
name: "en",
flow: Sink,
},
TraceClock {
location: TraceScalarId(141),
name: "clk",
flow: Sink,
},
TraceBool {
location: TraceScalarId(142),
name: "data",
flow: Sink,
},
TraceBool {
location: TraceScalarId(143),
name: "mask",
flow: Sink,
},
],
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
/* offset = 6 */
data: Bool,
/* offset = 7 */
mask: Bool,
},
flow: Sink,
},
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
/* offset = 6 */
data: Bool,
/* offset = 7 */
mask: Bool,
},
},
],
array_type: Array<Bool, 16>,
},
],
},
traces: [
SimTrace {
id: TraceScalarId(0),
kind: BigUInt {
index: StatePartIndex<BigSlots>(0),
ty: UInt<4>,
},
state: 0xf,
last_state: 0xf,
},
SimTrace {
id: TraceScalarId(1),
kind: BigBool {
index: StatePartIndex<BigSlots>(1),
},
state: 0x1,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(2),
kind: BigClock {
index: StatePartIndex<BigSlots>(2),
},
state: 0x0,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(3),
kind: BigBool {
index: StatePartIndex<BigSlots>(3),
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(4),
kind: BigUInt {
index: StatePartIndex<BigSlots>(4),
ty: UInt<4>,
},
state: 0xf,
last_state: 0xf,
},
SimTrace {
id: TraceScalarId(5),
kind: BigBool {
index: StatePartIndex<BigSlots>(5),
},
state: 0x1,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(6),
kind: BigClock {
index: StatePartIndex<BigSlots>(6),
},
state: 0x0,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(7),
kind: BigBool {
index: StatePartIndex<BigSlots>(7),
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(8),
kind: BigUInt {
index: StatePartIndex<BigSlots>(8),
ty: UInt<4>,
},
state: 0xf,
last_state: 0xf,
},
SimTrace {
id: TraceScalarId(9),
kind: BigBool {
index: StatePartIndex<BigSlots>(9),
},
state: 0x1,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(10),
kind: BigClock {
index: StatePartIndex<BigSlots>(10),
},
state: 0x0,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(11),
kind: BigBool {
index: StatePartIndex<BigSlots>(11),
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(12),
kind: BigUInt {
index: StatePartIndex<BigSlots>(12),
ty: UInt<4>,
},
state: 0xf,
last_state: 0xf,
},
SimTrace {
id: TraceScalarId(13),
kind: BigBool {
index: StatePartIndex<BigSlots>(13),
},
state: 0x1,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(14),
kind: BigClock {
index: StatePartIndex<BigSlots>(14),
},
state: 0x0,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(15),
kind: BigBool {
index: StatePartIndex<BigSlots>(15),
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(16),
kind: BigUInt {
index: StatePartIndex<BigSlots>(16),
ty: UInt<4>,
},
state: 0xf,
last_state: 0xf,
},
SimTrace {
id: TraceScalarId(17),
kind: BigBool {
index: StatePartIndex<BigSlots>(17),
},
state: 0x1,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(18),
kind: BigClock {
index: StatePartIndex<BigSlots>(18),
},
state: 0x0,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(19),
kind: BigBool {
index: StatePartIndex<BigSlots>(19),
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(20),
kind: BigUInt {
index: StatePartIndex<BigSlots>(20),
ty: UInt<4>,
},
state: 0xf,
last_state: 0xf,
},
SimTrace {
id: TraceScalarId(21),
kind: BigBool {
index: StatePartIndex<BigSlots>(21),
},
state: 0x1,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(22),
kind: BigClock {
index: StatePartIndex<BigSlots>(22),
},
state: 0x0,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(23),
kind: BigBool {
index: StatePartIndex<BigSlots>(23),
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(24),
kind: BigUInt {
index: StatePartIndex<BigSlots>(24),
ty: UInt<4>,
},
state: 0xf,
last_state: 0xf,
},
SimTrace {
id: TraceScalarId(25),
kind: BigBool {
index: StatePartIndex<BigSlots>(25),
},
state: 0x1,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(26),
kind: BigClock {
index: StatePartIndex<BigSlots>(26),
},
state: 0x0,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(27),
kind: BigBool {
index: StatePartIndex<BigSlots>(27),
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(28),
kind: BigUInt {
index: StatePartIndex<BigSlots>(28),
ty: UInt<4>,
},
state: 0xf,
last_state: 0xf,
},
SimTrace {
id: TraceScalarId(29),
kind: BigBool {
index: StatePartIndex<BigSlots>(29),
},
state: 0x1,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(30),
kind: BigClock {
index: StatePartIndex<BigSlots>(30),
},
state: 0x0,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(31),
kind: BigBool {
index: StatePartIndex<BigSlots>(31),
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(32),
kind: BigUInt {
index: StatePartIndex<BigSlots>(32),
ty: UInt<4>,
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(33),
kind: BigBool {
index: StatePartIndex<BigSlots>(33),
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(34),
kind: BigClock {
index: StatePartIndex<BigSlots>(34),
},
state: 0x0,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(35),
kind: BigBool {
index: StatePartIndex<BigSlots>(35),
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(36),
kind: BigBool {
index: StatePartIndex<BigSlots>(36),
},
state: 0x1,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(37),
kind: BigUInt {
index: StatePartIndex<BigSlots>(37),
ty: UInt<4>,
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(38),
kind: BigBool {
index: StatePartIndex<BigSlots>(38),
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(39),
kind: BigClock {
index: StatePartIndex<BigSlots>(39),
},
state: 0x0,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(40),
kind: BigBool {
index: StatePartIndex<BigSlots>(40),
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(41),
kind: BigBool {
index: StatePartIndex<BigSlots>(41),
},
state: 0x1,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(42),
kind: BigUInt {
index: StatePartIndex<BigSlots>(42),
ty: UInt<4>,
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(43),
kind: BigBool {
index: StatePartIndex<BigSlots>(43),
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(44),
kind: BigClock {
index: StatePartIndex<BigSlots>(44),
},
state: 0x0,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(45),
kind: BigBool {
index: StatePartIndex<BigSlots>(45),
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(46),
kind: BigBool {
index: StatePartIndex<BigSlots>(46),
},
state: 0x1,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(47),
kind: BigUInt {
index: StatePartIndex<BigSlots>(47),
ty: UInt<4>,
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(48),
kind: BigBool {
index: StatePartIndex<BigSlots>(48),
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(49),
kind: BigClock {
index: StatePartIndex<BigSlots>(49),
},
state: 0x0,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(50),
kind: BigBool {
index: StatePartIndex<BigSlots>(50),
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(51),
kind: BigBool {
index: StatePartIndex<BigSlots>(51),
},
state: 0x1,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(52),
kind: BigUInt {
index: StatePartIndex<BigSlots>(52),
ty: UInt<4>,
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(53),
kind: BigBool {
index: StatePartIndex<BigSlots>(53),
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(54),
kind: BigClock {
index: StatePartIndex<BigSlots>(54),
},
state: 0x0,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(55),
kind: BigBool {
index: StatePartIndex<BigSlots>(55),
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(56),
kind: BigBool {
index: StatePartIndex<BigSlots>(56),
},
state: 0x1,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(57),
kind: BigUInt {
index: StatePartIndex<BigSlots>(57),
ty: UInt<4>,
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(58),
kind: BigBool {
index: StatePartIndex<BigSlots>(58),
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(59),
kind: BigClock {
index: StatePartIndex<BigSlots>(59),
},
state: 0x0,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(60),
kind: BigBool {
index: StatePartIndex<BigSlots>(60),
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(61),
kind: BigBool {
index: StatePartIndex<BigSlots>(61),
},
state: 0x1,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(62),
kind: BigUInt {
index: StatePartIndex<BigSlots>(62),
ty: UInt<4>,
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(63),
kind: BigBool {
index: StatePartIndex<BigSlots>(63),
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(64),
kind: BigClock {
index: StatePartIndex<BigSlots>(64),
},
state: 0x0,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(65),
kind: BigBool {
index: StatePartIndex<BigSlots>(65),
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(66),
kind: BigBool {
index: StatePartIndex<BigSlots>(66),
},
state: 0x1,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(67),
kind: BigUInt {
index: StatePartIndex<BigSlots>(67),
ty: UInt<4>,
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(68),
kind: BigBool {
index: StatePartIndex<BigSlots>(68),
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(69),
kind: BigClock {
index: StatePartIndex<BigSlots>(69),
},
state: 0x0,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(70),
kind: BigBool {
index: StatePartIndex<BigSlots>(70),
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(71),
kind: BigBool {
index: StatePartIndex<BigSlots>(71),
},
state: 0x1,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(72),
kind: BigUInt {
index: StatePartIndex<BigSlots>(72),
ty: UInt<4>,
},
state: 0xf,
last_state: 0xf,
},
SimTrace {
id: TraceScalarId(73),
kind: BigBool {
index: StatePartIndex<BigSlots>(73),
},
state: 0x1,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(74),
kind: BigClock {
index: StatePartIndex<BigSlots>(74),
},
state: 0x0,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(75),
kind: BigBool {
index: StatePartIndex<BigSlots>(75),
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(76),
kind: BigUInt {
index: StatePartIndex<BigSlots>(76),
ty: UInt<4>,
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(77),
kind: BigBool {
index: StatePartIndex<BigSlots>(77),
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(78),
kind: BigClock {
index: StatePartIndex<BigSlots>(78),
},
state: 0x0,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(79),
kind: BigBool {
index: StatePartIndex<BigSlots>(79),
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(80),
kind: BigBool {
index: StatePartIndex<BigSlots>(80),
},
state: 0x1,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(81),
kind: BigUInt {
index: StatePartIndex<BigSlots>(83),
ty: UInt<4>,
},
state: 0xf,
last_state: 0xf,
},
SimTrace {
id: TraceScalarId(82),
kind: BigBool {
index: StatePartIndex<BigSlots>(84),
},
state: 0x1,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(83),
kind: BigClock {
index: StatePartIndex<BigSlots>(85),
},
state: 0x0,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(84),
kind: BigBool {
index: StatePartIndex<BigSlots>(86),
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(85),
kind: BigUInt {
index: StatePartIndex<BigSlots>(87),
ty: UInt<4>,
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(86),
kind: BigBool {
index: StatePartIndex<BigSlots>(88),
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(87),
kind: BigClock {
index: StatePartIndex<BigSlots>(89),
},
state: 0x0,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(88),
kind: BigBool {
index: StatePartIndex<BigSlots>(90),
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(89),
kind: BigBool {
index: StatePartIndex<BigSlots>(91),
},
state: 0x1,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(90),
kind: BigUInt {
index: StatePartIndex<BigSlots>(94),
ty: UInt<4>,
},
state: 0xf,
last_state: 0xf,
},
SimTrace {
id: TraceScalarId(91),
kind: BigBool {
index: StatePartIndex<BigSlots>(95),
},
state: 0x1,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(92),
kind: BigClock {
index: StatePartIndex<BigSlots>(96),
},
state: 0x0,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(93),
kind: BigBool {
index: StatePartIndex<BigSlots>(97),
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(94),
kind: BigUInt {
index: StatePartIndex<BigSlots>(98),
ty: UInt<4>,
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(95),
kind: BigBool {
index: StatePartIndex<BigSlots>(99),
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(96),
kind: BigClock {
index: StatePartIndex<BigSlots>(100),
},
state: 0x0,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(97),
kind: BigBool {
index: StatePartIndex<BigSlots>(101),
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(98),
kind: BigBool {
index: StatePartIndex<BigSlots>(102),
},
state: 0x1,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(99),
kind: BigUInt {
index: StatePartIndex<BigSlots>(105),
ty: UInt<4>,
},
state: 0xf,
last_state: 0xf,
},
SimTrace {
id: TraceScalarId(100),
kind: BigBool {
index: StatePartIndex<BigSlots>(106),
},
state: 0x1,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(101),
kind: BigClock {
index: StatePartIndex<BigSlots>(107),
},
state: 0x0,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(102),
kind: BigBool {
index: StatePartIndex<BigSlots>(108),
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(103),
kind: BigUInt {
index: StatePartIndex<BigSlots>(109),
ty: UInt<4>,
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(104),
kind: BigBool {
index: StatePartIndex<BigSlots>(110),
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(105),
kind: BigClock {
index: StatePartIndex<BigSlots>(111),
},
state: 0x0,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(106),
kind: BigBool {
index: StatePartIndex<BigSlots>(112),
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(107),
kind: BigBool {
index: StatePartIndex<BigSlots>(113),
},
state: 0x1,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(108),
kind: BigUInt {
index: StatePartIndex<BigSlots>(116),
ty: UInt<4>,
},
state: 0xf,
last_state: 0xf,
},
SimTrace {
id: TraceScalarId(109),
kind: BigBool {
index: StatePartIndex<BigSlots>(117),
},
state: 0x1,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(110),
kind: BigClock {
index: StatePartIndex<BigSlots>(118),
},
state: 0x0,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(111),
kind: BigBool {
index: StatePartIndex<BigSlots>(119),
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(112),
kind: BigUInt {
index: StatePartIndex<BigSlots>(120),
ty: UInt<4>,
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(113),
kind: BigBool {
index: StatePartIndex<BigSlots>(121),
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(114),
kind: BigClock {
index: StatePartIndex<BigSlots>(122),
},
state: 0x0,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(115),
kind: BigBool {
index: StatePartIndex<BigSlots>(123),
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(116),
kind: BigBool {
index: StatePartIndex<BigSlots>(124),
},
state: 0x1,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(117),
kind: BigUInt {
index: StatePartIndex<BigSlots>(127),
ty: UInt<4>,
},
state: 0xf,
last_state: 0xf,
},
SimTrace {
id: TraceScalarId(118),
kind: BigBool {
index: StatePartIndex<BigSlots>(128),
},
state: 0x1,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(119),
kind: BigClock {
index: StatePartIndex<BigSlots>(129),
},
state: 0x0,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(120),
kind: BigBool {
index: StatePartIndex<BigSlots>(130),
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(121),
kind: BigUInt {
index: StatePartIndex<BigSlots>(131),
ty: UInt<4>,
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(122),
kind: BigBool {
index: StatePartIndex<BigSlots>(132),
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(123),
kind: BigClock {
index: StatePartIndex<BigSlots>(133),
},
state: 0x0,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(124),
kind: BigBool {
index: StatePartIndex<BigSlots>(134),
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(125),
kind: BigBool {
index: StatePartIndex<BigSlots>(135),
},
state: 0x1,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(126),
kind: BigUInt {
index: StatePartIndex<BigSlots>(138),
ty: UInt<4>,
},
state: 0xf,
last_state: 0xf,
},
SimTrace {
id: TraceScalarId(127),
kind: BigBool {
index: StatePartIndex<BigSlots>(139),
},
state: 0x1,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(128),
kind: BigClock {
index: StatePartIndex<BigSlots>(140),
},
state: 0x0,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(129),
kind: BigBool {
index: StatePartIndex<BigSlots>(141),
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(130),
kind: BigUInt {
index: StatePartIndex<BigSlots>(142),
ty: UInt<4>,
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(131),
kind: BigBool {
index: StatePartIndex<BigSlots>(143),
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(132),
kind: BigClock {
index: StatePartIndex<BigSlots>(144),
},
state: 0x0,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(133),
kind: BigBool {
index: StatePartIndex<BigSlots>(145),
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(134),
kind: BigBool {
index: StatePartIndex<BigSlots>(146),
},
state: 0x1,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(135),
kind: BigUInt {
index: StatePartIndex<BigSlots>(149),
ty: UInt<4>,
},
state: 0xf,
last_state: 0xf,
},
SimTrace {
id: TraceScalarId(136),
kind: BigBool {
index: StatePartIndex<BigSlots>(150),
},
state: 0x1,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(137),
kind: BigClock {
index: StatePartIndex<BigSlots>(151),
},
state: 0x0,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(138),
kind: BigBool {
index: StatePartIndex<BigSlots>(152),
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(139),
kind: BigUInt {
index: StatePartIndex<BigSlots>(153),
ty: UInt<4>,
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(140),
kind: BigBool {
index: StatePartIndex<BigSlots>(154),
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(141),
kind: BigClock {
index: StatePartIndex<BigSlots>(155),
},
state: 0x0,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(142),
kind: BigBool {
index: StatePartIndex<BigSlots>(156),
},
state: 0x0,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(143),
kind: BigBool {
index: StatePartIndex<BigSlots>(157),
},
state: 0x1,
last_state: 0x1,
},
],
trace_memories: {
StatePartIndex<Memories>(0): TraceMem {
id: TraceMemoryId(0),
name: "mem_0",
stride: 1,
element_type: TraceBool {
location: TraceMemoryLocation {
id: TraceMemoryId(0),
depth: 16,
stride: 1,
start: 0,
len: 1,
},
name: "mem_0",
flow: Duplex,
},
ports: [
TraceMemPort {
name: "r0",
bundle: TraceBundle {
name: "r0",
fields: [
TraceUInt {
location: TraceScalarId(72),
name: "addr",
ty: UInt<4>,
flow: Sink,
},
TraceBool {
location: TraceScalarId(73),
name: "en",
flow: Sink,
},
TraceClock {
location: TraceScalarId(74),
name: "clk",
flow: Sink,
},
TraceBool {
location: TraceScalarId(75),
name: "data",
flow: Source,
},
],
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
#[hdl(flip)] /* offset = 6 */
data: Bool,
},
flow: Sink,
},
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
#[hdl(flip)] /* offset = 6 */
data: Bool,
},
},
TraceMemPort {
name: "w1",
bundle: TraceBundle {
name: "w1",
fields: [
TraceUInt {
location: TraceScalarId(76),
name: "addr",
ty: UInt<4>,
flow: Sink,
},
TraceBool {
location: TraceScalarId(77),
name: "en",
flow: Sink,
},
TraceClock {
location: TraceScalarId(78),
name: "clk",
flow: Sink,
},
TraceBool {
location: TraceScalarId(79),
name: "data",
flow: Sink,
},
TraceBool {
location: TraceScalarId(80),
name: "mask",
flow: Sink,
},
],
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
/* offset = 6 */
data: Bool,
/* offset = 7 */
mask: Bool,
},
flow: Sink,
},
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
/* offset = 6 */
data: Bool,
/* offset = 7 */
mask: Bool,
},
},
],
array_type: Array<Bool, 16>,
},
StatePartIndex<Memories>(1): TraceMem {
id: TraceMemoryId(1),
name: "mem_1",
stride: 1,
element_type: TraceBool {
location: TraceMemoryLocation {
id: TraceMemoryId(1),
depth: 16,
stride: 1,
start: 0,
len: 1,
},
name: "mem_1",
flow: Duplex,
},
ports: [
TraceMemPort {
name: "r0",
bundle: TraceBundle {
name: "r0",
fields: [
TraceUInt {
location: TraceScalarId(81),
name: "addr",
ty: UInt<4>,
flow: Sink,
},
TraceBool {
location: TraceScalarId(82),
name: "en",
flow: Sink,
},
TraceClock {
location: TraceScalarId(83),
name: "clk",
flow: Sink,
},
TraceBool {
location: TraceScalarId(84),
name: "data",
flow: Source,
},
],
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
#[hdl(flip)] /* offset = 6 */
data: Bool,
},
flow: Sink,
},
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
#[hdl(flip)] /* offset = 6 */
data: Bool,
},
},
TraceMemPort {
name: "w1",
bundle: TraceBundle {
name: "w1",
fields: [
TraceUInt {
location: TraceScalarId(85),
name: "addr",
ty: UInt<4>,
flow: Sink,
},
TraceBool {
location: TraceScalarId(86),
name: "en",
flow: Sink,
},
TraceClock {
location: TraceScalarId(87),
name: "clk",
flow: Sink,
},
TraceBool {
location: TraceScalarId(88),
name: "data",
flow: Sink,
},
TraceBool {
location: TraceScalarId(89),
name: "mask",
flow: Sink,
},
],
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
/* offset = 6 */
data: Bool,
/* offset = 7 */
mask: Bool,
},
flow: Sink,
},
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
/* offset = 6 */
data: Bool,
/* offset = 7 */
mask: Bool,
},
},
],
array_type: Array<Bool, 16>,
},
StatePartIndex<Memories>(2): TraceMem {
id: TraceMemoryId(2),
name: "mem_2",
stride: 1,
element_type: TraceBool {
location: TraceMemoryLocation {
id: TraceMemoryId(2),
depth: 16,
stride: 1,
start: 0,
len: 1,
},
name: "mem_2",
flow: Duplex,
},
ports: [
TraceMemPort {
name: "r0",
bundle: TraceBundle {
name: "r0",
fields: [
TraceUInt {
location: TraceScalarId(90),
name: "addr",
ty: UInt<4>,
flow: Sink,
},
TraceBool {
location: TraceScalarId(91),
name: "en",
flow: Sink,
},
TraceClock {
location: TraceScalarId(92),
name: "clk",
flow: Sink,
},
TraceBool {
location: TraceScalarId(93),
name: "data",
flow: Source,
},
],
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
#[hdl(flip)] /* offset = 6 */
data: Bool,
},
flow: Sink,
},
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
#[hdl(flip)] /* offset = 6 */
data: Bool,
},
},
TraceMemPort {
name: "w1",
bundle: TraceBundle {
name: "w1",
fields: [
TraceUInt {
location: TraceScalarId(94),
name: "addr",
ty: UInt<4>,
flow: Sink,
},
TraceBool {
location: TraceScalarId(95),
name: "en",
flow: Sink,
},
TraceClock {
location: TraceScalarId(96),
name: "clk",
flow: Sink,
},
TraceBool {
location: TraceScalarId(97),
name: "data",
flow: Sink,
},
TraceBool {
location: TraceScalarId(98),
name: "mask",
flow: Sink,
},
],
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
/* offset = 6 */
data: Bool,
/* offset = 7 */
mask: Bool,
},
flow: Sink,
},
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
/* offset = 6 */
data: Bool,
/* offset = 7 */
mask: Bool,
},
},
],
array_type: Array<Bool, 16>,
},
StatePartIndex<Memories>(3): TraceMem {
id: TraceMemoryId(3),
name: "mem_3",
stride: 1,
element_type: TraceBool {
location: TraceMemoryLocation {
id: TraceMemoryId(3),
depth: 16,
stride: 1,
start: 0,
len: 1,
},
name: "mem_3",
flow: Duplex,
},
ports: [
TraceMemPort {
name: "r0",
bundle: TraceBundle {
name: "r0",
fields: [
TraceUInt {
location: TraceScalarId(99),
name: "addr",
ty: UInt<4>,
flow: Sink,
},
TraceBool {
location: TraceScalarId(100),
name: "en",
flow: Sink,
},
TraceClock {
location: TraceScalarId(101),
name: "clk",
flow: Sink,
},
TraceBool {
location: TraceScalarId(102),
name: "data",
flow: Source,
},
],
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
#[hdl(flip)] /* offset = 6 */
data: Bool,
},
flow: Sink,
},
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
#[hdl(flip)] /* offset = 6 */
data: Bool,
},
},
TraceMemPort {
name: "w1",
bundle: TraceBundle {
name: "w1",
fields: [
TraceUInt {
location: TraceScalarId(103),
name: "addr",
ty: UInt<4>,
flow: Sink,
},
TraceBool {
location: TraceScalarId(104),
name: "en",
flow: Sink,
},
TraceClock {
location: TraceScalarId(105),
name: "clk",
flow: Sink,
},
TraceBool {
location: TraceScalarId(106),
name: "data",
flow: Sink,
},
TraceBool {
location: TraceScalarId(107),
name: "mask",
flow: Sink,
},
],
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
/* offset = 6 */
data: Bool,
/* offset = 7 */
mask: Bool,
},
flow: Sink,
},
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
/* offset = 6 */
data: Bool,
/* offset = 7 */
mask: Bool,
},
},
],
array_type: Array<Bool, 16>,
},
StatePartIndex<Memories>(4): TraceMem {
id: TraceMemoryId(4),
name: "mem_4",
stride: 1,
element_type: TraceBool {
location: TraceMemoryLocation {
id: TraceMemoryId(4),
depth: 16,
stride: 1,
start: 0,
len: 1,
},
name: "mem_4",
flow: Duplex,
},
ports: [
TraceMemPort {
name: "r0",
bundle: TraceBundle {
name: "r0",
fields: [
TraceUInt {
location: TraceScalarId(108),
name: "addr",
ty: UInt<4>,
flow: Sink,
},
TraceBool {
location: TraceScalarId(109),
name: "en",
flow: Sink,
},
TraceClock {
location: TraceScalarId(110),
name: "clk",
flow: Sink,
},
TraceBool {
location: TraceScalarId(111),
name: "data",
flow: Source,
},
],
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
#[hdl(flip)] /* offset = 6 */
data: Bool,
},
flow: Sink,
},
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
#[hdl(flip)] /* offset = 6 */
data: Bool,
},
},
TraceMemPort {
name: "w1",
bundle: TraceBundle {
name: "w1",
fields: [
TraceUInt {
location: TraceScalarId(112),
name: "addr",
ty: UInt<4>,
flow: Sink,
},
TraceBool {
location: TraceScalarId(113),
name: "en",
flow: Sink,
},
TraceClock {
location: TraceScalarId(114),
name: "clk",
flow: Sink,
},
TraceBool {
location: TraceScalarId(115),
name: "data",
flow: Sink,
},
TraceBool {
location: TraceScalarId(116),
name: "mask",
flow: Sink,
},
],
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
/* offset = 6 */
data: Bool,
/* offset = 7 */
mask: Bool,
},
flow: Sink,
},
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
/* offset = 6 */
data: Bool,
/* offset = 7 */
mask: Bool,
},
},
],
array_type: Array<Bool, 16>,
},
StatePartIndex<Memories>(5): TraceMem {
id: TraceMemoryId(5),
name: "mem_5",
stride: 1,
element_type: TraceBool {
location: TraceMemoryLocation {
id: TraceMemoryId(5),
depth: 16,
stride: 1,
start: 0,
len: 1,
},
name: "mem_5",
flow: Duplex,
},
ports: [
TraceMemPort {
name: "r0",
bundle: TraceBundle {
name: "r0",
fields: [
TraceUInt {
location: TraceScalarId(117),
name: "addr",
ty: UInt<4>,
flow: Sink,
},
TraceBool {
location: TraceScalarId(118),
name: "en",
flow: Sink,
},
TraceClock {
location: TraceScalarId(119),
name: "clk",
flow: Sink,
},
TraceBool {
location: TraceScalarId(120),
name: "data",
flow: Source,
},
],
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
#[hdl(flip)] /* offset = 6 */
data: Bool,
},
flow: Sink,
},
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
#[hdl(flip)] /* offset = 6 */
data: Bool,
},
},
TraceMemPort {
name: "w1",
bundle: TraceBundle {
name: "w1",
fields: [
TraceUInt {
location: TraceScalarId(121),
name: "addr",
ty: UInt<4>,
flow: Sink,
},
TraceBool {
location: TraceScalarId(122),
name: "en",
flow: Sink,
},
TraceClock {
location: TraceScalarId(123),
name: "clk",
flow: Sink,
},
TraceBool {
location: TraceScalarId(124),
name: "data",
flow: Sink,
},
TraceBool {
location: TraceScalarId(125),
name: "mask",
flow: Sink,
},
],
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
/* offset = 6 */
data: Bool,
/* offset = 7 */
mask: Bool,
},
flow: Sink,
},
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
/* offset = 6 */
data: Bool,
/* offset = 7 */
mask: Bool,
},
},
],
array_type: Array<Bool, 16>,
},
StatePartIndex<Memories>(6): TraceMem {
id: TraceMemoryId(6),
name: "mem_6",
stride: 1,
element_type: TraceBool {
location: TraceMemoryLocation {
id: TraceMemoryId(6),
depth: 16,
stride: 1,
start: 0,
len: 1,
},
name: "mem_6",
flow: Duplex,
},
ports: [
TraceMemPort {
name: "r0",
bundle: TraceBundle {
name: "r0",
fields: [
TraceUInt {
location: TraceScalarId(126),
name: "addr",
ty: UInt<4>,
flow: Sink,
},
TraceBool {
location: TraceScalarId(127),
name: "en",
flow: Sink,
},
TraceClock {
location: TraceScalarId(128),
name: "clk",
flow: Sink,
},
TraceBool {
location: TraceScalarId(129),
name: "data",
flow: Source,
},
],
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
#[hdl(flip)] /* offset = 6 */
data: Bool,
},
flow: Sink,
},
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
#[hdl(flip)] /* offset = 6 */
data: Bool,
},
},
TraceMemPort {
name: "w1",
bundle: TraceBundle {
name: "w1",
fields: [
TraceUInt {
location: TraceScalarId(130),
name: "addr",
ty: UInt<4>,
flow: Sink,
},
TraceBool {
location: TraceScalarId(131),
name: "en",
flow: Sink,
},
TraceClock {
location: TraceScalarId(132),
name: "clk",
flow: Sink,
},
TraceBool {
location: TraceScalarId(133),
name: "data",
flow: Sink,
},
TraceBool {
location: TraceScalarId(134),
name: "mask",
flow: Sink,
},
],
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
/* offset = 6 */
data: Bool,
/* offset = 7 */
mask: Bool,
},
flow: Sink,
},
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
/* offset = 6 */
data: Bool,
/* offset = 7 */
mask: Bool,
},
},
],
array_type: Array<Bool, 16>,
},
StatePartIndex<Memories>(7): TraceMem {
id: TraceMemoryId(7),
name: "mem_7",
stride: 1,
element_type: TraceBool {
location: TraceMemoryLocation {
id: TraceMemoryId(7),
depth: 16,
stride: 1,
start: 0,
len: 1,
},
name: "mem_7",
flow: Duplex,
},
ports: [
TraceMemPort {
name: "r0",
bundle: TraceBundle {
name: "r0",
fields: [
TraceUInt {
location: TraceScalarId(135),
name: "addr",
ty: UInt<4>,
flow: Sink,
},
TraceBool {
location: TraceScalarId(136),
name: "en",
flow: Sink,
},
TraceClock {
location: TraceScalarId(137),
name: "clk",
flow: Sink,
},
TraceBool {
location: TraceScalarId(138),
name: "data",
flow: Source,
},
],
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
#[hdl(flip)] /* offset = 6 */
data: Bool,
},
flow: Sink,
},
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
#[hdl(flip)] /* offset = 6 */
data: Bool,
},
},
TraceMemPort {
name: "w1",
bundle: TraceBundle {
name: "w1",
fields: [
TraceUInt {
location: TraceScalarId(139),
name: "addr",
ty: UInt<4>,
flow: Sink,
},
TraceBool {
location: TraceScalarId(140),
name: "en",
flow: Sink,
},
TraceClock {
location: TraceScalarId(141),
name: "clk",
flow: Sink,
},
TraceBool {
location: TraceScalarId(142),
name: "data",
flow: Sink,
},
TraceBool {
location: TraceScalarId(143),
name: "mask",
flow: Sink,
},
],
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
/* offset = 6 */
data: Bool,
/* offset = 7 */
mask: Bool,
},
flow: Sink,
},
ty: Bundle {
/* offset = 0 */
addr: UInt<4>,
/* offset = 4 */
en: Bool,
/* offset = 5 */
clk: Clock,
/* offset = 6 */
data: Bool,
/* offset = 7 */
mask: Bool,
},
},
],
array_type: Array<Bool, 16>,
},
},
trace_writers: [
Running(
VcdWriter {
finished_init: true,
timescale: 1 ps,
..
},
),
],
clocks_triggered: [
StatePartIndex<SmallSlots>(1),
StatePartIndex<SmallSlots>(6),
StatePartIndex<SmallSlots>(13),
StatePartIndex<SmallSlots>(18),
StatePartIndex<SmallSlots>(25),
StatePartIndex<SmallSlots>(30),
StatePartIndex<SmallSlots>(37),
StatePartIndex<SmallSlots>(42),
StatePartIndex<SmallSlots>(49),
StatePartIndex<SmallSlots>(54),
StatePartIndex<SmallSlots>(61),
StatePartIndex<SmallSlots>(66),
StatePartIndex<SmallSlots>(73),
StatePartIndex<SmallSlots>(78),
StatePartIndex<SmallSlots>(85),
StatePartIndex<SmallSlots>(90),
],
event_queue: EventQueue(EventQueueData {
instant: 38 μs,
events: {},
}),
waiting_sensitivity_sets_by_address: {},
waiting_sensitivity_sets_by_compiled_value: {},
..
}
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