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fayalite/crates/fayalite/tests/sim/expected/mod1.vcd

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$timescale 1 ps $end
$scope module mod1 $end
$scope struct o $end
$var wire 4 avK(^ i $end
$var wire 2 Q2~aG o $end
$var wire 2 DXK'| i2 $end
$var wire 4 cPuix o2 $end
$upscope $end
$scope struct child $end
$var wire 4 ($5K7 i $end
$var wire 2 %6Wv" o $end
$var wire 2 +|-AU i2 $end
$var wire 4 Hw?%j o2 $end
$upscope $end
$scope module mod1_child $end
$var wire 4 4}s%= i $end
$var wire 2 }IY?g o $end
$var wire 2 of42K i2 $end
$var wire 4 D9]&= o2 $end
$upscope $end
$upscope $end
$enddefinitions $end
$dumpvars
b11 avK(^
b11 Q2~aG
b10 DXK'|
b1110 cPuix
b11 4}s%=
b11 }IY?g
b10 of42K
b1110 D9]&=
b11 ($5K7
b11 %6Wv"
b10 +|-AU
b1110 Hw?%j
$end
#1000000
b1010 avK(^
b10 Q2~aG
b1111 cPuix
b1010 4}s%=
b10 }IY?g
b1111 D9]&=
b1010 ($5K7
b10 %6Wv"
b1111 Hw?%j
#2000000