Jacob Lifshay d4d9706798 reimplement fayalite::formal and add support to the simulator ... Add support to the simulator for running hdl asserts/assumes and being able to write to the formal global clock/reset and all any/all_const/seq that are used. This allows you to use the exact same HDL code for running a simulation and for running a formal proof.		2026-06-05 00:56:24 -07:00
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expected	fayalite::testing: add checked_vcd_output!()	2026-06-05 00:35:19 -07:00
sim/expected	reimplement fayalite::formal and add support to the simulator	2026-06-05 00:56:24 -07:00
ui	Add .to_trace_as_string() and clean up code	2026-05-14 22:13:31 -07:00
formal.rs	move FormalMode to crate::testing and add to prelude	2025-10-24 00:14:04 -07:00
hdl_types.rs	silence warning for enums with only one variant	2026-02-23 16:07:05 -08:00
hdl_types_fmt.rs	add support for custom debug/display formatting of #[hdl] structs/enums	2026-04-30 23:10:49 -07:00
module.rs	reimplement fayalite::formal and add support to the simulator	2026-06-05 00:56:24 -07:00
sim.rs	reimplement fayalite::formal and add support to the simulator	2026-06-05 00:56:24 -07:00
ui.rs	initial public commit	2024-06-10 23:09:13 -07:00