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fayalite
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libre-chip/fayalite
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cdd84953d0
fayalite
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crates
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fayalite
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Jacob Lifshay
cdd84953d0
support unknown trait bounds in type parameters
2025-02-13 18:35:30 -08:00
..
sim
/expected
sim: fix "label address not set" bug when the last Assignment is conditional
2025-01-15 19:04:40 -08:00
ui
support #[hdl] type aliases
2024-10-30 20:47:10 -07:00
formal.rs
add module exercising formal verification of memories
2024-12-08 17:13:26 -03:00
hdl_types.rs
support #[hdl] type aliases
2024-10-30 20:47:10 -07:00
module.rs
support unknown trait bounds in type parameters
2025-02-13 18:35:30 -08:00
sim.rs
sim: fix "label address not set" bug when the last Assignment is conditional
2025-01-15 19:04:40 -08:00
ui.rs
initial public commit
2024-06-10 23:09:13 -07:00