forked from libre-chip/fayalite
810 lines
No EOL
32 KiB
Text
810 lines
No EOL
32 KiB
Text
Simulation {
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state: State {
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insns: Insns {
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state_layout: StateLayout {
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ty: TypeLayout {
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small_slots: StatePartLayout<SmallSlots> {
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len: 0,
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debug_data: [],
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..
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},
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big_slots: StatePartLayout<BigSlots> {
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len: 17,
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debug_data: [
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SlotDebugData {
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name: "InstantiatedModule(mod1: mod1).mod1::o.i",
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ty: UInt<4>,
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},
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SlotDebugData {
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name: "InstantiatedModule(mod1: mod1).mod1::o.o",
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ty: SInt<2>,
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},
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SlotDebugData {
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name: "InstantiatedModule(mod1: mod1).mod1::o.i2",
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ty: SInt<2>,
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},
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SlotDebugData {
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name: "InstantiatedModule(mod1: mod1).mod1::o.o2",
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ty: UInt<4>,
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},
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SlotDebugData {
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name: "InstantiatedModule(mod1: mod1).mod1::child.i",
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ty: UInt<4>,
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},
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SlotDebugData {
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name: "InstantiatedModule(mod1: mod1).mod1::child.o",
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ty: SInt<2>,
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},
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SlotDebugData {
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name: "InstantiatedModule(mod1: mod1).mod1::child.i2",
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ty: SInt<2>,
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},
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SlotDebugData {
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name: "InstantiatedModule(mod1: mod1).mod1::child.o2",
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ty: UInt<4>,
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},
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SlotDebugData {
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name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i",
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ty: UInt<4>,
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},
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SlotDebugData {
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name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o",
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ty: SInt<2>,
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},
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SlotDebugData {
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name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i2",
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ty: SInt<2>,
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},
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SlotDebugData {
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name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2",
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ty: UInt<4>,
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},
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SlotDebugData {
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name: "",
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ty: SInt<2>,
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},
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SlotDebugData {
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name: "",
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ty: UInt<4>,
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},
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SlotDebugData {
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name: "",
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ty: UInt<4>,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: UInt<4>,
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},
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],
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..
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},
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},
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memories: StatePartLayout<Memories> {
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len: 0,
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debug_data: [],
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layout_data: [],
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..
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},
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},
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insns: [
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// at: module-XXXXXXXXXX.rs:4:1
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0: Copy {
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dest: StatePartIndex<BigSlots>(6), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i2", ty: SInt<2> },
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src: StatePartIndex<BigSlots>(2), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.i2", ty: SInt<2> },
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},
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1: Copy {
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dest: StatePartIndex<BigSlots>(4), // (0xa) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i", ty: UInt<4> },
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src: StatePartIndex<BigSlots>(0), // (0xa) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.i", ty: UInt<4> },
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},
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// at: module-XXXXXXXXXX.rs:2:1
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2: Copy {
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dest: StatePartIndex<BigSlots>(10), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i2", ty: SInt<2> },
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src: StatePartIndex<BigSlots>(6), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i2", ty: SInt<2> },
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},
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3: Copy {
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dest: StatePartIndex<BigSlots>(8), // (0xa) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> },
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src: StatePartIndex<BigSlots>(4), // (0xa) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i", ty: UInt<4> },
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},
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// at: module-XXXXXXXXXX-2.rs:1:1
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4: Const {
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dest: StatePartIndex<BigSlots>(16), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
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value: 0xf,
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},
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5: Const {
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dest: StatePartIndex<BigSlots>(14), // (0x5) SlotDebugData { name: "", ty: UInt<4> },
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value: 0x5,
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},
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6: CmpLt {
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dest: StatePartIndex<BigSlots>(15), // (0x1) SlotDebugData { name: "", ty: Bool },
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lhs: StatePartIndex<BigSlots>(14), // (0x5) SlotDebugData { name: "", ty: UInt<4> },
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rhs: StatePartIndex<BigSlots>(8), // (0xa) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> },
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},
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7: CastToUInt {
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dest: StatePartIndex<BigSlots>(13), // (0xe) SlotDebugData { name: "", ty: UInt<4> },
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src: StatePartIndex<BigSlots>(10), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i2", ty: SInt<2> },
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dest_width: 4,
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},
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// at: module-XXXXXXXXXX-2.rs:7:1
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8: Copy {
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dest: StatePartIndex<BigSlots>(11), // (0xf) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> },
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src: StatePartIndex<BigSlots>(13), // (0xe) SlotDebugData { name: "", ty: UInt<4> },
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},
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// at: module-XXXXXXXXXX-2.rs:8:1
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9: BranchIfZero {
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target: 11,
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value: StatePartIndex<BigSlots>(15), // (0x1) SlotDebugData { name: "", ty: Bool },
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},
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// at: module-XXXXXXXXXX-2.rs:9:1
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10: Copy {
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dest: StatePartIndex<BigSlots>(11), // (0xf) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> },
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src: StatePartIndex<BigSlots>(16), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
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},
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// at: module-XXXXXXXXXX.rs:2:1
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11: Copy {
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dest: StatePartIndex<BigSlots>(7), // (0xf) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o2", ty: UInt<4> },
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src: StatePartIndex<BigSlots>(11), // (0xf) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> },
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},
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// at: module-XXXXXXXXXX.rs:4:1
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12: Copy {
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dest: StatePartIndex<BigSlots>(3), // (0xf) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.o2", ty: UInt<4> },
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src: StatePartIndex<BigSlots>(7), // (0xf) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o2", ty: UInt<4> },
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},
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// at: module-XXXXXXXXXX-2.rs:1:1
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13: CastToSInt {
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dest: StatePartIndex<BigSlots>(12), // (-0x2) SlotDebugData { name: "", ty: SInt<2> },
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src: StatePartIndex<BigSlots>(8), // (0xa) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> },
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dest_width: 2,
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},
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// at: module-XXXXXXXXXX-2.rs:6:1
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14: Copy {
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dest: StatePartIndex<BigSlots>(9), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o", ty: SInt<2> },
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src: StatePartIndex<BigSlots>(12), // (-0x2) SlotDebugData { name: "", ty: SInt<2> },
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},
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// at: module-XXXXXXXXXX.rs:2:1
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15: Copy {
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dest: StatePartIndex<BigSlots>(5), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o", ty: SInt<2> },
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src: StatePartIndex<BigSlots>(9), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o", ty: SInt<2> },
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},
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// at: module-XXXXXXXXXX.rs:4:1
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16: Copy {
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dest: StatePartIndex<BigSlots>(1), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.o", ty: SInt<2> },
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src: StatePartIndex<BigSlots>(5), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o", ty: SInt<2> },
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},
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// at: module-XXXXXXXXXX.rs:1:1
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17: Return,
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],
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..
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},
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pc: 17,
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memory_write_log: [],
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memories: StatePart {
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value: [],
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},
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small_slots: StatePart {
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value: [],
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},
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big_slots: StatePart {
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value: [
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10,
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-2,
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-2,
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15,
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10,
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-2,
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-2,
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15,
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10,
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-2,
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-2,
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15,
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-2,
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14,
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5,
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1,
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15,
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],
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},
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},
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io: Instance {
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name: <simulator>::mod1,
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instantiated: Module {
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name: mod1,
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..
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},
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},
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uninitialized_inputs: {},
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io_targets: {
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Instance {
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name: <simulator>::mod1,
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instantiated: Module {
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name: mod1,
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..
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},
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}.o: CompiledValue {
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layout: CompiledTypeLayout {
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ty: Bundle {
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#[hdl(flip)] /* offset = 0 */
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i: UInt<4>,
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/* offset = 4 */
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o: SInt<2>,
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#[hdl(flip)] /* offset = 6 */
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i2: SInt<2>,
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/* offset = 8 */
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o2: UInt<4>,
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},
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layout: TypeLayout {
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small_slots: StatePartLayout<SmallSlots> {
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len: 0,
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debug_data: [],
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..
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},
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big_slots: StatePartLayout<BigSlots> {
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len: 4,
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debug_data: [
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SlotDebugData {
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name: "InstantiatedModule(mod1: mod1).mod1::o.i",
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ty: UInt<4>,
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},
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SlotDebugData {
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name: "InstantiatedModule(mod1: mod1).mod1::o.o",
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ty: SInt<2>,
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},
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SlotDebugData {
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name: "InstantiatedModule(mod1: mod1).mod1::o.i2",
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ty: SInt<2>,
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},
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SlotDebugData {
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name: "InstantiatedModule(mod1: mod1).mod1::o.o2",
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ty: UInt<4>,
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},
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],
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..
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},
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},
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body: Bundle {
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fields: [
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CompiledBundleField {
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offset: TypeIndex {
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small_slots: StatePartIndex<SmallSlots>(0),
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big_slots: StatePartIndex<BigSlots>(0),
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},
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ty: CompiledTypeLayout {
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ty: UInt<4>,
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layout: TypeLayout {
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small_slots: StatePartLayout<SmallSlots> {
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len: 0,
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debug_data: [],
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..
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},
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big_slots: StatePartLayout<BigSlots> {
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len: 1,
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debug_data: [
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SlotDebugData {
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name: "",
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ty: UInt<4>,
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},
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],
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..
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},
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},
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body: Scalar,
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},
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},
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CompiledBundleField {
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offset: TypeIndex {
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small_slots: StatePartIndex<SmallSlots>(0),
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big_slots: StatePartIndex<BigSlots>(1),
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},
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ty: CompiledTypeLayout {
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ty: SInt<2>,
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layout: TypeLayout {
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small_slots: StatePartLayout<SmallSlots> {
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len: 0,
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debug_data: [],
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..
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},
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big_slots: StatePartLayout<BigSlots> {
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len: 1,
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debug_data: [
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SlotDebugData {
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name: "",
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ty: SInt<2>,
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},
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],
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..
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},
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},
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body: Scalar,
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},
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},
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CompiledBundleField {
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offset: TypeIndex {
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small_slots: StatePartIndex<SmallSlots>(0),
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big_slots: StatePartIndex<BigSlots>(2),
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},
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ty: CompiledTypeLayout {
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ty: SInt<2>,
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layout: TypeLayout {
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small_slots: StatePartLayout<SmallSlots> {
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len: 0,
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debug_data: [],
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..
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},
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big_slots: StatePartLayout<BigSlots> {
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len: 1,
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debug_data: [
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SlotDebugData {
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name: "",
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ty: SInt<2>,
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},
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],
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..
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},
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},
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body: Scalar,
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},
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},
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CompiledBundleField {
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offset: TypeIndex {
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small_slots: StatePartIndex<SmallSlots>(0),
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big_slots: StatePartIndex<BigSlots>(3),
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},
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ty: CompiledTypeLayout {
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ty: UInt<4>,
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layout: TypeLayout {
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small_slots: StatePartLayout<SmallSlots> {
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len: 0,
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debug_data: [],
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..
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},
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big_slots: StatePartLayout<BigSlots> {
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len: 1,
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debug_data: [
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SlotDebugData {
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name: "",
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ty: UInt<4>,
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},
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],
|
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..
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},
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},
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body: Scalar,
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},
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},
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],
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},
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},
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range: TypeIndexRange {
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small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
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big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 4 },
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},
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write: None,
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},
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Instance {
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name: <simulator>::mod1,
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instantiated: Module {
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name: mod1,
|
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..
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},
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}.o.i: CompiledValue {
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layout: CompiledTypeLayout {
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ty: UInt<4>,
|
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layout: TypeLayout {
|
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small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
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},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
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SlotDebugData {
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name: "",
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ty: UInt<4>,
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},
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],
|
|
..
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},
|
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},
|
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body: Scalar,
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},
|
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range: TypeIndexRange {
|
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small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
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big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
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},
|
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write: None,
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},
|
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Instance {
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name: <simulator>::mod1,
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instantiated: Module {
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name: mod1,
|
|
..
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},
|
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}.o.i2: CompiledValue {
|
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layout: CompiledTypeLayout {
|
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ty: SInt<2>,
|
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layout: TypeLayout {
|
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small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
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|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
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name: "",
|
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ty: SInt<2>,
|
|
},
|
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],
|
|
..
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|
},
|
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},
|
|
body: Scalar,
|
|
},
|
|
range: TypeIndexRange {
|
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small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
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big_slots: StatePartIndexRange<BigSlots> { start: 2, len: 1 },
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},
|
|
write: None,
|
|
},
|
|
Instance {
|
|
name: <simulator>::mod1,
|
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instantiated: Module {
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name: mod1,
|
|
..
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},
|
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}.o.o: CompiledValue {
|
|
layout: CompiledTypeLayout {
|
|
ty: SInt<2>,
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
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|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "",
|
|
ty: SInt<2>,
|
|
},
|
|
],
|
|
..
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|
},
|
|
},
|
|
body: Scalar,
|
|
},
|
|
range: TypeIndexRange {
|
|
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
|
big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
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|
},
|
|
write: None,
|
|
},
|
|
Instance {
|
|
name: <simulator>::mod1,
|
|
instantiated: Module {
|
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name: mod1,
|
|
..
|
|
},
|
|
}.o.o2: CompiledValue {
|
|
layout: CompiledTypeLayout {
|
|
ty: UInt<4>,
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "",
|
|
ty: UInt<4>,
|
|
},
|
|
],
|
|
..
|
|
},
|
|
},
|
|
body: Scalar,
|
|
},
|
|
range: TypeIndexRange {
|
|
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
|
big_slots: StatePartIndexRange<BigSlots> { start: 3, len: 1 },
|
|
},
|
|
write: None,
|
|
},
|
|
},
|
|
made_initial_step: true,
|
|
needs_settle: false,
|
|
trace_decls: TraceModule {
|
|
name: "mod1",
|
|
children: [
|
|
TraceModuleIO {
|
|
name: "o",
|
|
child: TraceBundle {
|
|
name: "o",
|
|
fields: [
|
|
TraceUInt {
|
|
location: TraceScalarId(0),
|
|
name: "i",
|
|
ty: UInt<4>,
|
|
flow: Source,
|
|
},
|
|
TraceSInt {
|
|
location: TraceScalarId(1),
|
|
name: "o",
|
|
ty: SInt<2>,
|
|
flow: Sink,
|
|
},
|
|
TraceSInt {
|
|
location: TraceScalarId(2),
|
|
name: "i2",
|
|
ty: SInt<2>,
|
|
flow: Source,
|
|
},
|
|
TraceUInt {
|
|
location: TraceScalarId(3),
|
|
name: "o2",
|
|
ty: UInt<4>,
|
|
flow: Sink,
|
|
},
|
|
],
|
|
ty: Bundle {
|
|
#[hdl(flip)] /* offset = 0 */
|
|
i: UInt<4>,
|
|
/* offset = 4 */
|
|
o: SInt<2>,
|
|
#[hdl(flip)] /* offset = 6 */
|
|
i2: SInt<2>,
|
|
/* offset = 8 */
|
|
o2: UInt<4>,
|
|
},
|
|
flow: Sink,
|
|
},
|
|
ty: Bundle {
|
|
#[hdl(flip)] /* offset = 0 */
|
|
i: UInt<4>,
|
|
/* offset = 4 */
|
|
o: SInt<2>,
|
|
#[hdl(flip)] /* offset = 6 */
|
|
i2: SInt<2>,
|
|
/* offset = 8 */
|
|
o2: UInt<4>,
|
|
},
|
|
flow: Sink,
|
|
},
|
|
TraceInstance {
|
|
name: "child",
|
|
instance_io: TraceBundle {
|
|
name: "child",
|
|
fields: [
|
|
TraceUInt {
|
|
location: TraceScalarId(8),
|
|
name: "i",
|
|
ty: UInt<4>,
|
|
flow: Sink,
|
|
},
|
|
TraceSInt {
|
|
location: TraceScalarId(9),
|
|
name: "o",
|
|
ty: SInt<2>,
|
|
flow: Source,
|
|
},
|
|
TraceSInt {
|
|
location: TraceScalarId(10),
|
|
name: "i2",
|
|
ty: SInt<2>,
|
|
flow: Sink,
|
|
},
|
|
TraceUInt {
|
|
location: TraceScalarId(11),
|
|
name: "o2",
|
|
ty: UInt<4>,
|
|
flow: Source,
|
|
},
|
|
],
|
|
ty: Bundle {
|
|
#[hdl(flip)] /* offset = 0 */
|
|
i: UInt<4>,
|
|
/* offset = 4 */
|
|
o: SInt<2>,
|
|
#[hdl(flip)] /* offset = 6 */
|
|
i2: SInt<2>,
|
|
/* offset = 8 */
|
|
o2: UInt<4>,
|
|
},
|
|
flow: Source,
|
|
},
|
|
module: TraceModule {
|
|
name: "mod1_child",
|
|
children: [
|
|
TraceModuleIO {
|
|
name: "i",
|
|
child: TraceUInt {
|
|
location: TraceScalarId(4),
|
|
name: "i",
|
|
ty: UInt<4>,
|
|
flow: Source,
|
|
},
|
|
ty: UInt<4>,
|
|
flow: Source,
|
|
},
|
|
TraceModuleIO {
|
|
name: "o",
|
|
child: TraceSInt {
|
|
location: TraceScalarId(5),
|
|
name: "o",
|
|
ty: SInt<2>,
|
|
flow: Sink,
|
|
},
|
|
ty: SInt<2>,
|
|
flow: Sink,
|
|
},
|
|
TraceModuleIO {
|
|
name: "i2",
|
|
child: TraceSInt {
|
|
location: TraceScalarId(6),
|
|
name: "i2",
|
|
ty: SInt<2>,
|
|
flow: Source,
|
|
},
|
|
ty: SInt<2>,
|
|
flow: Source,
|
|
},
|
|
TraceModuleIO {
|
|
name: "o2",
|
|
child: TraceUInt {
|
|
location: TraceScalarId(7),
|
|
name: "o2",
|
|
ty: UInt<4>,
|
|
flow: Sink,
|
|
},
|
|
ty: UInt<4>,
|
|
flow: Sink,
|
|
},
|
|
],
|
|
},
|
|
ty: Bundle {
|
|
#[hdl(flip)] /* offset = 0 */
|
|
i: UInt<4>,
|
|
/* offset = 4 */
|
|
o: SInt<2>,
|
|
#[hdl(flip)] /* offset = 6 */
|
|
i2: SInt<2>,
|
|
/* offset = 8 */
|
|
o2: UInt<4>,
|
|
},
|
|
},
|
|
],
|
|
},
|
|
traces: [
|
|
SimTrace {
|
|
id: TraceScalarId(0),
|
|
kind: BigUInt {
|
|
index: StatePartIndex<BigSlots>(0),
|
|
ty: UInt<4>,
|
|
},
|
|
state: 0xa,
|
|
last_state: 0x3,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(1),
|
|
kind: BigSInt {
|
|
index: StatePartIndex<BigSlots>(1),
|
|
ty: SInt<2>,
|
|
},
|
|
state: 0x2,
|
|
last_state: 0x3,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(2),
|
|
kind: BigSInt {
|
|
index: StatePartIndex<BigSlots>(2),
|
|
ty: SInt<2>,
|
|
},
|
|
state: 0x2,
|
|
last_state: 0x2,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(3),
|
|
kind: BigUInt {
|
|
index: StatePartIndex<BigSlots>(3),
|
|
ty: UInt<4>,
|
|
},
|
|
state: 0xf,
|
|
last_state: 0xe,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(4),
|
|
kind: BigUInt {
|
|
index: StatePartIndex<BigSlots>(8),
|
|
ty: UInt<4>,
|
|
},
|
|
state: 0xa,
|
|
last_state: 0x3,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(5),
|
|
kind: BigSInt {
|
|
index: StatePartIndex<BigSlots>(9),
|
|
ty: SInt<2>,
|
|
},
|
|
state: 0x2,
|
|
last_state: 0x3,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(6),
|
|
kind: BigSInt {
|
|
index: StatePartIndex<BigSlots>(10),
|
|
ty: SInt<2>,
|
|
},
|
|
state: 0x2,
|
|
last_state: 0x2,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(7),
|
|
kind: BigUInt {
|
|
index: StatePartIndex<BigSlots>(11),
|
|
ty: UInt<4>,
|
|
},
|
|
state: 0xf,
|
|
last_state: 0xe,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(8),
|
|
kind: BigUInt {
|
|
index: StatePartIndex<BigSlots>(4),
|
|
ty: UInt<4>,
|
|
},
|
|
state: 0xa,
|
|
last_state: 0x3,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(9),
|
|
kind: BigSInt {
|
|
index: StatePartIndex<BigSlots>(5),
|
|
ty: SInt<2>,
|
|
},
|
|
state: 0x2,
|
|
last_state: 0x3,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(10),
|
|
kind: BigSInt {
|
|
index: StatePartIndex<BigSlots>(6),
|
|
ty: SInt<2>,
|
|
},
|
|
state: 0x2,
|
|
last_state: 0x2,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(11),
|
|
kind: BigUInt {
|
|
index: StatePartIndex<BigSlots>(7),
|
|
ty: UInt<4>,
|
|
},
|
|
state: 0xf,
|
|
last_state: 0xe,
|
|
},
|
|
],
|
|
trace_memories: {},
|
|
trace_writers: [
|
|
Running(
|
|
VcdWriter {
|
|
finished_init: true,
|
|
timescale: 1 ps,
|
|
..
|
|
},
|
|
),
|
|
],
|
|
instant: 2 μs,
|
|
clocks_triggered: [],
|
|
..
|
|
} |